On Tue, Apr 02, 2013 at 08:28:53AM +0300, Terje Bergström wrote:
> On 29.03.2013 23:46, Stephen Warren wrote:
> > On 03/28/2013 02:31 PM, Thierry Reding wrote:
> >> By default these clocks are children of pll_m, but in downstream kernels
> >> they are reparented to pll_c. While at it, decrease their frequencies to
> >> 300 MHz because the defaults aren't in the specified range.
> >>
> >> gr2d can reportedly run at much higher frequencies, but 300 MHz works
> >> and is a more conservative default.
> > 
> > Questions on this patch:
> > 
> > Do we need to do the same thing for Tegra30 and/or Tegra114?
> > 
> > Is 300MHz the right value?
> > 
> > I'm hoping that Peter, Prashant, and/or Terje can provide guidance here.
> 
> We need a patch for all SoC's.

I think we also need that for all host1x children as well. But I think
we can tackle those at the same time as driver support is added. Right
now only 2D and 3D have some form of user code.

> 2D can fail subtly with the too high clocks, even though most of the
> time it seems to be doing just fine.
> 
> In Tegra20, 300MHz is the max rate we drive 2D in. Later Tegras have a
> higher max clock, and in Tegra114 we drive it from a different PLL. But
> for all of them 300MHz and PLLC should be a working configuration. I
> haven't checked how we use PLLC in upstream, so I'm not 100% sure.

At least on Tegra30 (CardHu) I can see that the clocks are also children
of PLLC. I can add a similar hunk for Tegra30 to the patch. I have no
Tegra114 hardware available and none of the downstream kernel branches I
have seem to include Tegra114 support either so I can't check what's in
use there, but if you say it should be fine I can include that in the
patch as well.

Thierry