From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [PATCH 2/9] drm/i915: fix linetime_watermarks code
Date: Mon, 6 May 2013 14:43:20 +0100
Message-ID: <20130506134320.GA1985@cantiga.alporthouse.com>
References: <1367612625-4823-1-git-send-email-przanoni@gmail.com>
	<1367612625-4823-3-git-send-email-przanoni@gmail.com>
	<20130505071825.GA15274@cantiga.alporthouse.com>
	<CA+gsUGT7cntQj5uTh5Rt5ishCP-=w6DD4L32Vadc-p=yaJcJyA@mail.gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mga03.intel.com (mga03.intel.com [143.182.124.21])
	by gabe.freedesktop.org (Postfix) with ESMTP id A753EE5F49
	for <intel-gfx@lists.freedesktop.org>;
	Mon,  6 May 2013 06:43:23 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <CA+gsUGT7cntQj5uTh5Rt5ishCP-=w6DD4L32Vadc-p=yaJcJyA@mail.gmail.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Paulo Zanoni <przanoni@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Mon, May 06, 2013 at 10:13:33AM -0300, Paulo Zanoni wrote:
> 2013/5/5 Chris Wilson <chris@chris-wilson.co.uk>:
> > On Fri, May 03, 2013 at 05:23:38PM -0300, Paulo Zanoni wrote:
> >> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >>
> >> The spec says the linetime watermarks must be programmed before
> >> enabling any display low power watermarks, but we're currently
> >> updating the linetime watermarks after we call intel_update_watermarks
> >> (and only at crtc_mode_set, not at crtc_{enable,disable}). So IMHO the
> >> best way guarantee the linetime watermarks will be updated before the
> >> low power watermarks is inside the update_wm function, because it's
> >> the function that enables low power watermarks. And since Haswell is
> >> the only platform that has linetime watermarks, let's completely kill
> >> the "intel_update_linetime_watermarks" abstraction and just use the
> >> intel_update_watermarks abstraction by creating haswell_update_wm.
> >
> >> +static void haswell_update_wm(struct drm_device *dev)
> >> +{
> >> +     struct drm_i915_private *dev_priv = dev->dev_private;
> >> +     struct drm_crtc *crtc;
> >> +     enum pipe pipe;
> >> +
> >> +     for_each_pipe(pipe) {
> >> +             crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> >> +             haswell_update_linetime_wm(dev, crtc);
> >> +     }
> >
> > The LP watermarks are still enabled at this point.
> 
> Did you mean "they're not disabled yet"? Well, at least now we're
> programming the linetime registers _before_ we update the LP
> registers, and every time. If we want to be 100% spec-compliant
> without any intermediate steps then I guess we can discard this
> linetime series and merge it all inside the single patch that will
> fully implement haswell_update_wm. But it will be one single big
> patch. Just tell me which one you prefer.

Or you can just disable the 3 LP wm first before updating the linetime
wm.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre