From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 8/9] drm/i915: MCH_SSKPD is a 64 bit
 register on Haswell
Date: Mon, 20 May 2013 16:38:20 +0300
Message-ID: <20130520133820.GD14974@intel.com>
References: <1367612625-4823-1-git-send-email-przanoni@gmail.com>
	<1367612625-4823-9-git-send-email-przanoni@gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mga09.intel.com (mga09.intel.com [134.134.136.24])
	by gabe.freedesktop.org (Postfix) with ESMTP id 1CE85E5DE3
	for <intel-gfx@lists.freedesktop.org>;
	Mon, 20 May 2013 06:38:24 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <1367612625-4823-9-git-send-email-przanoni@gmail.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Paulo Zanoni <przanoni@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Fri, May 03, 2013 at 05:23:44PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> =

> And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
> have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
> the new one is not zero.
> =

> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> =

> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel=
_pm.c
> index 59bac2e..b56de92 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4491,7 +4491,7 @@ void intel_init_pm(struct drm_device *dev)
>  			}
>  			dev_priv->display.init_clock_gating =3D ivybridge_init_clock_gating;
>  		} else if (IS_HASWELL(dev)) {
> -			if (SNB_READ_WM0_LATENCY()) {
> +			if (I915_READ64(MCH_SSKPD)) {
>  				dev_priv->display.update_wm =3D haswell_update_wm;
>  				dev_priv->display.update_sprite_wm =3D sandybridge_update_sprite_wm;
>  			} else {
> -- =

> 1.7.10.4
> =

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- =

Ville Syrj=E4l=E4
Intel OTC