From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 7/9] drm/i915: set the IPS linetime watermark Date: Mon, 20 May 2013 17:05:59 +0300 Message-ID: <20130520140559.GJ14974@intel.com> References: <1367612625-4823-1-git-send-email-przanoni@gmail.com> <1367612625-4823-8-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 46F09E5ED2 for ; Mon, 20 May 2013 07:06:03 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1367612625-4823-8-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Fri, May 03, 2013 at 05:23:43PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > = > Remove the "placeholder" comment and set the actual value described by > the specification. We still don't enable IPS, but it won't hurt to > already have the value set here. > = > While at it, fully set the register value instead of just masking the > values we're changing. > = > Signed-off-by: Paulo Zanoni Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_pm.c | 22 +++++++--------------- > 1 file changed, 7 insertions(+), 15 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 3ca020c..59bac2e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2022,7 +2022,7 @@ haswell_update_linetime_wm(struct drm_device *dev, = struct drm_crtc *crtc) > enum pipe pipe =3D intel_crtc->pipe; > struct drm_display_mode *mode =3D &intel_crtc->config.adjusted_mode; > int target_clock; > - u32 temp; > + u32 linetime, ips_linetime; > = > if (!intel_crtc_active(crtc)) { > I915_WRITE(PIPE_WM_LINETIME(pipe), 0); > @@ -2034,24 +2034,16 @@ haswell_update_linetime_wm(struct drm_device *dev= , struct drm_crtc *crtc) > else > target_clock =3D intel_crtc->config.adjusted_mode.clock; > = > - temp =3D I915_READ(PIPE_WM_LINETIME(pipe)); > - temp &=3D ~PIPE_WM_LINETIME_MASK; > - > /* The WM are computed with base on how long it takes to fill a single > * row at the given clock rate, multiplied by 8. > * */ > - temp |=3D PIPE_WM_LINETIME_TIME( > - DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, target_clock)); > - > - /* IPS watermarks are only used by pipe A, and are ignored by > - * pipes B and C. They are calculated similarly to the common > - * linetime values, except that we are using CD clock frequency > - * in MHz instead of pixel rate for the division. > - * > - * This is a placeholder for the IPS watermark calculation code. > - */ > + linetime =3D DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, target_clock); > + ips_linetime =3D DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, > + intel_ddi_get_cdclk_freq(dev_priv)); > = > - I915_WRITE(PIPE_WM_LINETIME(pipe), temp); > + I915_WRITE(PIPE_WM_LINETIME(pipe), > + PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | > + PIPE_WM_LINETIME_TIME(linetime)); > } > = > static void haswell_update_wm(struct drm_device *dev) > -- = > 1.7.10.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC