From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v2 1/3] drm/i915: Disable primary plane
 trickle feed for g4x
Date: Tue, 21 May 2013 17:43:53 +0300
Message-ID: <20130521144353.GD16772@intel.com>
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To: Daniel Vetter <daniel@ffwll.ch>
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On Tue, May 21, 2013 at 02:52:24PM +0200, Daniel Vetter wrote:
> On Tue, May 21, 2013 at 2:35 PM, Ville Syrj=E4l=E4
> <ville.syrjala@linux.intel.com> wrote:
> > On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrjala@linux.intel.com=
 wrote:
> >> From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> >>
> >> The docs say that the trickle feed disable bit is present (for primary
> >> planes only, not video sprites) on CTG, and that it must be set
> >> for ELK. Just set it for all g4x chipsets.
> >>
> >> v2: Do it in init_clock_gating too
> >
> > Actually I just noticed that we don't set up this stuff in
> > ironlake_init_clock_gating() either. Any opinions whether I should just
> > kill the per-plane trickle feed stuff from *_init_clock_gating(), or
> > should I add it to ironlake_init_clock_gating() as well?
> =

> This is a bit a crazy topic since conceptually it ties into the
> wm/pipe-config stuff. And fastboot will make this stuff rather
> interesting ... I expect that we'll eventually end up with a
> post_modeset_fixup stage to patch up all these little bits&pieces -
> fastboot would only call that one if possible.

I'd expect we do at least a set_base w/ fastboot, which would take care
of the per-plane trickle feed bit. But I don't care much either way at
this point. I'll post a quick patch for ironlake_init_clock_gating()
just to keep these things at least somewhat consistent...

-- =

Ville Syrj=E4l=E4
Intel OTC