From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35648) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ui1pL-0000WC-3x for qemu-devel@nongnu.org; Thu, 30 May 2013 08:19:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ui1pE-0008Rf-UW for qemu-devel@nongnu.org; Thu, 30 May 2013 08:19:31 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34180) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ui1pE-0008Ra-Mf for qemu-devel@nongnu.org; Thu, 30 May 2013 08:19:24 -0400 Date: Thu, 30 May 2013 15:19:50 +0300 From: "Michael S. Tsirkin" Message-ID: <20130530121950.GA12791@redhat.com> References: <1369911913-10934-1-git-send-email-mst@redhat.com> <1369911913-10934-3-git-send-email-mst@redhat.com> <51A7430D.7060102@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <51A7430D.7060102@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 2/5] pci: store PCI hole ranges in guestinfo structure List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: Anthony Liguori , qemu-devel@nongnu.org On Thu, May 30, 2013 at 02:16:13PM +0200, Gerd Hoffmann wrote: > Hi, > > > + } else { > > + guest_info->pci_info.w64.begin = 0x100000000ULL + above_4g_mem_size; > > + guest_info->pci_info.w64.end = guest_info->pci_info.w64.begin + > > + (0x1ULL << 62); > > Doesn't this give unaligned windows? PCI Bridge windows do not need to be size aligned. In any case, the windows are *exactly* as calculated by seabios - apparently it does not size-align windows either. > > + /* Set PCI window size the way seabios has always done it. */ > > + /* TODO: consider just starting at below_4g_mem_size */ > > Used to be that way. Was changed for alignment reasons (i.e. 1G window > starts at 1G border etc). Where's the alignment requirement coming from? > > cheers, > Gerd