From mboxrd@z Thu Jan  1 00:00:00 1970
From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Tue, 11 Jun 2013 17:28:29 +0200
Subject: [U-Boot] [PATCH v4 1/7] arm: add MMU/D-Cache support for
 Faraday cores
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	<CAK65tU6_Rea0imUrWqt_x7EFh8j+Ar8mjuwXUfSHDZm6rmEUZA@mail.gmail.com>
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Hi Kuo-Jung,

On Tue, 11 Jun 2013 11:09:57 +0800, Kuo-Jung Su <dantesu@gmail.com>
wrote:

> 2013/6/11 Albert ARIBAUD <albert.u.boot@aribaud.net>:
> > Hi Kuo-Jung,
> >
> > On Tue,  7 May 2013 14:25:07 +0800, Kuo-Jung Su <dantesu@gmail.com>
> > wrote:
> >
> >> diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
> >> index 5bbb0a0..5a13af5 100644
> >> --- a/arch/arm/include/asm/dma-mapping.h
> >> +++ b/arch/arm/include/asm/dma-mapping.h
> >> @@ -3,6 +3,9 @@
> >>   * Stelian Pop <stelian@popies.net>
> >>   * Lead Tech Design <www.leadtechdesign.com>
> >>   *
> >> + * (C) Copyright 2010
> >> + * Dante Su <dantesu@faraday-tech.com>
> >
> > Fix Copyright notices (dates) throughout the patch (and series as
> > needed).
> >
> 
> Got it, thanks.
> 
> >>   * See file CREDITS for list of people who contributed to this
> >>   * project.
> >>   *
> >> @@ -24,22 +27,76 @@
> >>  #ifndef __ASM_ARM_DMA_MAPPING_H
> >>  #define __ASM_ARM_DMA_MAPPING_H
> >>
> >> +#if defined(CONFIG_FARADAY) && !defined(CONFIG_SYS_DCACHE_OFF)
> >> +#include <asm/u-boot.h>
> >> +#include <asm/global_data.h>
> >> +#include <asm/io.h>
> >> +#include <malloc.h>
> >> +
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +#endif /* CONFIG_FARADAY && !CONFIG_SYS_DCACHE_OFF */
> >> +
> >>  enum dma_data_direction {
> >>       DMA_BIDIRECTIONAL       = 0,
> >>       DMA_TO_DEVICE           = 1,
> >>       DMA_FROM_DEVICE         = 2,
> >>  };
> >>
> >> -static void *dma_alloc_coherent(size_t len, unsigned long *handle)
> >> +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
> >>  {
> >> -     *handle = (unsigned long)malloc(len);
> >> +#if defined(CONFIG_FARADAY) && !defined(CONFIG_SYS_DCACHE_OFF)
> >> +     void *map, *va = memalign(ARCH_DMA_MINALIGN, len);
> >> +
> >> +     if (va && gd->arch.cpu_mmu) {
> >> +             invalidate_dcache_range((ulong)va, (ulong)va + len);
> >> +             map = map_physmem((phys_addr_t)va, len, MAP_NOCACHE);
> >> +             if (!map)
> >> +                     free(va);
> >> +             va = map;
> >> +     }
> >> +
> >> +     if (handle)
> >> +             *handle = virt_to_phys(va);
> >> +
> >> +     return va;
> >> +#else  /* CONFIG_FARADAY && !CONFIG_SYS_DCACHE_OFF */
> >> +     *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
> >>       return (void *)*handle;
> >
> > This is not identical to what the code was before the patch. Why the
> > difference?
> >
> 
> Yes, it's not identical to what the code was.
> 
> It was:
>     *handle = (unsigned long)malloc(len);
> But I think it should be
>     *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
> 
> Because even though the MMU/D-cache is off, some DMA engines still
> requires strict address alignment.
> 
> For example, the Faraday FTMAC110 & FTGMAC100 ether-net controllers
> expect the descriptors are always aligned to 16-bytes boundary.

Unless there exists an actual case where the current form causes an
issue, please leave it unchanged. And if it is needed, then please make
it a separate patch.

> Best wishes,
> Kuo-Jung Su

Amicalement,
-- 
Albert.