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Date: Thu, 4 Jul 2013 11:57:35 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: "Yan, Zheng" <zheng.z.yan@intel.com>
Cc: linux-kernel@vger.kernel.org, mingo@kernel.org, eranian@google.com,
        andi@firstfloor.org
Subject: Re: [PATCH v2 4/7] perf, x86: Save/resotre LBR stack during context
 switch
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References: <1372663387-11754-1-git-send-email-zheng.z.yan@intel.com>
 <1372663387-11754-5-git-send-email-zheng.z.yan@intel.com>
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On Mon, Jul 01, 2013 at 03:23:04PM +0800, Yan, Zheng wrote:
> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> @@ -185,6 +185,13 @@ void intel_pmu_lbr_reset(void)
>  		intel_pmu_lbr_reset_32();
>  	else
>  		intel_pmu_lbr_reset_64();
> +
> +	wrmsrl(x86_pmu.lbr_tos, 0);
> +}

I double checked; my SDM Jun 2013, Vol 3C 35-93 very explicitly states that
MSR_LASTBRANCH_TOS is a read-only MSR. And afaicr all previous times I checked
this it did say this too.