* [PATCH v1 00/24] add COMMON_CLK support for PowerPC MPC512x
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this series introduces support for the common clock framework (CCF,
COMMON_CLK Kconfig option) in the PowerPC based MPC512x platform, a
resulting debugfs clk_summary is at the end of the message after the
stats
although the series does touch several subsystems -- serial, spi, net
(can, fs_enet), mtd (nfc), usb, i2c, media (viu), and dts -- all of the
patches are strictly clock related, changes outside of the clock driver
in the mpc512x platform are rather small and local to probe and setup
the distribution was chosen such to not spam too many lists, yet reach
all the relevant maintainers (there appears to be no clk related list,
it's assumed that the clk API is ARM centric, which is why I send the
PowerPC related changes to the ARM list as well), but I'd be happy to
add more participants if necessary
it appears most appropriate to take this series through either the clk
or the powerpc trees after it has passed review and other subsystem
maintainers ACKed the clock setup related driver modifications --
splitting the series and taking the parts through several trees might
reorder the set (make drivers fail to see the device tree specs) or
would create unnecessary dependencies which need to get tracked upon
merges and might defer propagation (unless I missed something)
the series passes 'checkpatch.pl --strict' except for one warning which
cannot get resolved, since that either breaks compilation (the data type
is preset by the clk-provider.h API) or requires a cast which shadows
real mismatches:
WARNING: static const char * array should probably be static const char * const
#413: FILE: arch/powerpc/platforms/512x/clock-commonclk.c:335:
+static const char *parent_names_mux0[] = {
total: 0 errors, 1 warnings, 0 checks, 836 lines checked
Gerhard Sittig (24):
spi: mpc512x: prepare clocks before enabling them
serial: mpc512x: prepare clocks before enabling them
mtd: mpc5121_nfc: prepare clocks before enabling them
powerpc: mpc512x: array decl for MCLK registers in CCM
clk: wrap I/O access for improved portability
dts: mpc512x: prepare for preprocessor support
dts: mpc512x: introduce dt-bindings/clock/ header
dts: mpc512x: add clock related device tree specs
clk: mpc512x: introduce COMMON_CLK for MPC512x
dts: mpc512x: add clock specs for client lookups
net: can: mscan: add a comment on reg to idx mapping
net: can: mscan: make mpc512x code use common clock
spi: mpc512x: OF clock lookup, use the 'mclk' name
powerpc/mpc512x: improve DIU related clock setup
serial: mpc512x: OF clock lookup, use the 'mclk' name
clk: mpc512x: remove now obsolete clkdev registration
serial: mpc512x: setup the PSC FIFO clock as well
i2c: mpc: OF clock lookup for MPC512x
USB: fsl-mph-dr-of: OF clock lookup, prepare and enable
fs_enet: OF clock lookup (non-fatal), prepare and enable
[media] fsl-viu: OF clock lookup, prepare before enable
powerpc/fsl-pci: OF clock lookup, prepare before enable
clk: mpc512x: switch to COMMON_CLK, remove PPC_CLOCK
net: can: mscan: remove MPC512x non-COMMON_CLK code path
arch/powerpc/boot/dts/ac14xx.dts | 9 +-
arch/powerpc/boot/dts/include/dt-bindings | 1 +
arch/powerpc/boot/dts/mpc5121.dtsi | 94 ++-
arch/powerpc/boot/dts/mpc5121ads.dts | 2 +-
arch/powerpc/boot/dts/pdm360ng.dts | 2 +-
arch/powerpc/include/asm/mpc5121.h | 18 +-
arch/powerpc/platforms/512x/Kconfig | 2 +-
arch/powerpc/platforms/512x/Makefile | 3 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 762 ++++++++++++++++++++
arch/powerpc/platforms/512x/clock.c | 753 -------------------
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++--
arch/powerpc/sysdev/fsl_pci.c | 15 +
drivers/clk/clk-divider.c | 6 +-
drivers/clk/clk-gate.c | 6 +-
drivers/clk/clk-mux.c | 6 +-
drivers/i2c/busses/i2c-mpc.c | 9 +
drivers/media/platform/fsl-viu.c | 12 +-
drivers/mtd/nand/mpc5121_nfc.c | 4 +-
drivers/net/can/mscan/mpc5xxx_can.c | 234 +++---
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 27 +-
drivers/spi/spi-mpc512x-psc.c | 6 +-
drivers/tty/serial/mpc52xx_uart.c | 59 +-
drivers/usb/host/fsl-mph-dr-of.c | 24 +-
include/dt-bindings/clock/mpc512x-clock.h | 59 ++
include/linux/clk-provider.h | 33 +
include/linux/fs_enet_pd.h | 3 +
26 files changed, 1299 insertions(+), 1015 deletions(-)
create mode 120000 arch/powerpc/boot/dts/include/dt-bindings
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
delete mode 100644 arch/powerpc/platforms/512x/clock.c
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
$ uname -srm
Linux 3.11.0-rc1-00024-g25dc674 ppc
$ cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
ac97 0 0 24567000
spdif_rx_in 0 0 0
spdif_tx_in 0 0 0
psc_mclk_in 0 0 25000000
dummy 1 1 0
osc 1 1 25000000
ref 1 1 25000000
sys 9 9 320000000
spdif-mux0 0 0 320000000
spdif-en0 0 0 320000000
spdif_mclk_div 0 0 80000000
spdif_mclk_out 0 0 80000000
spdif_mclk 0 0 80000000
mscan3-mux0 1 1 320000000
mscan3-en0 1 1 320000000
mscan3_mclk_div 1 1 80000000
mscan3_mclk_out 1 1 80000000
mscan3_mclk 1 1 80000000
mscan2-mux0 1 1 320000000
mscan2-en0 1 1 320000000
mscan2_mclk_div 1 1 80000000
mscan2_mclk_out 1 1 80000000
mscan2_mclk 1 1 80000000
mscan1-mux0 1 1 320000000
mscan1-en0 1 1 320000000
mscan1_mclk_div 1 1 16000000
mscan1_mclk_out 1 1 16000000
mscan1_mclk 2 2 16000000
mscan0-mux0 1 1 320000000
mscan0-en0 1 1 320000000
mscan0_mclk_div 1 1 16000000
mscan0_mclk_out 1 1 16000000
mscan0_mclk 2 2 16000000
psc11-mux0 0 0 320000000
psc11-en0 0 0 320000000
psc11_mclk_div 0 0 80000000
psc11_mclk_out 0 0 80000000
psc11_mclk 0 0 80000000
psc10-mux0 0 0 320000000
psc10-en0 0 0 320000000
psc10_mclk_div 0 0 80000000
psc10_mclk_out 0 0 80000000
psc10_mclk 0 0 80000000
psc9-mux0 0 0 320000000
psc9-en0 0 0 320000000
psc9_mclk_div 0 0 80000000
psc9_mclk_out 0 0 80000000
psc9_mclk 0 0 80000000
psc8-mux0 0 0 320000000
psc8-en0 0 0 320000000
psc8_mclk_div 0 0 80000000
psc8_mclk_out 0 0 80000000
psc8_mclk 0 0 80000000
psc7-mux0 0 0 320000000
psc7-en0 0 0 320000000
psc7_mclk_div 0 0 80000000
psc7_mclk_out 0 0 80000000
psc7_mclk 0 0 80000000
psc6-mux0 0 0 320000000
psc6-en0 0 0 320000000
psc6_mclk_div 0 0 80000000
psc6_mclk_out 0 0 80000000
psc6_mclk 0 0 80000000
psc5-mux0 1 1 320000000
psc5-en0 1 1 320000000
psc5_mclk_div 1 1 80000000
psc5_mclk_out 1 1 80000000
psc5_mclk 1 1 80000000
psc4-mux0 1 1 320000000
psc4-en0 1 1 320000000
psc4_mclk_div 1 1 80000000
psc4_mclk_out 1 1 80000000
psc4_mclk 1 1 80000000
psc3-mux0 1 1 320000000
psc3-en0 1 1 320000000
psc3_mclk_div 1 1 80000000
psc3_mclk_out 1 1 80000000
psc3_mclk 1 1 80000000
psc2-mux0 0 0 320000000
psc2-en0 0 0 320000000
psc2_mclk_div 0 0 80000000
psc2_mclk_out 0 0 80000000
psc2_mclk 0 0 80000000
psc1-mux0 0 0 320000000
psc1-en0 0 0 320000000
psc1_mclk_div 0 0 80000000
psc1_mclk_out 0 0 80000000
psc1_mclk 0 0 80000000
psc0-mux0 0 0 320000000
psc0-en0 0 0 320000000
psc0_mclk_div 0 0 80000000
psc0_mclk_out 0 0 80000000
psc0_mclk 0 0 80000000
ddr-ug 1 1 160000000
ddr 1 1 160000000
csb 4 4 160000000
viu 0 0 160000000
iim 0 0 160000000
usb2 0 0 160000000
usb1 0 0 160000000
axe 0 0 160000000
pci-ug 0 0 26666666
pci 0 0 26666666
mbx-bus-ug 0 0 80000000
mbx-bus 0 0 80000000
mbx-ug 0 0 80000000
mbx 0 0 80000000
mbx-3d-ug 0 0 80000000
mbx-3d 0 0 80000000
e300 1 1 400000000
diu-x4 1 1 640000000
diu-ug 1 1 2509803
diu 2 2 2509803
sdhc-x4 1 1 640000000
sdhc-ug 1 1 53333333
sdhc-2 0 0 53333333
sdhc 1 1 53333333
ips 7 7 80000000
i2c 3 3 80000000
mem 1 1 80000000
fec 1 1 80000000
sata 0 0 80000000
psc-fifo 1 1 80000000
pata 0 0 80000000
lpc-ug 1 1 40000000
lpc 1 1 40000000
nfc-ug 0 0 40000000
nfc 0 0 40000000
--
1.7.10.4
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 00/24] add COMMON_CLK support for PowerPC MPC512x
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
this series introduces support for the common clock framework (CCF,
COMMON_CLK Kconfig option) in the PowerPC based MPC512x platform, a
resulting debugfs clk_summary is at the end of the message after the
stats
although the series does touch several subsystems -- serial, spi, net
(can, fs_enet), mtd (nfc), usb, i2c, media (viu), and dts -- all of the
patches are strictly clock related, changes outside of the clock driver
in the mpc512x platform are rather small and local to probe and setup
the distribution was chosen such to not spam too many lists, yet reach
all the relevant maintainers (there appears to be no clk related list,
it's assumed that the clk API is ARM centric, which is why I send the
PowerPC related changes to the ARM list as well), but I'd be happy to
add more participants if necessary
it appears most appropriate to take this series through either the clk
or the powerpc trees after it has passed review and other subsystem
maintainers ACKed the clock setup related driver modifications --
splitting the series and taking the parts through several trees might
reorder the set (make drivers fail to see the device tree specs) or
would create unnecessary dependencies which need to get tracked upon
merges and might defer propagation (unless I missed something)
the series passes 'checkpatch.pl --strict' except for one warning which
cannot get resolved, since that either breaks compilation (the data type
is preset by the clk-provider.h API) or requires a cast which shadows
real mismatches:
WARNING: static const char * array should probably be static const char * const
#413: FILE: arch/powerpc/platforms/512x/clock-commonclk.c:335:
+static const char *parent_names_mux0[] = {
total: 0 errors, 1 warnings, 0 checks, 836 lines checked
Gerhard Sittig (24):
spi: mpc512x: prepare clocks before enabling them
serial: mpc512x: prepare clocks before enabling them
mtd: mpc5121_nfc: prepare clocks before enabling them
powerpc: mpc512x: array decl for MCLK registers in CCM
clk: wrap I/O access for improved portability
dts: mpc512x: prepare for preprocessor support
dts: mpc512x: introduce dt-bindings/clock/ header
dts: mpc512x: add clock related device tree specs
clk: mpc512x: introduce COMMON_CLK for MPC512x
dts: mpc512x: add clock specs for client lookups
net: can: mscan: add a comment on reg to idx mapping
net: can: mscan: make mpc512x code use common clock
spi: mpc512x: OF clock lookup, use the 'mclk' name
powerpc/mpc512x: improve DIU related clock setup
serial: mpc512x: OF clock lookup, use the 'mclk' name
clk: mpc512x: remove now obsolete clkdev registration
serial: mpc512x: setup the PSC FIFO clock as well
i2c: mpc: OF clock lookup for MPC512x
USB: fsl-mph-dr-of: OF clock lookup, prepare and enable
fs_enet: OF clock lookup (non-fatal), prepare and enable
[media] fsl-viu: OF clock lookup, prepare before enable
powerpc/fsl-pci: OF clock lookup, prepare before enable
clk: mpc512x: switch to COMMON_CLK, remove PPC_CLOCK
net: can: mscan: remove MPC512x non-COMMON_CLK code path
arch/powerpc/boot/dts/ac14xx.dts | 9 +-
arch/powerpc/boot/dts/include/dt-bindings | 1 +
arch/powerpc/boot/dts/mpc5121.dtsi | 94 ++-
arch/powerpc/boot/dts/mpc5121ads.dts | 2 +-
arch/powerpc/boot/dts/pdm360ng.dts | 2 +-
arch/powerpc/include/asm/mpc5121.h | 18 +-
arch/powerpc/platforms/512x/Kconfig | 2 +-
arch/powerpc/platforms/512x/Makefile | 3 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 762 ++++++++++++++++++++
arch/powerpc/platforms/512x/clock.c | 753 -------------------
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++--
arch/powerpc/sysdev/fsl_pci.c | 15 +
drivers/clk/clk-divider.c | 6 +-
drivers/clk/clk-gate.c | 6 +-
drivers/clk/clk-mux.c | 6 +-
drivers/i2c/busses/i2c-mpc.c | 9 +
drivers/media/platform/fsl-viu.c | 12 +-
drivers/mtd/nand/mpc5121_nfc.c | 4 +-
drivers/net/can/mscan/mpc5xxx_can.c | 234 +++---
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 27 +-
drivers/spi/spi-mpc512x-psc.c | 6 +-
drivers/tty/serial/mpc52xx_uart.c | 59 +-
drivers/usb/host/fsl-mph-dr-of.c | 24 +-
include/dt-bindings/clock/mpc512x-clock.h | 59 ++
include/linux/clk-provider.h | 33 +
include/linux/fs_enet_pd.h | 3 +
26 files changed, 1299 insertions(+), 1015 deletions(-)
create mode 120000 arch/powerpc/boot/dts/include/dt-bindings
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
delete mode 100644 arch/powerpc/platforms/512x/clock.c
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
$ uname -srm
Linux 3.11.0-rc1-00024-g25dc674 ppc
$ cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
ac97 0 0 24567000
spdif_rx_in 0 0 0
spdif_tx_in 0 0 0
psc_mclk_in 0 0 25000000
dummy 1 1 0
osc 1 1 25000000
ref 1 1 25000000
sys 9 9 320000000
spdif-mux0 0 0 320000000
spdif-en0 0 0 320000000
spdif_mclk_div 0 0 80000000
spdif_mclk_out 0 0 80000000
spdif_mclk 0 0 80000000
mscan3-mux0 1 1 320000000
mscan3-en0 1 1 320000000
mscan3_mclk_div 1 1 80000000
mscan3_mclk_out 1 1 80000000
mscan3_mclk 1 1 80000000
mscan2-mux0 1 1 320000000
mscan2-en0 1 1 320000000
mscan2_mclk_div 1 1 80000000
mscan2_mclk_out 1 1 80000000
mscan2_mclk 1 1 80000000
mscan1-mux0 1 1 320000000
mscan1-en0 1 1 320000000
mscan1_mclk_div 1 1 16000000
mscan1_mclk_out 1 1 16000000
mscan1_mclk 2 2 16000000
mscan0-mux0 1 1 320000000
mscan0-en0 1 1 320000000
mscan0_mclk_div 1 1 16000000
mscan0_mclk_out 1 1 16000000
mscan0_mclk 2 2 16000000
psc11-mux0 0 0 320000000
psc11-en0 0 0 320000000
psc11_mclk_div 0 0 80000000
psc11_mclk_out 0 0 80000000
psc11_mclk 0 0 80000000
psc10-mux0 0 0 320000000
psc10-en0 0 0 320000000
psc10_mclk_div 0 0 80000000
psc10_mclk_out 0 0 80000000
psc10_mclk 0 0 80000000
psc9-mux0 0 0 320000000
psc9-en0 0 0 320000000
psc9_mclk_div 0 0 80000000
psc9_mclk_out 0 0 80000000
psc9_mclk 0 0 80000000
psc8-mux0 0 0 320000000
psc8-en0 0 0 320000000
psc8_mclk_div 0 0 80000000
psc8_mclk_out 0 0 80000000
psc8_mclk 0 0 80000000
psc7-mux0 0 0 320000000
psc7-en0 0 0 320000000
psc7_mclk_div 0 0 80000000
psc7_mclk_out 0 0 80000000
psc7_mclk 0 0 80000000
psc6-mux0 0 0 320000000
psc6-en0 0 0 320000000
psc6_mclk_div 0 0 80000000
psc6_mclk_out 0 0 80000000
psc6_mclk 0 0 80000000
psc5-mux0 1 1 320000000
psc5-en0 1 1 320000000
psc5_mclk_div 1 1 80000000
psc5_mclk_out 1 1 80000000
psc5_mclk 1 1 80000000
psc4-mux0 1 1 320000000
psc4-en0 1 1 320000000
psc4_mclk_div 1 1 80000000
psc4_mclk_out 1 1 80000000
psc4_mclk 1 1 80000000
psc3-mux0 1 1 320000000
psc3-en0 1 1 320000000
psc3_mclk_div 1 1 80000000
psc3_mclk_out 1 1 80000000
psc3_mclk 1 1 80000000
psc2-mux0 0 0 320000000
psc2-en0 0 0 320000000
psc2_mclk_div 0 0 80000000
psc2_mclk_out 0 0 80000000
psc2_mclk 0 0 80000000
psc1-mux0 0 0 320000000
psc1-en0 0 0 320000000
psc1_mclk_div 0 0 80000000
psc1_mclk_out 0 0 80000000
psc1_mclk 0 0 80000000
psc0-mux0 0 0 320000000
psc0-en0 0 0 320000000
psc0_mclk_div 0 0 80000000
psc0_mclk_out 0 0 80000000
psc0_mclk 0 0 80000000
ddr-ug 1 1 160000000
ddr 1 1 160000000
csb 4 4 160000000
viu 0 0 160000000
iim 0 0 160000000
usb2 0 0 160000000
usb1 0 0 160000000
axe 0 0 160000000
pci-ug 0 0 26666666
pci 0 0 26666666
mbx-bus-ug 0 0 80000000
mbx-bus 0 0 80000000
mbx-ug 0 0 80000000
mbx 0 0 80000000
mbx-3d-ug 0 0 80000000
mbx-3d 0 0 80000000
e300 1 1 400000000
diu-x4 1 1 640000000
diu-ug 1 1 2509803
diu 2 2 2509803
sdhc-x4 1 1 640000000
sdhc-ug 1 1 53333333
sdhc-2 0 0 53333333
sdhc 1 1 53333333
ips 7 7 80000000
i2c 3 3 80000000
mem 1 1 80000000
fec 1 1 80000000
sata 0 0 80000000
psc-fifo 1 1 80000000
pata 0 0 80000000
lpc-ug 1 1 40000000
lpc 1 1 40000000
nfc-ug 0 0 40000000
nfc 0 0 40000000
--
1.7.10.4
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
clocks need to get prepared before they can get enabled,
fix the MPC512x PSC SPI master's initialization
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
drivers/spi/spi-mpc512x-psc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 29fce6a..76b20ea 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -395,7 +395,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
sprintf(name, "psc%d_mclk", master->bus_num);
spiclk = clk_get(&master->dev, name);
- clk_enable(spiclk);
+ clk_prepare_enable(spiclk);
mps->mclk = clk_get_rate(spiclk);
clk_put(spiclk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
clocks need to get prepared before they can get enabled,
fix the MPC512x PSC SPI master's initialization
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/spi/spi-mpc512x-psc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 29fce6a..76b20ea 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -395,7 +395,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
sprintf(name, "psc%d_mclk", master->bus_num);
spiclk = clk_get(&master->dev, name);
- clk_enable(spiclk);
+ clk_prepare_enable(spiclk);
mps->mclk = clk_get_rate(spiclk);
clk_put(spiclk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
clocks need to get prepared before they can get enabled,
fix the MPC512x PSC SPI master's initialization
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/spi/spi-mpc512x-psc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 29fce6a..76b20ea 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -395,7 +395,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
sprintf(name, "psc%d_mclk", master->bus_num);
spiclk = clk_get(&master->dev, name);
- clk_enable(spiclk);
+ clk_prepare_enable(spiclk);
mps->mclk = clk_get_rate(spiclk);
clk_put(spiclk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 02/24] serial: mpc512x: prepare clocks before enabling them
2013-07-15 18:47 ` Gerhard Sittig
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
clocks need to get prepared before they can get enabled, and after
disabling them they can get unprepared
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/tty/serial/mpc52xx_uart.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index e1280a2..53c1093 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -636,9 +636,9 @@ static int mpc512x_psc_clock(struct uart_port *port, int enable)
dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
if (enable)
- clk_enable(psc_clk);
+ clk_prepare_enable(psc_clk);
else
- clk_disable(psc_clk);
+ clk_disable_unprepare(psc_clk);
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 02/24] serial: mpc512x: prepare clocks before enabling them
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
clocks need to get prepared before they can get enabled, and after
disabling them they can get unprepared
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/tty/serial/mpc52xx_uart.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index e1280a2..53c1093 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -636,9 +636,9 @@ static int mpc512x_psc_clock(struct uart_port *port, int enable)
dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
if (enable)
- clk_enable(psc_clk);
+ clk_prepare_enable(psc_clk);
else
- clk_disable(psc_clk);
+ clk_disable_unprepare(psc_clk);
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 03/24] mtd: mpc5121_nfc: prepare clocks before enabling them
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
must prepare clocks before enabling them, unprepare after disable
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/mtd/nand/mpc5121_nfc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 3c9cdcb..eb7771d 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -618,7 +618,7 @@ static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
struct mpc5121_nfc_prv *prv = chip->priv;
if (prv->clk) {
- clk_disable(prv->clk);
+ clk_disable_unprepare(prv->clk);
clk_put(prv->clk);
}
@@ -737,7 +737,7 @@ static int mpc5121_nfc_probe(struct platform_device *op)
goto error;
}
- clk_enable(prv->clk);
+ clk_prepare_enable(prv->clk);
/* Reset NAND Flash controller */
nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 03/24] mtd: mpc5121_nfc: prepare clocks before enabling them
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
must prepare clocks before enabling them, unprepare after disable
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/mtd/nand/mpc5121_nfc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 3c9cdcb..eb7771d 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -618,7 +618,7 @@ static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
struct mpc5121_nfc_prv *prv = chip->priv;
if (prv->clk) {
- clk_disable(prv->clk);
+ clk_disable_unprepare(prv->clk);
clk_put(prv->clk);
}
@@ -737,7 +737,7 @@ static int mpc5121_nfc_probe(struct platform_device *op)
goto error;
}
- clk_enable(prv->clk);
+ clk_prepare_enable(prv->clk);
/* Reset NAND Flash controller */
nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 03/24] mtd: mpc5121_nfc: prepare clocks before enabling them
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
must prepare clocks before enabling them, unprepare after disable
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/mtd/nand/mpc5121_nfc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 3c9cdcb..eb7771d 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -618,7 +618,7 @@ static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
struct mpc5121_nfc_prv *prv = chip->priv;
if (prv->clk) {
- clk_disable(prv->clk);
+ clk_disable_unprepare(prv->clk);
clk_put(prv->clk);
}
@@ -737,7 +737,7 @@ static int mpc5121_nfc_probe(struct platform_device *op)
goto error;
}
- clk_enable(prv->clk);
+ clk_prepare_enable(prv->clk);
/* Reset NAND Flash controller */
nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 04/24] powerpc: mpc512x: array decl for MCLK registers in CCM
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
reword the clock control module's registers declaration such that the
MCLK related registers form an array and get indexed by PSC number
this change is in preparation to COMMON_CLK support for the MPC512x
platform, the changed declaration remains neutral to existing code since
the PSC and MSCAN CCR fields declared here aren't referenced anywhere
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/include/asm/mpc5121.h | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 8ae133e..887d3d6 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -32,25 +32,11 @@ struct mpc512x_ccm {
u32 scfr2; /* System Clock Frequency Register 2 */
u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
u32 bcr; /* Bread Crumb Register */
- u32 p0ccr; /* PSC0 Clock Control Register */
- u32 p1ccr; /* PSC1 CCR */
- u32 p2ccr; /* PSC2 CCR */
- u32 p3ccr; /* PSC3 CCR */
- u32 p4ccr; /* PSC4 CCR */
- u32 p5ccr; /* PSC5 CCR */
- u32 p6ccr; /* PSC6 CCR */
- u32 p7ccr; /* PSC7 CCR */
- u32 p8ccr; /* PSC8 CCR */
- u32 p9ccr; /* PSC9 CCR */
- u32 p10ccr; /* PSC10 CCR */
- u32 p11ccr; /* PSC11 CCR */
+ u32 psc_ccr[12]; /* PSC Clock Control Registers */
u32 spccr; /* SPDIF Clock Control Register */
u32 cccr; /* CFM Clock Control Register */
u32 dccr; /* DIU Clock Control Register */
- u32 m1ccr; /* MSCAN1 CCR */
- u32 m2ccr; /* MSCAN2 CCR */
- u32 m3ccr; /* MSCAN3 CCR */
- u32 m4ccr; /* MSCAN4 CCR */
+ u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
u8 res[0x98]; /* Reserved */
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 04/24] powerpc: mpc512x: array decl for MCLK registers in CCM
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
reword the clock control module's registers declaration such that the
MCLK related registers form an array and get indexed by PSC number
this change is in preparation to COMMON_CLK support for the MPC512x
platform, the changed declaration remains neutral to existing code since
the PSC and MSCAN CCR fields declared here aren't referenced anywhere
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/include/asm/mpc5121.h | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 8ae133e..887d3d6 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -32,25 +32,11 @@ struct mpc512x_ccm {
u32 scfr2; /* System Clock Frequency Register 2 */
u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
u32 bcr; /* Bread Crumb Register */
- u32 p0ccr; /* PSC0 Clock Control Register */
- u32 p1ccr; /* PSC1 CCR */
- u32 p2ccr; /* PSC2 CCR */
- u32 p3ccr; /* PSC3 CCR */
- u32 p4ccr; /* PSC4 CCR */
- u32 p5ccr; /* PSC5 CCR */
- u32 p6ccr; /* PSC6 CCR */
- u32 p7ccr; /* PSC7 CCR */
- u32 p8ccr; /* PSC8 CCR */
- u32 p9ccr; /* PSC9 CCR */
- u32 p10ccr; /* PSC10 CCR */
- u32 p11ccr; /* PSC11 CCR */
+ u32 psc_ccr[12]; /* PSC Clock Control Registers */
u32 spccr; /* SPDIF Clock Control Register */
u32 cccr; /* CFM Clock Control Register */
u32 dccr; /* DIU Clock Control Register */
- u32 m1ccr; /* MSCAN1 CCR */
- u32 m2ccr; /* MSCAN2 CCR */
- u32 m3ccr; /* MSCAN3 CCR */
- u32 m4ccr; /* MSCAN4 CCR */
+ u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
u8 res[0x98]; /* Reserved */
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 04/24] powerpc: mpc512x: array decl for MCLK registers in CCM
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
reword the clock control module's registers declaration such that the
MCLK related registers form an array and get indexed by PSC number
this change is in preparation to COMMON_CLK support for the MPC512x
platform, the changed declaration remains neutral to existing code since
the PSC and MSCAN CCR fields declared here aren't referenced anywhere
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/include/asm/mpc5121.h | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 8ae133e..887d3d6 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -32,25 +32,11 @@ struct mpc512x_ccm {
u32 scfr2; /* System Clock Frequency Register 2 */
u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
u32 bcr; /* Bread Crumb Register */
- u32 p0ccr; /* PSC0 Clock Control Register */
- u32 p1ccr; /* PSC1 CCR */
- u32 p2ccr; /* PSC2 CCR */
- u32 p3ccr; /* PSC3 CCR */
- u32 p4ccr; /* PSC4 CCR */
- u32 p5ccr; /* PSC5 CCR */
- u32 p6ccr; /* PSC6 CCR */
- u32 p7ccr; /* PSC7 CCR */
- u32 p8ccr; /* PSC8 CCR */
- u32 p9ccr; /* PSC9 CCR */
- u32 p10ccr; /* PSC10 CCR */
- u32 p11ccr; /* PSC11 CCR */
+ u32 psc_ccr[12]; /* PSC Clock Control Registers */
u32 spccr; /* SPDIF Clock Control Register */
u32 cccr; /* CFM Clock Control Register */
u32 dccr; /* DIU Clock Control Register */
- u32 m1ccr; /* MSCAN1 CCR */
- u32 m2ccr; /* MSCAN2 CCR */
- u32 m3ccr; /* MSCAN3 CCR */
- u32 m4ccr; /* MSCAN4 CCR */
+ u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
u8 res[0x98]; /* Reserved */
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals
wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
drivers/clk/clk-divider.c | 6 +++---
drivers/clk/clk-gate.c | 6 +++---
drivers/clk/clk-mux.c | 6 +++---
include/linux/clk-provider.h | 17 +++++++++++++++++
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6d55eb2..2c07061 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int div, val;
- val = readl(divider->reg) >> divider->shift;
+ val = clk_readl(divider->reg) >> divider->shift;
val &= div_mask(divider);
div = _get_div(divider, val);
@@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider) << (divider->shift + 16);
} else {
- val = readl(divider->reg);
+ val = clk_readl(divider->reg);
val &= ~(div_mask(divider) << divider->shift);
}
val |= value << divider->shift;
- writel(val, divider->reg);
+ clk_writel(val, divider->reg);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 790306e..b7fbd96 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
if (set)
reg |= BIT(gate->bit_idx);
} else {
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
if (set)
reg |= BIT(gate->bit_idx);
@@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
reg &= ~BIT(gate->bit_idx);
}
- writel(reg, gate->reg);
+ clk_writel(reg, gate->reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
@@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
/* if a set bit disables this clk, flip it before masking */
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 614444c..02ef506 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
* val = 0x4 really means "bit 2, index starts at bit 0"
*/
- val = readl(mux->reg) >> mux->shift;
+ val = clk_readl(mux->reg) >> mux->shift;
val &= mux->mask;
if (mux->table) {
@@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
if (mux->flags & CLK_MUX_HIWORD_MASK) {
val = mux->mask << (mux->shift + 16);
} else {
- val = readl(mux->reg);
+ val = clk_readl(mux->reg);
val &= ~(mux->mask << mux->shift);
}
val |= index << mux->shift;
- writel(val, mux->reg);
+ clk_writel(val, mux->reg);
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1ec14a7..c4f7799 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -12,6 +12,7 @@
#define __LINUX_CLK_PROVIDER_H
#include <linux/clk.h>
+#include <linux/io.h>
#ifdef CONFIG_COMMON_CLK
@@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
#define of_clk_init(matches) \
{ while (0); }
#endif /* CONFIG_OF */
+
+/*
+ * wrap access to peripherals in accessor routines
+ * for improved portability across platforms
+ */
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return readl(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ writel(val, reg);
+}
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals
wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/clk/clk-divider.c | 6 +++---
drivers/clk/clk-gate.c | 6 +++---
drivers/clk/clk-mux.c | 6 +++---
include/linux/clk-provider.h | 17 +++++++++++++++++
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6d55eb2..2c07061 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int div, val;
- val = readl(divider->reg) >> divider->shift;
+ val = clk_readl(divider->reg) >> divider->shift;
val &= div_mask(divider);
div = _get_div(divider, val);
@@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider) << (divider->shift + 16);
} else {
- val = readl(divider->reg);
+ val = clk_readl(divider->reg);
val &= ~(div_mask(divider) << divider->shift);
}
val |= value << divider->shift;
- writel(val, divider->reg);
+ clk_writel(val, divider->reg);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 790306e..b7fbd96 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
if (set)
reg |= BIT(gate->bit_idx);
} else {
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
if (set)
reg |= BIT(gate->bit_idx);
@@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
reg &= ~BIT(gate->bit_idx);
}
- writel(reg, gate->reg);
+ clk_writel(reg, gate->reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
@@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
/* if a set bit disables this clk, flip it before masking */
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 614444c..02ef506 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
* val = 0x4 really means "bit 2, index starts at bit 0"
*/
- val = readl(mux->reg) >> mux->shift;
+ val = clk_readl(mux->reg) >> mux->shift;
val &= mux->mask;
if (mux->table) {
@@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
if (mux->flags & CLK_MUX_HIWORD_MASK) {
val = mux->mask << (mux->shift + 16);
} else {
- val = readl(mux->reg);
+ val = clk_readl(mux->reg);
val &= ~(mux->mask << mux->shift);
}
val |= index << mux->shift;
- writel(val, mux->reg);
+ clk_writel(val, mux->reg);
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1ec14a7..c4f7799 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -12,6 +12,7 @@
#define __LINUX_CLK_PROVIDER_H
#include <linux/clk.h>
+#include <linux/io.h>
#ifdef CONFIG_COMMON_CLK
@@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
#define of_clk_init(matches) \
{ while (0); }
#endif /* CONFIG_OF */
+
+/*
+ * wrap access to peripherals in accessor routines
+ * for improved portability across platforms
+ */
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return readl(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ writel(val, reg);
+}
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals
wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/clk/clk-divider.c | 6 +++---
drivers/clk/clk-gate.c | 6 +++---
drivers/clk/clk-mux.c | 6 +++---
include/linux/clk-provider.h | 17 +++++++++++++++++
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6d55eb2..2c07061 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int div, val;
- val = readl(divider->reg) >> divider->shift;
+ val = clk_readl(divider->reg) >> divider->shift;
val &= div_mask(divider);
div = _get_div(divider, val);
@@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider) << (divider->shift + 16);
} else {
- val = readl(divider->reg);
+ val = clk_readl(divider->reg);
val &= ~(div_mask(divider) << divider->shift);
}
val |= value << divider->shift;
- writel(val, divider->reg);
+ clk_writel(val, divider->reg);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 790306e..b7fbd96 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
if (set)
reg |= BIT(gate->bit_idx);
} else {
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
if (set)
reg |= BIT(gate->bit_idx);
@@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
reg &= ~BIT(gate->bit_idx);
}
- writel(reg, gate->reg);
+ clk_writel(reg, gate->reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
@@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
/* if a set bit disables this clk, flip it before masking */
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 614444c..02ef506 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
* val = 0x4 really means "bit 2, index starts at bit 0"
*/
- val = readl(mux->reg) >> mux->shift;
+ val = clk_readl(mux->reg) >> mux->shift;
val &= mux->mask;
if (mux->table) {
@@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
if (mux->flags & CLK_MUX_HIWORD_MASK) {
val = mux->mask << (mux->shift + 16);
} else {
- val = readl(mux->reg);
+ val = clk_readl(mux->reg);
val &= ~(mux->mask << mux->shift);
}
val |= index << mux->shift;
- writel(val, mux->reg);
+ clk_writel(val, mux->reg);
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1ec14a7..c4f7799 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -12,6 +12,7 @@
#define __LINUX_CLK_PROVIDER_H
#include <linux/clk.h>
+#include <linux/io.h>
#ifdef CONFIG_COMMON_CLK
@@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
#define of_clk_init(matches) \
{ while (0); }
#endif /* CONFIG_OF */
+
+/*
+ * wrap access to peripherals in accessor routines
+ * for improved portability across platforms
+ */
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return readl(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ writel(val, reg);
+}
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 06/24] dts: mpc512x: prepare for preprocessor support
2013-07-15 18:47 ` Gerhard Sittig
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
prepare C preprocessor support when processing MPC512x DTS files
- switch from DTS syntax to CPP syntax for include specs
- create a symlink such that DTS processing can reference includes
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/ac14xx.dts | 2 +-
arch/powerpc/boot/dts/include/dt-bindings | 1 +
arch/powerpc/boot/dts/mpc5121ads.dts | 2 +-
arch/powerpc/boot/dts/pdm360ng.dts | 2 +-
4 files changed, 4 insertions(+), 3 deletions(-)
create mode 120000 arch/powerpc/boot/dts/include/dt-bindings
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a27a460..a543c40 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -10,7 +10,7 @@
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "ac14xx";
diff --git a/arch/powerpc/boot/dts/include/dt-bindings b/arch/powerpc/boot/dts/include/dt-bindings
new file mode 120000
index 0000000..08c00e4
--- /dev/null
+++ b/arch/powerpc/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index 7d3cb79..c228a0a 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -9,7 +9,7 @@
* option) any later version.
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "mpc5121ads";
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
index 7433740..871c16d 100644
--- a/arch/powerpc/boot/dts/pdm360ng.dts
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -13,7 +13,7 @@
* option) any later version.
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "pdm360ng";
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 06/24] dts: mpc512x: prepare for preprocessor support
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
prepare C preprocessor support when processing MPC512x DTS files
- switch from DTS syntax to CPP syntax for include specs
- create a symlink such that DTS processing can reference includes
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/ac14xx.dts | 2 +-
arch/powerpc/boot/dts/include/dt-bindings | 1 +
arch/powerpc/boot/dts/mpc5121ads.dts | 2 +-
arch/powerpc/boot/dts/pdm360ng.dts | 2 +-
4 files changed, 4 insertions(+), 3 deletions(-)
create mode 120000 arch/powerpc/boot/dts/include/dt-bindings
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a27a460..a543c40 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -10,7 +10,7 @@
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "ac14xx";
diff --git a/arch/powerpc/boot/dts/include/dt-bindings b/arch/powerpc/boot/dts/include/dt-bindings
new file mode 120000
index 0000000..08c00e4
--- /dev/null
+++ b/arch/powerpc/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index 7d3cb79..c228a0a 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -9,7 +9,7 @@
* option) any later version.
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "mpc5121ads";
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
index 7433740..871c16d 100644
--- a/arch/powerpc/boot/dts/pdm360ng.dts
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -13,7 +13,7 @@
* option) any later version.
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "pdm360ng";
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 07/24] dts: mpc512x: introduce dt-bindings/clock/ header
2013-07-15 18:47 ` Gerhard Sittig
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
introduce a dt-bindings/ header file for MPC512x clocks,
providing symbolic identifiers for those SoC clocks which
clients will reference from their device tree nodes
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
include/dt-bindings/clock/mpc512x-clock.h | 59 +++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
diff --git a/include/dt-bindings/clock/mpc512x-clock.h b/include/dt-bindings/clock/mpc512x-clock.h
new file mode 100644
index 0000000..46c560e
--- /dev/null
+++ b/include/dt-bindings/clock/mpc512x-clock.h
@@ -0,0 +1,59 @@
+/*
+ * This header provides constants for MPC512x clock specs in DT bindings.
+ *
+ * Unfortunately the clock number declaration cannot be an enum but
+ * needs to be a list of #define directives since when referenced from
+ * within DTS files they need to get resolved "at compile time".
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+
+#define MPC512x_CLK_DUMMY 0
+#define MPC512x_CLK_REF 1
+#define MPC512x_CLK_SYS 2
+#define MPC512x_CLK_DIU 3
+#define MPC512x_CLK_VIU 4
+#define MPC512x_CLK_CSB 5
+#define MPC512x_CLK_E300 6
+#define MPC512x_CLK_IPS 7
+#define MPC512x_CLK_FEC 8
+#define MPC512x_CLK_SATA 9
+#define MPC512x_CLK_PATA 10
+#define MPC512x_CLK_NFC 11
+#define MPC512x_CLK_LPC 12
+#define MPC512x_CLK_MBX_BUS 13
+#define MPC512x_CLK_MBX 14
+#define MPC512x_CLK_MBX_3D 15
+#define MPC512x_CLK_AXE 16
+#define MPC512x_CLK_USB1 17
+#define MPC512x_CLK_USB2 18
+#define MPC512x_CLK_I2C 19
+#define MPC512x_CLK_MSCAN0_MCLK 20
+#define MPC512x_CLK_MSCAN1_MCLK 21
+#define MPC512x_CLK_MSCAN2_MCLK 22
+#define MPC512x_CLK_MSCAN3_MCLK 23
+#define MPC512x_CLK_SDHC 24
+#define MPC512x_CLK_PCI 25
+#define MPC512x_CLK_PSC_MCLK_IN 26
+#define MPC512x_CLK_SPDIF_TX 27
+#define MPC512x_CLK_SPDIF_RX 28
+#define MPC512x_CLK_SPDIF_MCLK 29
+#define MPC512x_CLK_AC97 30
+#define MPC512x_CLK_PSC0_MCLK 31
+#define MPC512x_CLK_PSC1_MCLK 32
+#define MPC512x_CLK_PSC2_MCLK 33
+#define MPC512x_CLK_PSC3_MCLK 34
+#define MPC512x_CLK_PSC4_MCLK 35
+#define MPC512x_CLK_PSC5_MCLK 36
+#define MPC512x_CLK_PSC6_MCLK 37
+#define MPC512x_CLK_PSC7_MCLK 38
+#define MPC512x_CLK_PSC8_MCLK 39
+#define MPC512x_CLK_PSC9_MCLK 40
+#define MPC512x_CLK_PSC10_MCLK 41
+#define MPC512x_CLK_PSC11_MCLK 42
+#define MPC512x_CLK_PSC_FIFO 43
+
+#define MPC512x_CLK_LAST_PUBLIC 43
+
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 07/24] dts: mpc512x: introduce dt-bindings/clock/ header
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
introduce a dt-bindings/ header file for MPC512x clocks,
providing symbolic identifiers for those SoC clocks which
clients will reference from their device tree nodes
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
include/dt-bindings/clock/mpc512x-clock.h | 59 +++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
diff --git a/include/dt-bindings/clock/mpc512x-clock.h b/include/dt-bindings/clock/mpc512x-clock.h
new file mode 100644
index 0000000..46c560e
--- /dev/null
+++ b/include/dt-bindings/clock/mpc512x-clock.h
@@ -0,0 +1,59 @@
+/*
+ * This header provides constants for MPC512x clock specs in DT bindings.
+ *
+ * Unfortunately the clock number declaration cannot be an enum but
+ * needs to be a list of #define directives since when referenced from
+ * within DTS files they need to get resolved "at compile time".
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+
+#define MPC512x_CLK_DUMMY 0
+#define MPC512x_CLK_REF 1
+#define MPC512x_CLK_SYS 2
+#define MPC512x_CLK_DIU 3
+#define MPC512x_CLK_VIU 4
+#define MPC512x_CLK_CSB 5
+#define MPC512x_CLK_E300 6
+#define MPC512x_CLK_IPS 7
+#define MPC512x_CLK_FEC 8
+#define MPC512x_CLK_SATA 9
+#define MPC512x_CLK_PATA 10
+#define MPC512x_CLK_NFC 11
+#define MPC512x_CLK_LPC 12
+#define MPC512x_CLK_MBX_BUS 13
+#define MPC512x_CLK_MBX 14
+#define MPC512x_CLK_MBX_3D 15
+#define MPC512x_CLK_AXE 16
+#define MPC512x_CLK_USB1 17
+#define MPC512x_CLK_USB2 18
+#define MPC512x_CLK_I2C 19
+#define MPC512x_CLK_MSCAN0_MCLK 20
+#define MPC512x_CLK_MSCAN1_MCLK 21
+#define MPC512x_CLK_MSCAN2_MCLK 22
+#define MPC512x_CLK_MSCAN3_MCLK 23
+#define MPC512x_CLK_SDHC 24
+#define MPC512x_CLK_PCI 25
+#define MPC512x_CLK_PSC_MCLK_IN 26
+#define MPC512x_CLK_SPDIF_TX 27
+#define MPC512x_CLK_SPDIF_RX 28
+#define MPC512x_CLK_SPDIF_MCLK 29
+#define MPC512x_CLK_AC97 30
+#define MPC512x_CLK_PSC0_MCLK 31
+#define MPC512x_CLK_PSC1_MCLK 32
+#define MPC512x_CLK_PSC2_MCLK 33
+#define MPC512x_CLK_PSC3_MCLK 34
+#define MPC512x_CLK_PSC4_MCLK 35
+#define MPC512x_CLK_PSC5_MCLK 36
+#define MPC512x_CLK_PSC6_MCLK 37
+#define MPC512x_CLK_PSC7_MCLK 38
+#define MPC512x_CLK_PSC8_MCLK 39
+#define MPC512x_CLK_PSC9_MCLK 40
+#define MPC512x_CLK_PSC10_MCLK 41
+#define MPC512x_CLK_PSC11_MCLK 42
+#define MPC512x_CLK_PSC_FIFO 43
+
+#define MPC512x_CLK_LAST_PUBLIC 43
+
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 08/24] dts: mpc512x: add clock related device tree specs
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this addresses the clock driver aka provider's side of clocks
- prepare for future '<&clks ID>' phandle references for device tree
based clock lookup in client drivers
- introduce a 'clocks' subtree with an 'osc' node for the crystal
or oscillator SoC input (fixed frequency)
- provide default values with 33MHz oscillator frequency in the
common include (the 66MHz IPS bus already was there), add
override values for the ifm AC14xx board which deviates from
the reference design (25MHz xtal, 80MHz IPS bus)
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
arch/powerpc/boot/dts/ac14xx.dts | 7 +++++++
arch/powerpc/boot/dts/mpc5121.dtsi | 15 ++++++++++++++-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a543c40..a1b8837 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -139,7 +139,14 @@
};
};
+ clocks {
+ osc {
+ clock-frequency = <25000000>;
+ };
+ };
+
soc@80000000 {
+ bus-frequency = <80000000>; /* 80 MHz ips bus */
clock@f00 {
compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index bd14c00..8f4cba0 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -9,6 +9,8 @@
* option) any later version.
*/
+#include <dt-bindings/clock/mpc512x-clock.h>
+
/dts-v1/;
/ {
@@ -73,6 +75,16 @@
ranges = <0x0 0x0 0xfc000000 0x04000000>;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc {
+ compatible = "fsl,mpc512x-osc", "fixed-clock";
+ clock-frequency = <33000000>;
+ };
+ };
+
soc@80000000 {
compatible = "fsl,mpc5121-immr";
#address-cells = <1>;
@@ -118,9 +130,10 @@
};
/* Clock control */
- clock@f00 {
+ clks: clock@f00 {
compatible = "fsl,mpc5121-clock";
reg = <0xf00 0x100>;
+ #clock-cells = <1>;
};
/* Power Management Controller */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 08/24] dts: mpc512x: add clock related device tree specs
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this addresses the clock driver aka provider's side of clocks
- prepare for future '<&clks ID>' phandle references for device tree
based clock lookup in client drivers
- introduce a 'clocks' subtree with an 'osc' node for the crystal
or oscillator SoC input (fixed frequency)
- provide default values with 33MHz oscillator frequency in the
common include (the 66MHz IPS bus already was there), add
override values for the ifm AC14xx board which deviates from
the reference design (25MHz xtal, 80MHz IPS bus)
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/ac14xx.dts | 7 +++++++
arch/powerpc/boot/dts/mpc5121.dtsi | 15 ++++++++++++++-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a543c40..a1b8837 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -139,7 +139,14 @@
};
};
+ clocks {
+ osc {
+ clock-frequency = <25000000>;
+ };
+ };
+
soc@80000000 {
+ bus-frequency = <80000000>; /* 80 MHz ips bus */
clock@f00 {
compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index bd14c00..8f4cba0 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -9,6 +9,8 @@
* option) any later version.
*/
+#include <dt-bindings/clock/mpc512x-clock.h>
+
/dts-v1/;
/ {
@@ -73,6 +75,16 @@
ranges = <0x0 0x0 0xfc000000 0x04000000>;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc {
+ compatible = "fsl,mpc512x-osc", "fixed-clock";
+ clock-frequency = <33000000>;
+ };
+ };
+
soc@80000000 {
compatible = "fsl,mpc5121-immr";
#address-cells = <1>;
@@ -118,9 +130,10 @@
};
/* Clock control */
- clock@f00 {
+ clks: clock@f00 {
compatible = "fsl,mpc5121-clock";
reg = <0xf00 0x100>;
+ #clock-cells = <1>;
};
/* Power Management Controller */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 08/24] dts: mpc512x: add clock related device tree specs
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
this addresses the clock driver aka provider's side of clocks
- prepare for future '<&clks ID>' phandle references for device tree
based clock lookup in client drivers
- introduce a 'clocks' subtree with an 'osc' node for the crystal
or oscillator SoC input (fixed frequency)
- provide default values with 33MHz oscillator frequency in the
common include (the 66MHz IPS bus already was there), add
override values for the ifm AC14xx board which deviates from
the reference design (25MHz xtal, 80MHz IPS bus)
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/ac14xx.dts | 7 +++++++
arch/powerpc/boot/dts/mpc5121.dtsi | 15 ++++++++++++++-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a543c40..a1b8837 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -139,7 +139,14 @@
};
};
+ clocks {
+ osc {
+ clock-frequency = <25000000>;
+ };
+ };
+
soc at 80000000 {
+ bus-frequency = <80000000>; /* 80 MHz ips bus */
clock at f00 {
compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index bd14c00..8f4cba0 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -9,6 +9,8 @@
* option) any later version.
*/
+#include <dt-bindings/clock/mpc512x-clock.h>
+
/dts-v1/;
/ {
@@ -73,6 +75,16 @@
ranges = <0x0 0x0 0xfc000000 0x04000000>;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc {
+ compatible = "fsl,mpc512x-osc", "fixed-clock";
+ clock-frequency = <33000000>;
+ };
+ };
+
soc at 80000000 {
compatible = "fsl,mpc5121-immr";
#address-cells = <1>;
@@ -118,9 +130,10 @@
};
/* Clock control */
- clock at f00 {
+ clks: clock at f00 {
compatible = "fsl,mpc5121-clock";
reg = <0xf00 0x100>;
+ #clock-cells = <1>;
};
/* Power Management Controller */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 09/24] clk: mpc512x: introduce COMMON_CLK for MPC512x
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
this change introduces a clock infrastructure implementation for the
MPC512x PowerPC platform which follows the COMMON_CLK approach and uses
common clock drivers shared with other platforms
this driver implements the publicly announced set of clocks (which can
get referenced by means of symbolic identifiers from the dt-bindings
header file), as well as generates additional 'struct clk' items where
the SoC hardware cannot easily get mapped to the common primitives of
the clock API, or requires "intermediate" clock nodes to represent
clocks that have both gates and dividers
the previous PPC_CLOCK implementation is kept in place and resides in
parallel to the common clock implementation for test and comparison
during migration, a compile time option picks one of the two
alternatives (Kconfig switch, common clock used by default)
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/Kconfig | 14 +-
arch/powerpc/platforms/512x/Makefile | 4 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 777 +++++++++++++++++++++++++
include/linux/clk-provider.h | 16 +
4 files changed, 809 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index fc9c1cb..c5fcdd0 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,9 +1,21 @@
+config MPC512x_COMMON_CLK
+ bool "MPC512x platform uses COMMON_CLK"
+ default y
+ depends on PPC_MPC512x
+ help
+ This option is only here to support tests and comparison
+ during development and migration. This option will get
+ removed after the COMMON_CLK support for MPC512x has become
+ fully operational and all drivers were adjusted to explicitly
+ acquire their required clocks.
+
config PPC_MPC512x
bool "512x-based boards"
depends on 6xx
select FSL_SOC
select IPIC
- select PPC_CLOCK
+ select PPC_CLOCK if !MPC512x_COMMON_CLK
+ select COMMON_CLK if MPC512x_COMMON_CLK
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 72fb934..1e05f9d 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,7 +1,9 @@
#
# Makefile for the Freescale PowerPC 512x linux kernel.
#
-obj-y += clock.o mpc512x_shared.o
+obj-$(CONFIG_PPC_CLOCK) += clock.o
+obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
+obj-y += mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o
obj-$(CONFIG_PDM360NG) += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
new file mode 100644
index 0000000..218f55b
--- /dev/null
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -0,0 +1,777 @@
+/*
+ * Copyright (C) 2013 DENX Software Engineering
+ *
+ * Gerhard Sittig, <gsi@denx.de>
+ *
+ * common clock driver support for the MPC512x platform
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <asm/mpc5121.h>
+#include <dt-bindings/clock/mpc512x-clock.h>
+
+#include "mpc512x.h" /* our public mpc5121_clk_init() API */
+
+/* helpers to keep the MCLK intermediates "somewhere" in our table */
+enum {
+ MCLK_IDX_MUX0,
+ MCLK_IDX_EN0,
+ MCLK_IDX_DIV0,
+ MCLK_IDX_MUX1,
+ MCLK_MAX_IDX,
+};
+
+#define NR_PSCS 12
+#define NR_MSCANS 4
+#define NR_SPDIFS 1
+#define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS)
+
+/* extend the public set of clocks by adding internal slots for management */
+enum {
+ /* arrange for adjacent numbers after the public set */
+ MPC512x_CLK_START_PRIVATE = MPC512x_CLK_LAST_PUBLIC,
+ /* clocks which aren't announced to the public */
+ MPC512x_CLK_DDR,
+ MPC512x_CLK_MEM,
+ MPC512x_CLK_IIM,
+ MPC512x_CLK_SDHC_2,
+ /* intermediates in div+gate combos or fractional dividers */
+ MPC512x_CLK_DDR_UG,
+ MPC512x_CLK_SDHC_x4,
+ MPC512x_CLK_SDHC_UG,
+ MPC512x_CLK_DIU_x4,
+ MPC512x_CLK_DIU_UG,
+ MPC512x_CLK_MBX_BUS_UG,
+ MPC512x_CLK_MBX_UG,
+ MPC512x_CLK_MBX_3D_UG,
+ MPC512x_CLK_PCI_UG,
+ MPC512x_CLK_NFC_UG,
+ MPC512x_CLK_LPC_UG,
+ MPC512x_CLK_SPDIF_TX_IN,
+ /* intermediates for the mux+gate+div+mux MCLK generation */
+ MPC512x_CLK_MCLKS_FIRST,
+ MPC512x_CLK_MCLKS_LAST = MPC512x_CLK_MCLKS_FIRST
+ + NR_MCLKS * MCLK_MAX_IDX,
+ /* internal, symbolic spec for the number of slots */
+ MPC512x_CLK_LAST_PRIVATE,
+};
+
+/* data required for the OF clock provider registration */
+static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
+static struct clk_onecell_data clk_data;
+
+/* CCM register access */
+static struct mpc512x_ccm __iomem *clkregs;
+static DEFINE_SPINLOCK(clklock);
+
+/* convenience wrappers around the common clk API */
+static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
+{
+ return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *mpc512x_clk_factor(
+ const char *name, const char *parent_name,
+ int mul, int div)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_fixed_factor(NULL, name, parent_name, clkflags,
+ mul, div);
+}
+
+static inline struct clk *mpc512x_clk_divider(
+ const char *name, const char *parent_name, u8 clkflags,
+ u32 __iomem *reg, u8 pos, u8 len, int divflags)
+{
+ return clk_register_divider(NULL, name, parent_name, clkflags,
+ reg, pos, len, divflags, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_divtable(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos, u8 len,
+ const struct clk_div_table *divtab)
+{
+ u8 divflags;
+
+ divflags = 0;
+ return clk_register_divider_table(NULL, name, parent_name, 0,
+ reg, pos, len, divflags,
+ divtab, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_gated(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_gate(NULL, name, parent_name, clkflags,
+ reg, pos, 0, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_muxed(const char *name,
+ const char **parent_names, int parent_count,
+ u32 __iomem *reg, u8 pos, u8 len)
+{
+ int clkflags;
+ u8 muxflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ muxflags = 0;
+ return clk_register_mux(NULL, name,
+ parent_names, parent_count, clkflags,
+ reg, pos, len, muxflags, &clklock);
+}
+
+/* helper to isolate a bit field from a register */
+static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len)
+{
+ uint32_t val;
+
+ val = in_be32(reg);
+ val >>= pos;
+ val &= (1 << len) - 1;
+ return val;
+}
+
+/* get the SPMF and translate it into the "sys pll" multiplier */
+static int get_spmf_mult(void)
+{
+ static int spmf_to_mult[] = {
+ 68, 1, 12, 16, 20, 24, 28, 32,
+ 36, 40, 44, 48, 52, 56, 60, 64,
+ };
+ int spmf;
+
+ spmf = get_bit_field(&clkregs->spmr, 24, 4);
+ return spmf_to_mult[spmf];
+}
+
+/*
+ * get the SYS_DIV value and translate it into a divide factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * divide ratio is fractional
+ */
+static int get_sys_div_x2(void)
+{
+ static int sysdiv_code_to_x2[] = {
+ 4, 5, 6, 7, 8, 9, 10, 14,
+ 12, 16, 18, 22, 20, 24, 26, 30,
+ 28, 32, 34, 38, 36, 40, 42, 46,
+ 44, 48, 50, 54, 52, 56, 58, 62,
+ 60, 64, 66,
+ };
+ int divcode;
+
+ divcode = get_bit_field(&clkregs->scfr2, 26, 6);
+ return sysdiv_code_to_x2[divcode];
+}
+
+/*
+ * get the CPMF value and translate it into a multiplier factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * multiplier ratio is fractional
+ */
+static int get_cpmf_mult_x2(void)
+{
+ static int cpmf_to_mult[] = {
+ 72, 2, 2, 3, 4, 5, 6, 7,
+ };
+ int cpmf;
+
+ cpmf = get_bit_field(&clkregs->spmr, 16, 4);
+ return cpmf_to_mult[cpmf];
+}
+
+/*
+ * some of the clock dividers do scale in a linear way, yet not all of
+ * their bit combinations are legal; use a divider table to get a
+ * resulting set of applicable divider values
+ */
+
+/* applies to the IPS_DIV, and PCI_DIV values */
+static struct clk_div_table divtab_2346[] = {
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .val = 6, .div = 6, },
+ { .div = 0, },
+};
+
+/* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
+static struct clk_div_table divtab_1234[] = {
+ { .val = 1, .div = 1, },
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .div = 0, },
+};
+
+static int get_freq_from_dt(char *propname)
+{
+ struct device_node *np;
+ const unsigned int *prop;
+ int val;
+
+ val = 0;
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
+ if (np) {
+ prop = of_get_property(np, propname, NULL);
+ if (prop)
+ val = *prop;
+ of_node_put(np);
+ }
+ return val;
+}
+
+static void mpc512x_clk_preset_data(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++)
+ clks[i] = ERR_PTR(-ENODEV);
+}
+
+/*
+ * - receives the "bus frequency" from the caller (that's the IPS clock
+ * rate, the historical source of clock information)
+ * - fetches the system PLL multiplier and divider values as well as the
+ * IPS divider value from hardware
+ * - determines the REF clock rate either from the XTAL/OSC spec (if
+ * there is a device tree node describing the oscillator) or from the
+ * IPS bus clock (supported for backwards compatibility, such that
+ * setups without XTAL/OSC specs keep working)
+ * - creates the "ref" clock item in the clock tree, such that
+ * subsequent code can create the remainder of the hierarchy (REF ->
+ * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
+ * values
+ */
+static void mpc512x_clk_setup_ref_clock(int bus_freq,
+ int *sys_mul, int *sys_div, int *ips_div)
+{
+ struct clk *osc_clk;
+ int calc_freq;
+
+ /* fetch mul/div factors from the hardware */
+ *sys_mul = get_spmf_mult();
+ *sys_mul *= 2; /* compensate for the fractional divider */
+ *sys_div = get_sys_div_x2();
+ *ips_div = get_bit_field(&clkregs->scfr1, 23, 3);
+
+ /* lookup the oscillator node */
+ osc_clk = clk_get(NULL, "osc");
+ if (osc_clk) {
+ /* descend REF directly from OSC, verify the IPS rate */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1);
+ calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]);
+ calc_freq *= *sys_mul;
+ calc_freq /= *sys_div;
+ calc_freq /= 2;
+ calc_freq /= *ips_div;
+ if (bus_freq && calc_freq != bus_freq)
+ pr_warn("calc rate %d != OF spec %d\n",
+ calc_freq, bus_freq);
+ } else {
+ /* calculate OSC rate and create REF from the freq value */
+ calc_freq = bus_freq; /* start with IPS */
+ calc_freq *= *ips_div; /* IPS -> CSB */
+ calc_freq *= 2; /* CSB -> SYS */
+ calc_freq *= *sys_div; /* SYS -> PLL out */
+ calc_freq /= *sys_mul; /* PLL out -> REF == OSC */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq);
+ }
+}
+
+/*
+ * helper code for the MCLK subtree setup
+ *
+ * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
+ * suggests that all instances of the "PSC clock generation" are equal,
+ * and that one might re-use the PSC setup for MSCAN clock generation
+ * (section 5.2.5) as well, at least the logic if not the data for
+ * description
+ *
+ * the details (starting at page 5-20) show differences in the specific
+ * inputs of the first mux stage ("can clk in", "spdif tx"), and the
+ * factual non-availability of the second mux stage (it's present yet
+ * only one input is valid)
+ *
+ * the MSCAN clock related registers (starting at page 5-35) all
+ * reference "spdif clk" at the first mux stage and don't mention any
+ * "can clk" at all, which somehow is unexpected
+ *
+ * TODO re-check the document, and clarify whether the RM is correct in
+ * the overview or in the details, and whether the difference is a
+ * clipboard induced error or results from chip revisions
+ *
+ * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
+ * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
+ * first a doc update is required which better reflects reality in the
+ * SoC before the implementation should follow while no questions remain
+ */
+
+/*
+ * note that this declaration raises a checkpatch warning, but
+ * it's the very data type which <linux/clk-provider.h> expects,
+ * making this declaration pass checkpatch will break compilation
+ */
+static const char *parent_names_mux0[] = {
+ "sys", "ref", "psc-mclk-in", "spdif-tx",
+};
+
+enum mclk_type {
+ MCLK_TYPE_PSC,
+ MCLK_TYPE_MSCAN,
+ MCLK_TYPE_SPDIF,
+};
+
+struct mclk_setup_data {
+ enum mclk_type type;
+ int comp_idx;
+ bool has_mclk1;
+ int bit_sccr1, bit_sccr2;
+ const char *name_mux0;
+ const char *name_en0;
+ const char *name_div0;
+ const char *parent_names_mux1[2];
+ const char *name_mux1;
+ const char *name_mclk;
+};
+
+#define MCLK_SETUP_DATA_PSC(id) { \
+ MCLK_TYPE_PSC, id, \
+ 0, 27 - id, -1, \
+ "psc" #id "-mux0", \
+ "psc" #id "-en0", \
+ "psc" #id "_mclk_div", \
+ { "psc" #id "_mclk_div", "dummy", }, \
+ "psc" #id "_mclk_out", \
+ "psc" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_MSCAN(id) { \
+ MCLK_TYPE_MSCAN, id, \
+ 0, -1, 25, \
+ "mscan" #id "-mux0", \
+ "mscan" #id "-en0", \
+ "mscan" #id "_mclk_div", \
+ { "mscan" #id "_mclk_div", "dummy", }, \
+ "mscan" #id "_mclk_out", \
+ "mscan" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_SPDIF { \
+ MCLK_TYPE_SPDIF, 0, \
+ 1, -1, 23, \
+ "spdif-mux0", \
+ "spdif-en0", \
+ "spdif_mclk_div", \
+ { "spdif_mclk_div", "spdif-rx", }, \
+ "spdif_mclk_out", \
+ "spdif_mclk", \
+}
+
+static struct mclk_setup_data mclk_psc_data[] = {
+ MCLK_SETUP_DATA_PSC(0),
+ MCLK_SETUP_DATA_PSC(1),
+ MCLK_SETUP_DATA_PSC(2),
+ MCLK_SETUP_DATA_PSC(3),
+ MCLK_SETUP_DATA_PSC(4),
+ MCLK_SETUP_DATA_PSC(5),
+ MCLK_SETUP_DATA_PSC(6),
+ MCLK_SETUP_DATA_PSC(7),
+ MCLK_SETUP_DATA_PSC(8),
+ MCLK_SETUP_DATA_PSC(9),
+ MCLK_SETUP_DATA_PSC(10),
+ MCLK_SETUP_DATA_PSC(11),
+};
+
+static struct mclk_setup_data mclk_mscan_data[] = {
+ MCLK_SETUP_DATA_MSCAN(0),
+ MCLK_SETUP_DATA_MSCAN(1),
+ MCLK_SETUP_DATA_MSCAN(2),
+ MCLK_SETUP_DATA_MSCAN(3),
+};
+
+static struct mclk_setup_data mclk_spdif_data[] = {
+ MCLK_SETUP_DATA_SPDIF,
+};
+
+/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
+static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
+{
+ size_t clks_idx_pub, clks_idx_int;
+ u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */
+ u32 __iomem *sccr_reg; /* system clock control register (enable) */
+ int sccr_bit;
+ int div;
+
+ /* derive a few parameters from the component type and index */
+ switch (entry->type) {
+ case MCLK_TYPE_PSC:
+ clks_idx_pub = MPC512x_CLK_PSC0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->psc_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_MSCAN:
+ clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->mscan_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_SPDIF:
+ clks_idx_pub = MPC512x_CLK_SPDIF_MCLK;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->spccr;
+ break;
+ default:
+ return;
+ }
+ if (entry->bit_sccr1 >= 0) {
+ sccr_reg = &clkregs->sccr1;
+ sccr_bit = entry->bit_sccr1;
+ } else if (entry->bit_sccr2 >= 0) {
+ sccr_reg = &clkregs->sccr2;
+ sccr_bit = entry->bit_sccr2;
+ } else {
+ sccr_reg = NULL;
+ }
+
+ /*
+ * this was grabbed from the PPC_CLOCK implementation, which
+ * enforced a specific MCLK divider while the clock was gated
+ * during setup (that's a documented hardware requirement)
+ *
+ * the PPC_CLOCK implementation might even have violated the
+ * "MCLK <= IPS" constraint, the fixed divider value of 1
+ * results in a divider of 2 and thus MCLK = SYS/2 which equals
+ * CSB which is greater than IPS; the serial port setup may have
+ * adjusted the divider which the clock setup might have left in
+ * an undesirable state
+ *
+ * initial setup is:
+ * - MCLK 0 from SYS
+ * - MCLK DIV such to not exceed the IPS clock
+ * - MCLK 0 enabled
+ * - MCLK 1 from MCLK DIV
+ */
+ div = clk_get_rate(clks[MPC512x_CLK_SYS]);
+ div /= clk_get_rate(clks[MPC512x_CLK_IPS]);
+ out_be32(mccr_reg, (0 << 16));
+ out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
+ out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
+
+ /*
+ * create the 'struct clk' items of the MCLK's clock subtree
+ *
+ * note that by design we always create all nodes and won't take
+ * shortcuts here, because
+ * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
+ * selectable inputs to the CFM while those who "actually use"
+ * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
+ * for their bitrate
+ * - in the absence of "aliases" for clocks we need to create
+ * individial 'struct clk' items for whatever might get
+ * referenced or looked up, even if several of those items are
+ * identical from the logical POV (their rate value)
+ * - for easier future maintenance and for better reflection of
+ * the SoC's documentation, it appears appropriate to generate
+ * clock items even for those muxers which actually are NOPs
+ * (those with two inputs of which one is reserved)
+ */
+ clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed(
+ entry->name_mux0,
+ &parent_names_mux0[0], ARRAY_SIZE(parent_names_mux0),
+ mccr_reg, 14, 2);
+ clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated(
+ entry->name_en0, entry->name_mux0,
+ mccr_reg, 16);
+ clks[clks_idx_int + MCLK_IDX_DIV0] = mpc512x_clk_divider(
+ entry->name_div0,
+ entry->name_en0, CLK_SET_RATE_GATE,
+ mccr_reg, 17, 15, 0);
+ if (entry->has_mclk1) {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_muxed(
+ entry->name_mux1,
+ &entry->parent_names_mux1[0],
+ ARRAY_SIZE(entry->parent_names_mux1),
+ mccr_reg, 7, 1);
+ } else {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_factor(
+ entry->name_mux1, entry->parent_names_mux1[0],
+ 1, 1);
+ }
+ if (sccr_reg) {
+ clks[clks_idx_pub] = mpc512x_clk_gated(
+ entry->name_mclk,
+ entry->name_mux1, sccr_reg, sccr_bit);
+ } else {
+ clks[clks_idx_pub] = mpc512x_clk_factor(
+ entry->name_mclk,
+ entry->name_mux1, 1, 1);
+ }
+
+ /*
+ * without this "clock device" registration, "simple" lookups in
+ * the SPI master initialization and serial port setup will fail
+ *
+ * those drivers need to get adjusted to lookup their required
+ * clocks from OF specs, before this clkdev registration becomes
+ * obsolete
+ */
+ clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
+}
+
+static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
+{
+ while (count-- > 0)
+ mpc512x_clk_setup_mclk(table++);
+}
+
+static void mpc512x_clk_setup_clock_tree(int busfreq)
+{
+ int sys_mul, sys_div, ips_div;
+ int mul, div;
+ int freq;
+
+ /*
+ * TODO
+ * - consider whether to handle clocks which have both gates and
+ * dividers via intermediates or by means of composites
+ * - fractional dividers appear to not map well to composites
+ * since they can be seen as a fixed multiplier and an
+ * adjustable divider, while composites can only combine at
+ * most one of a mux, div, and gate each into one 'struct clk'
+ * item
+ * - PSC/MSCAN/SPDIF clock generation OTOH already is very
+ * specific and cannot get mapped to componsites (at least not
+ * a single one, maybe two of them, but see the comment about
+ * "intermediates are referenced from elsewhere, too")
+ * - trim the list of auto-enabled clocks after drivers acquire
+ * them correctly as needed
+ */
+
+ /* regardless of whether XTAL/OSC exists, have REF created */
+ mpc512x_clk_setup_ref_clock(busfreq, &sys_mul, &sys_div, &ips_div);
+
+ /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
+ clks[MPC512x_CLK_SYS] = mpc512x_clk_factor("sys", "ref",
+ sys_mul, sys_div);
+ clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2);
+ clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb",
+ &clkregs->scfr1, 23, 3,
+ divtab_2346);
+
+ /* now setup anything below SYS and CSB and IPS */
+ clks[MPC512x_CLK_DDR_UG] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2);
+ clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0,
+ &clkregs->scfr2, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+ clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_DIU_UG] = mpc512x_clk_divider("diu-ug", "diu-x4", 0,
+ &clkregs->scfr1, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+
+ /*
+ * the "power architecture PLL" was setup from data which was
+ * sampled from the reset config word, at this point in time the
+ * configuration can be considered fixed and read only (i.e. no
+ * longer adjustable, or no longer in need of adjustment), which
+ * is why we don't register a PLL here but assume fixed factors
+ */
+ mul = get_cpmf_mult_x2();
+ div = 2; /* compensate for the fractional factor */
+ clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div);
+
+ clks[MPC512x_CLK_MBX_BUS_UG] = mpc512x_clk_factor("mbx-bus-ug", "csb",
+ 1, 2);
+ clks[MPC512x_CLK_MBX_UG] = mpc512x_clk_divtable("mbx-ug", "mbx-bus-ug",
+ &clkregs->scfr1, 14, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_MBX_3D_UG] = mpc512x_clk_factor("mbx-3d-ug", "mbx-ug",
+ 1, 1);
+ clks[MPC512x_CLK_PCI_UG] = mpc512x_clk_divtable("pci-ug", "csb",
+ &clkregs->scfr1, 20, 3,
+ divtab_2346);
+ clks[MPC512x_CLK_NFC_UG] = mpc512x_clk_divtable("nfc-ug", "ips",
+ &clkregs->scfr1, 8, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips",
+ &clkregs->scfr1, 11, 3,
+ divtab_1234);
+
+ clks[MPC512x_CLK_LPC] = mpc512x_clk_gated("lpc", "lpc-ug",
+ &clkregs->sccr1, 30);
+ clks[MPC512x_CLK_NFC] = mpc512x_clk_gated("nfc", "nfc-ug",
+ &clkregs->sccr1, 29);
+ clks[MPC512x_CLK_PATA] = mpc512x_clk_gated("pata", "ips",
+ &clkregs->sccr1, 28);
+ mpc512x_clk_setup_mclks(mclk_psc_data, ARRAY_SIZE(mclk_psc_data));
+ clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips",
+ &clkregs->sccr1, 15);
+ clks[MPC512x_CLK_SATA] = mpc512x_clk_gated("sata", "ips",
+ &clkregs->sccr1, 14);
+ clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips",
+ &clkregs->sccr1, 13);
+ clks[MPC512x_CLK_PCI] = mpc512x_clk_gated("pci", "pci-ug",
+ &clkregs->sccr1, 11);
+ clks[MPC512x_CLK_DDR] = mpc512x_clk_gated("ddr", "ddr-ug",
+ &clkregs->sccr1, 10);
+
+ clks[MPC512x_CLK_DIU] = mpc512x_clk_gated("diu", "diu-ug",
+ &clkregs->sccr2, 31);
+ clks[MPC512x_CLK_AXE] = mpc512x_clk_gated("axe", "csb",
+ &clkregs->sccr2, 30);
+ clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips",
+ &clkregs->sccr2, 29);
+ clks[MPC512x_CLK_USB1] = mpc512x_clk_gated("usb1", "csb",
+ &clkregs->sccr2, 28);
+ clks[MPC512x_CLK_USB2] = mpc512x_clk_gated("usb2", "csb",
+ &clkregs->sccr2, 27);
+ clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips",
+ &clkregs->sccr2, 26);
+ mpc512x_clk_setup_mclks(mclk_mscan_data, ARRAY_SIZE(mclk_mscan_data));
+ clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug",
+ &clkregs->sccr2, 24);
+ mpc512x_clk_setup_mclks(mclk_spdif_data, ARRAY_SIZE(mclk_spdif_data));
+ clks[MPC512x_CLK_MBX_BUS] = mpc512x_clk_gated("mbx-bus", "mbx-bus-ug",
+ &clkregs->sccr2, 22);
+ clks[MPC512x_CLK_MBX] = mpc512x_clk_gated("mbx", "mbx-ug",
+ &clkregs->sccr2, 21);
+ clks[MPC512x_CLK_MBX_3D] = mpc512x_clk_gated("mbx-3d", "mbx-3d-ug",
+ &clkregs->sccr2, 20);
+ clks[MPC512x_CLK_IIM] = mpc512x_clk_gated("iim", "csb",
+ &clkregs->sccr2, 19);
+ clks[MPC512x_CLK_VIU] = mpc512x_clk_gated("viu", "csb",
+ &clkregs->sccr2, 18);
+ clks[MPC512x_CLK_SDHC_2] = mpc512x_clk_gated("sdhc-2", "sdhc-ug",
+ &clkregs->sccr2, 17);
+
+ /*
+ * externally provided clocks (when implemented in hardware,
+ * device tree may specify values which otherwise were unknown)
+ */
+ freq = get_freq_from_dt("psc_mclk_in");
+ if (!freq)
+ freq = 25000000;
+ clks[MPC512x_CLK_PSC_MCLK_IN] = mpc512x_clk_fixed("psc_mclk_in", freq);
+ freq = get_freq_from_dt("spdif_tx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_tx_in", freq);
+ freq = get_freq_from_dt("spdif_rx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_rx_in", freq);
+
+ /* fixed frequency for AC97, always 24.567MHz */
+ clks[MPC512x_CLK_AC97] = mpc512x_clk_fixed("ac97", 24567000);
+
+ pr_debug("clock tree setup complete\n");
+ freq = clk_get_rate(clks[MPC512x_CLK_E300]);
+ pr_debug("derived PPC freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_IPS]);
+ pr_debug("derived IPS freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_LPC]);
+ pr_debug("derived LPC freq [%d]\n", freq);
+
+ /* enable some of the clocks here unconditionally because ... */
+ pr_debug("automatically enabling some clocks\n");
+ /* some are essential yet never get claimed by any driver */
+ clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
+ clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */
+ clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
+ clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
+ /* some are required yet no dependencies were declared */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
+ /* some are not yet acquired by their respective drivers */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
+ clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
+ clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
+ clk_prepare_enable(clks[MPC512x_CLK_I2C]);
+ /*
+ * some have their individual clock subtree with separate clock
+ * items and their individual enable counters, yet share a
+ * common gate (refer to the same register location) while the
+ * common clock driver code is not aware of the fact and the
+ * platform's code doesn't provide specific support either
+ *
+ * what might happen is that e.g. enabling two MSCAN clock items
+ * and disabling one of them will disable the common gate and
+ * thus break the other MSCAN clock as well
+ */
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN0_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN1_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN2_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN3_MCLK]);
+}
+
+/*
+ * registers the set of public clocks (those listed in the dt-bindings/
+ * header file) for OF lookups, keeps the intermediates private to us
+ */
+static void mpc5121_clk_register_of_provider(struct device_node *np)
+{
+ clk_data.clks = clks;
+ clk_data.clk_num = MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_SIZE() */
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+int __init mpc5121_clk_init(void)
+{
+ struct device_node *clk_np;
+ int busfreq;
+
+ /* map the clock control registers */
+ clk_np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ if (!clk_np)
+ return -ENODEV;
+ clkregs = of_iomap(clk_np, 0);
+ WARN_ON(!clkregs);
+
+ /* invalidate all not yet registered clock slots */
+ mpc512x_clk_preset_data();
+
+ /*
+ * have the device tree scanned for "fixed-clock" nodes (which
+ * includes the oscillator node if the board's DT provides one)
+ */
+ of_clk_init(NULL);
+
+ /*
+ * add a dummy clock for those situations where a clock spec is
+ * required yet no real clock is involved
+ */
+ clks[MPC512x_CLK_DUMMY] = mpc512x_clk_fixed("dummy", 0);
+
+ /*
+ * have all the real nodes in the clock tree populated from REF
+ * down to all leaves, either starting from the OSC node or from
+ * a REF root that was created from the IPS bus clock input
+ */
+ busfreq = get_freq_from_dt("bus-frequency");
+ mpc512x_clk_setup_clock_tree(busfreq);
+
+ /* register as an OF clock provider */
+ mpc5121_clk_register_of_provider(clk_np);
+
+ return 0;
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c4f7799..7f8fc64 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -497,6 +497,20 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
* for improved portability across platforms
*/
+#if IS_ENABLED(CONFIG_PPC)
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return ioread32be(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ iowrite32be(val, reg);
+}
+
+#else /* platform dependent I/O accessors */
+
static inline u32 clk_readl(u32 __iomem *reg)
{
return readl(reg);
@@ -507,5 +521,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
writel(val, reg);
}
+#endif /* platform dependent I/O accessors */
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 09/24] clk: mpc512x: introduce COMMON_CLK for MPC512x
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this change introduces a clock infrastructure implementation for the
MPC512x PowerPC platform which follows the COMMON_CLK approach and uses
common clock drivers shared with other platforms
this driver implements the publicly announced set of clocks (which can
get referenced by means of symbolic identifiers from the dt-bindings
header file), as well as generates additional 'struct clk' items where
the SoC hardware cannot easily get mapped to the common primitives of
the clock API, or requires "intermediate" clock nodes to represent
clocks that have both gates and dividers
the previous PPC_CLOCK implementation is kept in place and resides in
parallel to the common clock implementation for test and comparison
during migration, a compile time option picks one of the two
alternatives (Kconfig switch, common clock used by default)
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/Kconfig | 14 +-
arch/powerpc/platforms/512x/Makefile | 4 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 777 +++++++++++++++++++++++++
include/linux/clk-provider.h | 16 +
4 files changed, 809 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index fc9c1cb..c5fcdd0 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,9 +1,21 @@
+config MPC512x_COMMON_CLK
+ bool "MPC512x platform uses COMMON_CLK"
+ default y
+ depends on PPC_MPC512x
+ help
+ This option is only here to support tests and comparison
+ during development and migration. This option will get
+ removed after the COMMON_CLK support for MPC512x has become
+ fully operational and all drivers were adjusted to explicitly
+ acquire their required clocks.
+
config PPC_MPC512x
bool "512x-based boards"
depends on 6xx
select FSL_SOC
select IPIC
- select PPC_CLOCK
+ select PPC_CLOCK if !MPC512x_COMMON_CLK
+ select COMMON_CLK if MPC512x_COMMON_CLK
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 72fb934..1e05f9d 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,7 +1,9 @@
#
# Makefile for the Freescale PowerPC 512x linux kernel.
#
-obj-y += clock.o mpc512x_shared.o
+obj-$(CONFIG_PPC_CLOCK) += clock.o
+obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
+obj-y += mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o
obj-$(CONFIG_PDM360NG) += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
new file mode 100644
index 0000000..218f55b
--- /dev/null
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -0,0 +1,777 @@
+/*
+ * Copyright (C) 2013 DENX Software Engineering
+ *
+ * Gerhard Sittig, <gsi@denx.de>
+ *
+ * common clock driver support for the MPC512x platform
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <asm/mpc5121.h>
+#include <dt-bindings/clock/mpc512x-clock.h>
+
+#include "mpc512x.h" /* our public mpc5121_clk_init() API */
+
+/* helpers to keep the MCLK intermediates "somewhere" in our table */
+enum {
+ MCLK_IDX_MUX0,
+ MCLK_IDX_EN0,
+ MCLK_IDX_DIV0,
+ MCLK_IDX_MUX1,
+ MCLK_MAX_IDX,
+};
+
+#define NR_PSCS 12
+#define NR_MSCANS 4
+#define NR_SPDIFS 1
+#define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS)
+
+/* extend the public set of clocks by adding internal slots for management */
+enum {
+ /* arrange for adjacent numbers after the public set */
+ MPC512x_CLK_START_PRIVATE = MPC512x_CLK_LAST_PUBLIC,
+ /* clocks which aren't announced to the public */
+ MPC512x_CLK_DDR,
+ MPC512x_CLK_MEM,
+ MPC512x_CLK_IIM,
+ MPC512x_CLK_SDHC_2,
+ /* intermediates in div+gate combos or fractional dividers */
+ MPC512x_CLK_DDR_UG,
+ MPC512x_CLK_SDHC_x4,
+ MPC512x_CLK_SDHC_UG,
+ MPC512x_CLK_DIU_x4,
+ MPC512x_CLK_DIU_UG,
+ MPC512x_CLK_MBX_BUS_UG,
+ MPC512x_CLK_MBX_UG,
+ MPC512x_CLK_MBX_3D_UG,
+ MPC512x_CLK_PCI_UG,
+ MPC512x_CLK_NFC_UG,
+ MPC512x_CLK_LPC_UG,
+ MPC512x_CLK_SPDIF_TX_IN,
+ /* intermediates for the mux+gate+div+mux MCLK generation */
+ MPC512x_CLK_MCLKS_FIRST,
+ MPC512x_CLK_MCLKS_LAST = MPC512x_CLK_MCLKS_FIRST
+ + NR_MCLKS * MCLK_MAX_IDX,
+ /* internal, symbolic spec for the number of slots */
+ MPC512x_CLK_LAST_PRIVATE,
+};
+
+/* data required for the OF clock provider registration */
+static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
+static struct clk_onecell_data clk_data;
+
+/* CCM register access */
+static struct mpc512x_ccm __iomem *clkregs;
+static DEFINE_SPINLOCK(clklock);
+
+/* convenience wrappers around the common clk API */
+static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
+{
+ return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *mpc512x_clk_factor(
+ const char *name, const char *parent_name,
+ int mul, int div)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_fixed_factor(NULL, name, parent_name, clkflags,
+ mul, div);
+}
+
+static inline struct clk *mpc512x_clk_divider(
+ const char *name, const char *parent_name, u8 clkflags,
+ u32 __iomem *reg, u8 pos, u8 len, int divflags)
+{
+ return clk_register_divider(NULL, name, parent_name, clkflags,
+ reg, pos, len, divflags, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_divtable(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos, u8 len,
+ const struct clk_div_table *divtab)
+{
+ u8 divflags;
+
+ divflags = 0;
+ return clk_register_divider_table(NULL, name, parent_name, 0,
+ reg, pos, len, divflags,
+ divtab, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_gated(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_gate(NULL, name, parent_name, clkflags,
+ reg, pos, 0, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_muxed(const char *name,
+ const char **parent_names, int parent_count,
+ u32 __iomem *reg, u8 pos, u8 len)
+{
+ int clkflags;
+ u8 muxflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ muxflags = 0;
+ return clk_register_mux(NULL, name,
+ parent_names, parent_count, clkflags,
+ reg, pos, len, muxflags, &clklock);
+}
+
+/* helper to isolate a bit field from a register */
+static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len)
+{
+ uint32_t val;
+
+ val = in_be32(reg);
+ val >>= pos;
+ val &= (1 << len) - 1;
+ return val;
+}
+
+/* get the SPMF and translate it into the "sys pll" multiplier */
+static int get_spmf_mult(void)
+{
+ static int spmf_to_mult[] = {
+ 68, 1, 12, 16, 20, 24, 28, 32,
+ 36, 40, 44, 48, 52, 56, 60, 64,
+ };
+ int spmf;
+
+ spmf = get_bit_field(&clkregs->spmr, 24, 4);
+ return spmf_to_mult[spmf];
+}
+
+/*
+ * get the SYS_DIV value and translate it into a divide factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * divide ratio is fractional
+ */
+static int get_sys_div_x2(void)
+{
+ static int sysdiv_code_to_x2[] = {
+ 4, 5, 6, 7, 8, 9, 10, 14,
+ 12, 16, 18, 22, 20, 24, 26, 30,
+ 28, 32, 34, 38, 36, 40, 42, 46,
+ 44, 48, 50, 54, 52, 56, 58, 62,
+ 60, 64, 66,
+ };
+ int divcode;
+
+ divcode = get_bit_field(&clkregs->scfr2, 26, 6);
+ return sysdiv_code_to_x2[divcode];
+}
+
+/*
+ * get the CPMF value and translate it into a multiplier factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * multiplier ratio is fractional
+ */
+static int get_cpmf_mult_x2(void)
+{
+ static int cpmf_to_mult[] = {
+ 72, 2, 2, 3, 4, 5, 6, 7,
+ };
+ int cpmf;
+
+ cpmf = get_bit_field(&clkregs->spmr, 16, 4);
+ return cpmf_to_mult[cpmf];
+}
+
+/*
+ * some of the clock dividers do scale in a linear way, yet not all of
+ * their bit combinations are legal; use a divider table to get a
+ * resulting set of applicable divider values
+ */
+
+/* applies to the IPS_DIV, and PCI_DIV values */
+static struct clk_div_table divtab_2346[] = {
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .val = 6, .div = 6, },
+ { .div = 0, },
+};
+
+/* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
+static struct clk_div_table divtab_1234[] = {
+ { .val = 1, .div = 1, },
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .div = 0, },
+};
+
+static int get_freq_from_dt(char *propname)
+{
+ struct device_node *np;
+ const unsigned int *prop;
+ int val;
+
+ val = 0;
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
+ if (np) {
+ prop = of_get_property(np, propname, NULL);
+ if (prop)
+ val = *prop;
+ of_node_put(np);
+ }
+ return val;
+}
+
+static void mpc512x_clk_preset_data(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++)
+ clks[i] = ERR_PTR(-ENODEV);
+}
+
+/*
+ * - receives the "bus frequency" from the caller (that's the IPS clock
+ * rate, the historical source of clock information)
+ * - fetches the system PLL multiplier and divider values as well as the
+ * IPS divider value from hardware
+ * - determines the REF clock rate either from the XTAL/OSC spec (if
+ * there is a device tree node describing the oscillator) or from the
+ * IPS bus clock (supported for backwards compatibility, such that
+ * setups without XTAL/OSC specs keep working)
+ * - creates the "ref" clock item in the clock tree, such that
+ * subsequent code can create the remainder of the hierarchy (REF ->
+ * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
+ * values
+ */
+static void mpc512x_clk_setup_ref_clock(int bus_freq,
+ int *sys_mul, int *sys_div, int *ips_div)
+{
+ struct clk *osc_clk;
+ int calc_freq;
+
+ /* fetch mul/div factors from the hardware */
+ *sys_mul = get_spmf_mult();
+ *sys_mul *= 2; /* compensate for the fractional divider */
+ *sys_div = get_sys_div_x2();
+ *ips_div = get_bit_field(&clkregs->scfr1, 23, 3);
+
+ /* lookup the oscillator node */
+ osc_clk = clk_get(NULL, "osc");
+ if (osc_clk) {
+ /* descend REF directly from OSC, verify the IPS rate */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1);
+ calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]);
+ calc_freq *= *sys_mul;
+ calc_freq /= *sys_div;
+ calc_freq /= 2;
+ calc_freq /= *ips_div;
+ if (bus_freq && calc_freq != bus_freq)
+ pr_warn("calc rate %d != OF spec %d\n",
+ calc_freq, bus_freq);
+ } else {
+ /* calculate OSC rate and create REF from the freq value */
+ calc_freq = bus_freq; /* start with IPS */
+ calc_freq *= *ips_div; /* IPS -> CSB */
+ calc_freq *= 2; /* CSB -> SYS */
+ calc_freq *= *sys_div; /* SYS -> PLL out */
+ calc_freq /= *sys_mul; /* PLL out -> REF == OSC */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq);
+ }
+}
+
+/*
+ * helper code for the MCLK subtree setup
+ *
+ * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
+ * suggests that all instances of the "PSC clock generation" are equal,
+ * and that one might re-use the PSC setup for MSCAN clock generation
+ * (section 5.2.5) as well, at least the logic if not the data for
+ * description
+ *
+ * the details (starting at page 5-20) show differences in the specific
+ * inputs of the first mux stage ("can clk in", "spdif tx"), and the
+ * factual non-availability of the second mux stage (it's present yet
+ * only one input is valid)
+ *
+ * the MSCAN clock related registers (starting at page 5-35) all
+ * reference "spdif clk" at the first mux stage and don't mention any
+ * "can clk" at all, which somehow is unexpected
+ *
+ * TODO re-check the document, and clarify whether the RM is correct in
+ * the overview or in the details, and whether the difference is a
+ * clipboard induced error or results from chip revisions
+ *
+ * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
+ * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
+ * first a doc update is required which better reflects reality in the
+ * SoC before the implementation should follow while no questions remain
+ */
+
+/*
+ * note that this declaration raises a checkpatch warning, but
+ * it's the very data type which <linux/clk-provider.h> expects,
+ * making this declaration pass checkpatch will break compilation
+ */
+static const char *parent_names_mux0[] = {
+ "sys", "ref", "psc-mclk-in", "spdif-tx",
+};
+
+enum mclk_type {
+ MCLK_TYPE_PSC,
+ MCLK_TYPE_MSCAN,
+ MCLK_TYPE_SPDIF,
+};
+
+struct mclk_setup_data {
+ enum mclk_type type;
+ int comp_idx;
+ bool has_mclk1;
+ int bit_sccr1, bit_sccr2;
+ const char *name_mux0;
+ const char *name_en0;
+ const char *name_div0;
+ const char *parent_names_mux1[2];
+ const char *name_mux1;
+ const char *name_mclk;
+};
+
+#define MCLK_SETUP_DATA_PSC(id) { \
+ MCLK_TYPE_PSC, id, \
+ 0, 27 - id, -1, \
+ "psc" #id "-mux0", \
+ "psc" #id "-en0", \
+ "psc" #id "_mclk_div", \
+ { "psc" #id "_mclk_div", "dummy", }, \
+ "psc" #id "_mclk_out", \
+ "psc" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_MSCAN(id) { \
+ MCLK_TYPE_MSCAN, id, \
+ 0, -1, 25, \
+ "mscan" #id "-mux0", \
+ "mscan" #id "-en0", \
+ "mscan" #id "_mclk_div", \
+ { "mscan" #id "_mclk_div", "dummy", }, \
+ "mscan" #id "_mclk_out", \
+ "mscan" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_SPDIF { \
+ MCLK_TYPE_SPDIF, 0, \
+ 1, -1, 23, \
+ "spdif-mux0", \
+ "spdif-en0", \
+ "spdif_mclk_div", \
+ { "spdif_mclk_div", "spdif-rx", }, \
+ "spdif_mclk_out", \
+ "spdif_mclk", \
+}
+
+static struct mclk_setup_data mclk_psc_data[] = {
+ MCLK_SETUP_DATA_PSC(0),
+ MCLK_SETUP_DATA_PSC(1),
+ MCLK_SETUP_DATA_PSC(2),
+ MCLK_SETUP_DATA_PSC(3),
+ MCLK_SETUP_DATA_PSC(4),
+ MCLK_SETUP_DATA_PSC(5),
+ MCLK_SETUP_DATA_PSC(6),
+ MCLK_SETUP_DATA_PSC(7),
+ MCLK_SETUP_DATA_PSC(8),
+ MCLK_SETUP_DATA_PSC(9),
+ MCLK_SETUP_DATA_PSC(10),
+ MCLK_SETUP_DATA_PSC(11),
+};
+
+static struct mclk_setup_data mclk_mscan_data[] = {
+ MCLK_SETUP_DATA_MSCAN(0),
+ MCLK_SETUP_DATA_MSCAN(1),
+ MCLK_SETUP_DATA_MSCAN(2),
+ MCLK_SETUP_DATA_MSCAN(3),
+};
+
+static struct mclk_setup_data mclk_spdif_data[] = {
+ MCLK_SETUP_DATA_SPDIF,
+};
+
+/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
+static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
+{
+ size_t clks_idx_pub, clks_idx_int;
+ u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */
+ u32 __iomem *sccr_reg; /* system clock control register (enable) */
+ int sccr_bit;
+ int div;
+
+ /* derive a few parameters from the component type and index */
+ switch (entry->type) {
+ case MCLK_TYPE_PSC:
+ clks_idx_pub = MPC512x_CLK_PSC0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->psc_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_MSCAN:
+ clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->mscan_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_SPDIF:
+ clks_idx_pub = MPC512x_CLK_SPDIF_MCLK;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->spccr;
+ break;
+ default:
+ return;
+ }
+ if (entry->bit_sccr1 >= 0) {
+ sccr_reg = &clkregs->sccr1;
+ sccr_bit = entry->bit_sccr1;
+ } else if (entry->bit_sccr2 >= 0) {
+ sccr_reg = &clkregs->sccr2;
+ sccr_bit = entry->bit_sccr2;
+ } else {
+ sccr_reg = NULL;
+ }
+
+ /*
+ * this was grabbed from the PPC_CLOCK implementation, which
+ * enforced a specific MCLK divider while the clock was gated
+ * during setup (that's a documented hardware requirement)
+ *
+ * the PPC_CLOCK implementation might even have violated the
+ * "MCLK <= IPS" constraint, the fixed divider value of 1
+ * results in a divider of 2 and thus MCLK = SYS/2 which equals
+ * CSB which is greater than IPS; the serial port setup may have
+ * adjusted the divider which the clock setup might have left in
+ * an undesirable state
+ *
+ * initial setup is:
+ * - MCLK 0 from SYS
+ * - MCLK DIV such to not exceed the IPS clock
+ * - MCLK 0 enabled
+ * - MCLK 1 from MCLK DIV
+ */
+ div = clk_get_rate(clks[MPC512x_CLK_SYS]);
+ div /= clk_get_rate(clks[MPC512x_CLK_IPS]);
+ out_be32(mccr_reg, (0 << 16));
+ out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
+ out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
+
+ /*
+ * create the 'struct clk' items of the MCLK's clock subtree
+ *
+ * note that by design we always create all nodes and won't take
+ * shortcuts here, because
+ * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
+ * selectable inputs to the CFM while those who "actually use"
+ * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
+ * for their bitrate
+ * - in the absence of "aliases" for clocks we need to create
+ * individial 'struct clk' items for whatever might get
+ * referenced or looked up, even if several of those items are
+ * identical from the logical POV (their rate value)
+ * - for easier future maintenance and for better reflection of
+ * the SoC's documentation, it appears appropriate to generate
+ * clock items even for those muxers which actually are NOPs
+ * (those with two inputs of which one is reserved)
+ */
+ clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed(
+ entry->name_mux0,
+ &parent_names_mux0[0], ARRAY_SIZE(parent_names_mux0),
+ mccr_reg, 14, 2);
+ clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated(
+ entry->name_en0, entry->name_mux0,
+ mccr_reg, 16);
+ clks[clks_idx_int + MCLK_IDX_DIV0] = mpc512x_clk_divider(
+ entry->name_div0,
+ entry->name_en0, CLK_SET_RATE_GATE,
+ mccr_reg, 17, 15, 0);
+ if (entry->has_mclk1) {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_muxed(
+ entry->name_mux1,
+ &entry->parent_names_mux1[0],
+ ARRAY_SIZE(entry->parent_names_mux1),
+ mccr_reg, 7, 1);
+ } else {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_factor(
+ entry->name_mux1, entry->parent_names_mux1[0],
+ 1, 1);
+ }
+ if (sccr_reg) {
+ clks[clks_idx_pub] = mpc512x_clk_gated(
+ entry->name_mclk,
+ entry->name_mux1, sccr_reg, sccr_bit);
+ } else {
+ clks[clks_idx_pub] = mpc512x_clk_factor(
+ entry->name_mclk,
+ entry->name_mux1, 1, 1);
+ }
+
+ /*
+ * without this "clock device" registration, "simple" lookups in
+ * the SPI master initialization and serial port setup will fail
+ *
+ * those drivers need to get adjusted to lookup their required
+ * clocks from OF specs, before this clkdev registration becomes
+ * obsolete
+ */
+ clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
+}
+
+static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
+{
+ while (count-- > 0)
+ mpc512x_clk_setup_mclk(table++);
+}
+
+static void mpc512x_clk_setup_clock_tree(int busfreq)
+{
+ int sys_mul, sys_div, ips_div;
+ int mul, div;
+ int freq;
+
+ /*
+ * TODO
+ * - consider whether to handle clocks which have both gates and
+ * dividers via intermediates or by means of composites
+ * - fractional dividers appear to not map well to composites
+ * since they can be seen as a fixed multiplier and an
+ * adjustable divider, while composites can only combine at
+ * most one of a mux, div, and gate each into one 'struct clk'
+ * item
+ * - PSC/MSCAN/SPDIF clock generation OTOH already is very
+ * specific and cannot get mapped to componsites (at least not
+ * a single one, maybe two of them, but see the comment about
+ * "intermediates are referenced from elsewhere, too")
+ * - trim the list of auto-enabled clocks after drivers acquire
+ * them correctly as needed
+ */
+
+ /* regardless of whether XTAL/OSC exists, have REF created */
+ mpc512x_clk_setup_ref_clock(busfreq, &sys_mul, &sys_div, &ips_div);
+
+ /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
+ clks[MPC512x_CLK_SYS] = mpc512x_clk_factor("sys", "ref",
+ sys_mul, sys_div);
+ clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2);
+ clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb",
+ &clkregs->scfr1, 23, 3,
+ divtab_2346);
+
+ /* now setup anything below SYS and CSB and IPS */
+ clks[MPC512x_CLK_DDR_UG] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2);
+ clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0,
+ &clkregs->scfr2, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+ clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_DIU_UG] = mpc512x_clk_divider("diu-ug", "diu-x4", 0,
+ &clkregs->scfr1, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+
+ /*
+ * the "power architecture PLL" was setup from data which was
+ * sampled from the reset config word, at this point in time the
+ * configuration can be considered fixed and read only (i.e. no
+ * longer adjustable, or no longer in need of adjustment), which
+ * is why we don't register a PLL here but assume fixed factors
+ */
+ mul = get_cpmf_mult_x2();
+ div = 2; /* compensate for the fractional factor */
+ clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div);
+
+ clks[MPC512x_CLK_MBX_BUS_UG] = mpc512x_clk_factor("mbx-bus-ug", "csb",
+ 1, 2);
+ clks[MPC512x_CLK_MBX_UG] = mpc512x_clk_divtable("mbx-ug", "mbx-bus-ug",
+ &clkregs->scfr1, 14, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_MBX_3D_UG] = mpc512x_clk_factor("mbx-3d-ug", "mbx-ug",
+ 1, 1);
+ clks[MPC512x_CLK_PCI_UG] = mpc512x_clk_divtable("pci-ug", "csb",
+ &clkregs->scfr1, 20, 3,
+ divtab_2346);
+ clks[MPC512x_CLK_NFC_UG] = mpc512x_clk_divtable("nfc-ug", "ips",
+ &clkregs->scfr1, 8, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips",
+ &clkregs->scfr1, 11, 3,
+ divtab_1234);
+
+ clks[MPC512x_CLK_LPC] = mpc512x_clk_gated("lpc", "lpc-ug",
+ &clkregs->sccr1, 30);
+ clks[MPC512x_CLK_NFC] = mpc512x_clk_gated("nfc", "nfc-ug",
+ &clkregs->sccr1, 29);
+ clks[MPC512x_CLK_PATA] = mpc512x_clk_gated("pata", "ips",
+ &clkregs->sccr1, 28);
+ mpc512x_clk_setup_mclks(mclk_psc_data, ARRAY_SIZE(mclk_psc_data));
+ clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips",
+ &clkregs->sccr1, 15);
+ clks[MPC512x_CLK_SATA] = mpc512x_clk_gated("sata", "ips",
+ &clkregs->sccr1, 14);
+ clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips",
+ &clkregs->sccr1, 13);
+ clks[MPC512x_CLK_PCI] = mpc512x_clk_gated("pci", "pci-ug",
+ &clkregs->sccr1, 11);
+ clks[MPC512x_CLK_DDR] = mpc512x_clk_gated("ddr", "ddr-ug",
+ &clkregs->sccr1, 10);
+
+ clks[MPC512x_CLK_DIU] = mpc512x_clk_gated("diu", "diu-ug",
+ &clkregs->sccr2, 31);
+ clks[MPC512x_CLK_AXE] = mpc512x_clk_gated("axe", "csb",
+ &clkregs->sccr2, 30);
+ clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips",
+ &clkregs->sccr2, 29);
+ clks[MPC512x_CLK_USB1] = mpc512x_clk_gated("usb1", "csb",
+ &clkregs->sccr2, 28);
+ clks[MPC512x_CLK_USB2] = mpc512x_clk_gated("usb2", "csb",
+ &clkregs->sccr2, 27);
+ clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips",
+ &clkregs->sccr2, 26);
+ mpc512x_clk_setup_mclks(mclk_mscan_data, ARRAY_SIZE(mclk_mscan_data));
+ clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug",
+ &clkregs->sccr2, 24);
+ mpc512x_clk_setup_mclks(mclk_spdif_data, ARRAY_SIZE(mclk_spdif_data));
+ clks[MPC512x_CLK_MBX_BUS] = mpc512x_clk_gated("mbx-bus", "mbx-bus-ug",
+ &clkregs->sccr2, 22);
+ clks[MPC512x_CLK_MBX] = mpc512x_clk_gated("mbx", "mbx-ug",
+ &clkregs->sccr2, 21);
+ clks[MPC512x_CLK_MBX_3D] = mpc512x_clk_gated("mbx-3d", "mbx-3d-ug",
+ &clkregs->sccr2, 20);
+ clks[MPC512x_CLK_IIM] = mpc512x_clk_gated("iim", "csb",
+ &clkregs->sccr2, 19);
+ clks[MPC512x_CLK_VIU] = mpc512x_clk_gated("viu", "csb",
+ &clkregs->sccr2, 18);
+ clks[MPC512x_CLK_SDHC_2] = mpc512x_clk_gated("sdhc-2", "sdhc-ug",
+ &clkregs->sccr2, 17);
+
+ /*
+ * externally provided clocks (when implemented in hardware,
+ * device tree may specify values which otherwise were unknown)
+ */
+ freq = get_freq_from_dt("psc_mclk_in");
+ if (!freq)
+ freq = 25000000;
+ clks[MPC512x_CLK_PSC_MCLK_IN] = mpc512x_clk_fixed("psc_mclk_in", freq);
+ freq = get_freq_from_dt("spdif_tx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_tx_in", freq);
+ freq = get_freq_from_dt("spdif_rx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_rx_in", freq);
+
+ /* fixed frequency for AC97, always 24.567MHz */
+ clks[MPC512x_CLK_AC97] = mpc512x_clk_fixed("ac97", 24567000);
+
+ pr_debug("clock tree setup complete\n");
+ freq = clk_get_rate(clks[MPC512x_CLK_E300]);
+ pr_debug("derived PPC freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_IPS]);
+ pr_debug("derived IPS freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_LPC]);
+ pr_debug("derived LPC freq [%d]\n", freq);
+
+ /* enable some of the clocks here unconditionally because ... */
+ pr_debug("automatically enabling some clocks\n");
+ /* some are essential yet never get claimed by any driver */
+ clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
+ clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */
+ clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
+ clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
+ /* some are required yet no dependencies were declared */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
+ /* some are not yet acquired by their respective drivers */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
+ clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
+ clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
+ clk_prepare_enable(clks[MPC512x_CLK_I2C]);
+ /*
+ * some have their individual clock subtree with separate clock
+ * items and their individual enable counters, yet share a
+ * common gate (refer to the same register location) while the
+ * common clock driver code is not aware of the fact and the
+ * platform's code doesn't provide specific support either
+ *
+ * what might happen is that e.g. enabling two MSCAN clock items
+ * and disabling one of them will disable the common gate and
+ * thus break the other MSCAN clock as well
+ */
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN0_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN1_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN2_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN3_MCLK]);
+}
+
+/*
+ * registers the set of public clocks (those listed in the dt-bindings/
+ * header file) for OF lookups, keeps the intermediates private to us
+ */
+static void mpc5121_clk_register_of_provider(struct device_node *np)
+{
+ clk_data.clks = clks;
+ clk_data.clk_num = MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_SIZE() */
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+int __init mpc5121_clk_init(void)
+{
+ struct device_node *clk_np;
+ int busfreq;
+
+ /* map the clock control registers */
+ clk_np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ if (!clk_np)
+ return -ENODEV;
+ clkregs = of_iomap(clk_np, 0);
+ WARN_ON(!clkregs);
+
+ /* invalidate all not yet registered clock slots */
+ mpc512x_clk_preset_data();
+
+ /*
+ * have the device tree scanned for "fixed-clock" nodes (which
+ * includes the oscillator node if the board's DT provides one)
+ */
+ of_clk_init(NULL);
+
+ /*
+ * add a dummy clock for those situations where a clock spec is
+ * required yet no real clock is involved
+ */
+ clks[MPC512x_CLK_DUMMY] = mpc512x_clk_fixed("dummy", 0);
+
+ /*
+ * have all the real nodes in the clock tree populated from REF
+ * down to all leaves, either starting from the OSC node or from
+ * a REF root that was created from the IPS bus clock input
+ */
+ busfreq = get_freq_from_dt("bus-frequency");
+ mpc512x_clk_setup_clock_tree(busfreq);
+
+ /* register as an OF clock provider */
+ mpc5121_clk_register_of_provider(clk_np);
+
+ return 0;
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c4f7799..7f8fc64 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -497,6 +497,20 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
* for improved portability across platforms
*/
+#if IS_ENABLED(CONFIG_PPC)
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return ioread32be(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ iowrite32be(val, reg);
+}
+
+#else /* platform dependent I/O accessors */
+
static inline u32 clk_readl(u32 __iomem *reg)
{
return readl(reg);
@@ -507,5 +521,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
writel(val, reg);
}
+#endif /* platform dependent I/O accessors */
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 09/24] clk: mpc512x: introduce COMMON_CLK for MPC512x
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
this change introduces a clock infrastructure implementation for the
MPC512x PowerPC platform which follows the COMMON_CLK approach and uses
common clock drivers shared with other platforms
this driver implements the publicly announced set of clocks (which can
get referenced by means of symbolic identifiers from the dt-bindings
header file), as well as generates additional 'struct clk' items where
the SoC hardware cannot easily get mapped to the common primitives of
the clock API, or requires "intermediate" clock nodes to represent
clocks that have both gates and dividers
the previous PPC_CLOCK implementation is kept in place and resides in
parallel to the common clock implementation for test and comparison
during migration, a compile time option picks one of the two
alternatives (Kconfig switch, common clock used by default)
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/Kconfig | 14 +-
arch/powerpc/platforms/512x/Makefile | 4 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 777 +++++++++++++++++++++++++
include/linux/clk-provider.h | 16 +
4 files changed, 809 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index fc9c1cb..c5fcdd0 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,9 +1,21 @@
+config MPC512x_COMMON_CLK
+ bool "MPC512x platform uses COMMON_CLK"
+ default y
+ depends on PPC_MPC512x
+ help
+ This option is only here to support tests and comparison
+ during development and migration. This option will get
+ removed after the COMMON_CLK support for MPC512x has become
+ fully operational and all drivers were adjusted to explicitly
+ acquire their required clocks.
+
config PPC_MPC512x
bool "512x-based boards"
depends on 6xx
select FSL_SOC
select IPIC
- select PPC_CLOCK
+ select PPC_CLOCK if !MPC512x_COMMON_CLK
+ select COMMON_CLK if MPC512x_COMMON_CLK
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 72fb934..1e05f9d 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,7 +1,9 @@
#
# Makefile for the Freescale PowerPC 512x linux kernel.
#
-obj-y += clock.o mpc512x_shared.o
+obj-$(CONFIG_PPC_CLOCK) += clock.o
+obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
+obj-y += mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o
obj-$(CONFIG_PDM360NG) += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
new file mode 100644
index 0000000..218f55b
--- /dev/null
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -0,0 +1,777 @@
+/*
+ * Copyright (C) 2013 DENX Software Engineering
+ *
+ * Gerhard Sittig, <gsi@denx.de>
+ *
+ * common clock driver support for the MPC512x platform
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <asm/mpc5121.h>
+#include <dt-bindings/clock/mpc512x-clock.h>
+
+#include "mpc512x.h" /* our public mpc5121_clk_init() API */
+
+/* helpers to keep the MCLK intermediates "somewhere" in our table */
+enum {
+ MCLK_IDX_MUX0,
+ MCLK_IDX_EN0,
+ MCLK_IDX_DIV0,
+ MCLK_IDX_MUX1,
+ MCLK_MAX_IDX,
+};
+
+#define NR_PSCS 12
+#define NR_MSCANS 4
+#define NR_SPDIFS 1
+#define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS)
+
+/* extend the public set of clocks by adding internal slots for management */
+enum {
+ /* arrange for adjacent numbers after the public set */
+ MPC512x_CLK_START_PRIVATE = MPC512x_CLK_LAST_PUBLIC,
+ /* clocks which aren't announced to the public */
+ MPC512x_CLK_DDR,
+ MPC512x_CLK_MEM,
+ MPC512x_CLK_IIM,
+ MPC512x_CLK_SDHC_2,
+ /* intermediates in div+gate combos or fractional dividers */
+ MPC512x_CLK_DDR_UG,
+ MPC512x_CLK_SDHC_x4,
+ MPC512x_CLK_SDHC_UG,
+ MPC512x_CLK_DIU_x4,
+ MPC512x_CLK_DIU_UG,
+ MPC512x_CLK_MBX_BUS_UG,
+ MPC512x_CLK_MBX_UG,
+ MPC512x_CLK_MBX_3D_UG,
+ MPC512x_CLK_PCI_UG,
+ MPC512x_CLK_NFC_UG,
+ MPC512x_CLK_LPC_UG,
+ MPC512x_CLK_SPDIF_TX_IN,
+ /* intermediates for the mux+gate+div+mux MCLK generation */
+ MPC512x_CLK_MCLKS_FIRST,
+ MPC512x_CLK_MCLKS_LAST = MPC512x_CLK_MCLKS_FIRST
+ + NR_MCLKS * MCLK_MAX_IDX,
+ /* internal, symbolic spec for the number of slots */
+ MPC512x_CLK_LAST_PRIVATE,
+};
+
+/* data required for the OF clock provider registration */
+static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
+static struct clk_onecell_data clk_data;
+
+/* CCM register access */
+static struct mpc512x_ccm __iomem *clkregs;
+static DEFINE_SPINLOCK(clklock);
+
+/* convenience wrappers around the common clk API */
+static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
+{
+ return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *mpc512x_clk_factor(
+ const char *name, const char *parent_name,
+ int mul, int div)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_fixed_factor(NULL, name, parent_name, clkflags,
+ mul, div);
+}
+
+static inline struct clk *mpc512x_clk_divider(
+ const char *name, const char *parent_name, u8 clkflags,
+ u32 __iomem *reg, u8 pos, u8 len, int divflags)
+{
+ return clk_register_divider(NULL, name, parent_name, clkflags,
+ reg, pos, len, divflags, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_divtable(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos, u8 len,
+ const struct clk_div_table *divtab)
+{
+ u8 divflags;
+
+ divflags = 0;
+ return clk_register_divider_table(NULL, name, parent_name, 0,
+ reg, pos, len, divflags,
+ divtab, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_gated(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_gate(NULL, name, parent_name, clkflags,
+ reg, pos, 0, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_muxed(const char *name,
+ const char **parent_names, int parent_count,
+ u32 __iomem *reg, u8 pos, u8 len)
+{
+ int clkflags;
+ u8 muxflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ muxflags = 0;
+ return clk_register_mux(NULL, name,
+ parent_names, parent_count, clkflags,
+ reg, pos, len, muxflags, &clklock);
+}
+
+/* helper to isolate a bit field from a register */
+static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len)
+{
+ uint32_t val;
+
+ val = in_be32(reg);
+ val >>= pos;
+ val &= (1 << len) - 1;
+ return val;
+}
+
+/* get the SPMF and translate it into the "sys pll" multiplier */
+static int get_spmf_mult(void)
+{
+ static int spmf_to_mult[] = {
+ 68, 1, 12, 16, 20, 24, 28, 32,
+ 36, 40, 44, 48, 52, 56, 60, 64,
+ };
+ int spmf;
+
+ spmf = get_bit_field(&clkregs->spmr, 24, 4);
+ return spmf_to_mult[spmf];
+}
+
+/*
+ * get the SYS_DIV value and translate it into a divide factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * divide ratio is fractional
+ */
+static int get_sys_div_x2(void)
+{
+ static int sysdiv_code_to_x2[] = {
+ 4, 5, 6, 7, 8, 9, 10, 14,
+ 12, 16, 18, 22, 20, 24, 26, 30,
+ 28, 32, 34, 38, 36, 40, 42, 46,
+ 44, 48, 50, 54, 52, 56, 58, 62,
+ 60, 64, 66,
+ };
+ int divcode;
+
+ divcode = get_bit_field(&clkregs->scfr2, 26, 6);
+ return sysdiv_code_to_x2[divcode];
+}
+
+/*
+ * get the CPMF value and translate it into a multiplier factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * multiplier ratio is fractional
+ */
+static int get_cpmf_mult_x2(void)
+{
+ static int cpmf_to_mult[] = {
+ 72, 2, 2, 3, 4, 5, 6, 7,
+ };
+ int cpmf;
+
+ cpmf = get_bit_field(&clkregs->spmr, 16, 4);
+ return cpmf_to_mult[cpmf];
+}
+
+/*
+ * some of the clock dividers do scale in a linear way, yet not all of
+ * their bit combinations are legal; use a divider table to get a
+ * resulting set of applicable divider values
+ */
+
+/* applies to the IPS_DIV, and PCI_DIV values */
+static struct clk_div_table divtab_2346[] = {
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .val = 6, .div = 6, },
+ { .div = 0, },
+};
+
+/* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
+static struct clk_div_table divtab_1234[] = {
+ { .val = 1, .div = 1, },
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .div = 0, },
+};
+
+static int get_freq_from_dt(char *propname)
+{
+ struct device_node *np;
+ const unsigned int *prop;
+ int val;
+
+ val = 0;
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
+ if (np) {
+ prop = of_get_property(np, propname, NULL);
+ if (prop)
+ val = *prop;
+ of_node_put(np);
+ }
+ return val;
+}
+
+static void mpc512x_clk_preset_data(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++)
+ clks[i] = ERR_PTR(-ENODEV);
+}
+
+/*
+ * - receives the "bus frequency" from the caller (that's the IPS clock
+ * rate, the historical source of clock information)
+ * - fetches the system PLL multiplier and divider values as well as the
+ * IPS divider value from hardware
+ * - determines the REF clock rate either from the XTAL/OSC spec (if
+ * there is a device tree node describing the oscillator) or from the
+ * IPS bus clock (supported for backwards compatibility, such that
+ * setups without XTAL/OSC specs keep working)
+ * - creates the "ref" clock item in the clock tree, such that
+ * subsequent code can create the remainder of the hierarchy (REF ->
+ * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
+ * values
+ */
+static void mpc512x_clk_setup_ref_clock(int bus_freq,
+ int *sys_mul, int *sys_div, int *ips_div)
+{
+ struct clk *osc_clk;
+ int calc_freq;
+
+ /* fetch mul/div factors from the hardware */
+ *sys_mul = get_spmf_mult();
+ *sys_mul *= 2; /* compensate for the fractional divider */
+ *sys_div = get_sys_div_x2();
+ *ips_div = get_bit_field(&clkregs->scfr1, 23, 3);
+
+ /* lookup the oscillator node */
+ osc_clk = clk_get(NULL, "osc");
+ if (osc_clk) {
+ /* descend REF directly from OSC, verify the IPS rate */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1);
+ calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]);
+ calc_freq *= *sys_mul;
+ calc_freq /= *sys_div;
+ calc_freq /= 2;
+ calc_freq /= *ips_div;
+ if (bus_freq && calc_freq != bus_freq)
+ pr_warn("calc rate %d != OF spec %d\n",
+ calc_freq, bus_freq);
+ } else {
+ /* calculate OSC rate and create REF from the freq value */
+ calc_freq = bus_freq; /* start with IPS */
+ calc_freq *= *ips_div; /* IPS -> CSB */
+ calc_freq *= 2; /* CSB -> SYS */
+ calc_freq *= *sys_div; /* SYS -> PLL out */
+ calc_freq /= *sys_mul; /* PLL out -> REF == OSC */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq);
+ }
+}
+
+/*
+ * helper code for the MCLK subtree setup
+ *
+ * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
+ * suggests that all instances of the "PSC clock generation" are equal,
+ * and that one might re-use the PSC setup for MSCAN clock generation
+ * (section 5.2.5) as well, at least the logic if not the data for
+ * description
+ *
+ * the details (starting at page 5-20) show differences in the specific
+ * inputs of the first mux stage ("can clk in", "spdif tx"), and the
+ * factual non-availability of the second mux stage (it's present yet
+ * only one input is valid)
+ *
+ * the MSCAN clock related registers (starting at page 5-35) all
+ * reference "spdif clk" at the first mux stage and don't mention any
+ * "can clk" at all, which somehow is unexpected
+ *
+ * TODO re-check the document, and clarify whether the RM is correct in
+ * the overview or in the details, and whether the difference is a
+ * clipboard induced error or results from chip revisions
+ *
+ * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
+ * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
+ * first a doc update is required which better reflects reality in the
+ * SoC before the implementation should follow while no questions remain
+ */
+
+/*
+ * note that this declaration raises a checkpatch warning, but
+ * it's the very data type which <linux/clk-provider.h> expects,
+ * making this declaration pass checkpatch will break compilation
+ */
+static const char *parent_names_mux0[] = {
+ "sys", "ref", "psc-mclk-in", "spdif-tx",
+};
+
+enum mclk_type {
+ MCLK_TYPE_PSC,
+ MCLK_TYPE_MSCAN,
+ MCLK_TYPE_SPDIF,
+};
+
+struct mclk_setup_data {
+ enum mclk_type type;
+ int comp_idx;
+ bool has_mclk1;
+ int bit_sccr1, bit_sccr2;
+ const char *name_mux0;
+ const char *name_en0;
+ const char *name_div0;
+ const char *parent_names_mux1[2];
+ const char *name_mux1;
+ const char *name_mclk;
+};
+
+#define MCLK_SETUP_DATA_PSC(id) { \
+ MCLK_TYPE_PSC, id, \
+ 0, 27 - id, -1, \
+ "psc" #id "-mux0", \
+ "psc" #id "-en0", \
+ "psc" #id "_mclk_div", \
+ { "psc" #id "_mclk_div", "dummy", }, \
+ "psc" #id "_mclk_out", \
+ "psc" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_MSCAN(id) { \
+ MCLK_TYPE_MSCAN, id, \
+ 0, -1, 25, \
+ "mscan" #id "-mux0", \
+ "mscan" #id "-en0", \
+ "mscan" #id "_mclk_div", \
+ { "mscan" #id "_mclk_div", "dummy", }, \
+ "mscan" #id "_mclk_out", \
+ "mscan" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_SPDIF { \
+ MCLK_TYPE_SPDIF, 0, \
+ 1, -1, 23, \
+ "spdif-mux0", \
+ "spdif-en0", \
+ "spdif_mclk_div", \
+ { "spdif_mclk_div", "spdif-rx", }, \
+ "spdif_mclk_out", \
+ "spdif_mclk", \
+}
+
+static struct mclk_setup_data mclk_psc_data[] = {
+ MCLK_SETUP_DATA_PSC(0),
+ MCLK_SETUP_DATA_PSC(1),
+ MCLK_SETUP_DATA_PSC(2),
+ MCLK_SETUP_DATA_PSC(3),
+ MCLK_SETUP_DATA_PSC(4),
+ MCLK_SETUP_DATA_PSC(5),
+ MCLK_SETUP_DATA_PSC(6),
+ MCLK_SETUP_DATA_PSC(7),
+ MCLK_SETUP_DATA_PSC(8),
+ MCLK_SETUP_DATA_PSC(9),
+ MCLK_SETUP_DATA_PSC(10),
+ MCLK_SETUP_DATA_PSC(11),
+};
+
+static struct mclk_setup_data mclk_mscan_data[] = {
+ MCLK_SETUP_DATA_MSCAN(0),
+ MCLK_SETUP_DATA_MSCAN(1),
+ MCLK_SETUP_DATA_MSCAN(2),
+ MCLK_SETUP_DATA_MSCAN(3),
+};
+
+static struct mclk_setup_data mclk_spdif_data[] = {
+ MCLK_SETUP_DATA_SPDIF,
+};
+
+/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
+static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
+{
+ size_t clks_idx_pub, clks_idx_int;
+ u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */
+ u32 __iomem *sccr_reg; /* system clock control register (enable) */
+ int sccr_bit;
+ int div;
+
+ /* derive a few parameters from the component type and index */
+ switch (entry->type) {
+ case MCLK_TYPE_PSC:
+ clks_idx_pub = MPC512x_CLK_PSC0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->psc_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_MSCAN:
+ clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->mscan_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_SPDIF:
+ clks_idx_pub = MPC512x_CLK_SPDIF_MCLK;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->spccr;
+ break;
+ default:
+ return;
+ }
+ if (entry->bit_sccr1 >= 0) {
+ sccr_reg = &clkregs->sccr1;
+ sccr_bit = entry->bit_sccr1;
+ } else if (entry->bit_sccr2 >= 0) {
+ sccr_reg = &clkregs->sccr2;
+ sccr_bit = entry->bit_sccr2;
+ } else {
+ sccr_reg = NULL;
+ }
+
+ /*
+ * this was grabbed from the PPC_CLOCK implementation, which
+ * enforced a specific MCLK divider while the clock was gated
+ * during setup (that's a documented hardware requirement)
+ *
+ * the PPC_CLOCK implementation might even have violated the
+ * "MCLK <= IPS" constraint, the fixed divider value of 1
+ * results in a divider of 2 and thus MCLK = SYS/2 which equals
+ * CSB which is greater than IPS; the serial port setup may have
+ * adjusted the divider which the clock setup might have left in
+ * an undesirable state
+ *
+ * initial setup is:
+ * - MCLK 0 from SYS
+ * - MCLK DIV such to not exceed the IPS clock
+ * - MCLK 0 enabled
+ * - MCLK 1 from MCLK DIV
+ */
+ div = clk_get_rate(clks[MPC512x_CLK_SYS]);
+ div /= clk_get_rate(clks[MPC512x_CLK_IPS]);
+ out_be32(mccr_reg, (0 << 16));
+ out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
+ out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
+
+ /*
+ * create the 'struct clk' items of the MCLK's clock subtree
+ *
+ * note that by design we always create all nodes and won't take
+ * shortcuts here, because
+ * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
+ * selectable inputs to the CFM while those who "actually use"
+ * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
+ * for their bitrate
+ * - in the absence of "aliases" for clocks we need to create
+ * individial 'struct clk' items for whatever might get
+ * referenced or looked up, even if several of those items are
+ * identical from the logical POV (their rate value)
+ * - for easier future maintenance and for better reflection of
+ * the SoC's documentation, it appears appropriate to generate
+ * clock items even for those muxers which actually are NOPs
+ * (those with two inputs of which one is reserved)
+ */
+ clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed(
+ entry->name_mux0,
+ &parent_names_mux0[0], ARRAY_SIZE(parent_names_mux0),
+ mccr_reg, 14, 2);
+ clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated(
+ entry->name_en0, entry->name_mux0,
+ mccr_reg, 16);
+ clks[clks_idx_int + MCLK_IDX_DIV0] = mpc512x_clk_divider(
+ entry->name_div0,
+ entry->name_en0, CLK_SET_RATE_GATE,
+ mccr_reg, 17, 15, 0);
+ if (entry->has_mclk1) {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_muxed(
+ entry->name_mux1,
+ &entry->parent_names_mux1[0],
+ ARRAY_SIZE(entry->parent_names_mux1),
+ mccr_reg, 7, 1);
+ } else {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_factor(
+ entry->name_mux1, entry->parent_names_mux1[0],
+ 1, 1);
+ }
+ if (sccr_reg) {
+ clks[clks_idx_pub] = mpc512x_clk_gated(
+ entry->name_mclk,
+ entry->name_mux1, sccr_reg, sccr_bit);
+ } else {
+ clks[clks_idx_pub] = mpc512x_clk_factor(
+ entry->name_mclk,
+ entry->name_mux1, 1, 1);
+ }
+
+ /*
+ * without this "clock device" registration, "simple" lookups in
+ * the SPI master initialization and serial port setup will fail
+ *
+ * those drivers need to get adjusted to lookup their required
+ * clocks from OF specs, before this clkdev registration becomes
+ * obsolete
+ */
+ clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
+}
+
+static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
+{
+ while (count-- > 0)
+ mpc512x_clk_setup_mclk(table++);
+}
+
+static void mpc512x_clk_setup_clock_tree(int busfreq)
+{
+ int sys_mul, sys_div, ips_div;
+ int mul, div;
+ int freq;
+
+ /*
+ * TODO
+ * - consider whether to handle clocks which have both gates and
+ * dividers via intermediates or by means of composites
+ * - fractional dividers appear to not map well to composites
+ * since they can be seen as a fixed multiplier and an
+ * adjustable divider, while composites can only combine at
+ * most one of a mux, div, and gate each into one 'struct clk'
+ * item
+ * - PSC/MSCAN/SPDIF clock generation OTOH already is very
+ * specific and cannot get mapped to componsites (at least not
+ * a single one, maybe two of them, but see the comment about
+ * "intermediates are referenced from elsewhere, too")
+ * - trim the list of auto-enabled clocks after drivers acquire
+ * them correctly as needed
+ */
+
+ /* regardless of whether XTAL/OSC exists, have REF created */
+ mpc512x_clk_setup_ref_clock(busfreq, &sys_mul, &sys_div, &ips_div);
+
+ /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
+ clks[MPC512x_CLK_SYS] = mpc512x_clk_factor("sys", "ref",
+ sys_mul, sys_div);
+ clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2);
+ clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb",
+ &clkregs->scfr1, 23, 3,
+ divtab_2346);
+
+ /* now setup anything below SYS and CSB and IPS */
+ clks[MPC512x_CLK_DDR_UG] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2);
+ clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0,
+ &clkregs->scfr2, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+ clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_DIU_UG] = mpc512x_clk_divider("diu-ug", "diu-x4", 0,
+ &clkregs->scfr1, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+
+ /*
+ * the "power architecture PLL" was setup from data which was
+ * sampled from the reset config word, at this point in time the
+ * configuration can be considered fixed and read only (i.e. no
+ * longer adjustable, or no longer in need of adjustment), which
+ * is why we don't register a PLL here but assume fixed factors
+ */
+ mul = get_cpmf_mult_x2();
+ div = 2; /* compensate for the fractional factor */
+ clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div);
+
+ clks[MPC512x_CLK_MBX_BUS_UG] = mpc512x_clk_factor("mbx-bus-ug", "csb",
+ 1, 2);
+ clks[MPC512x_CLK_MBX_UG] = mpc512x_clk_divtable("mbx-ug", "mbx-bus-ug",
+ &clkregs->scfr1, 14, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_MBX_3D_UG] = mpc512x_clk_factor("mbx-3d-ug", "mbx-ug",
+ 1, 1);
+ clks[MPC512x_CLK_PCI_UG] = mpc512x_clk_divtable("pci-ug", "csb",
+ &clkregs->scfr1, 20, 3,
+ divtab_2346);
+ clks[MPC512x_CLK_NFC_UG] = mpc512x_clk_divtable("nfc-ug", "ips",
+ &clkregs->scfr1, 8, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips",
+ &clkregs->scfr1, 11, 3,
+ divtab_1234);
+
+ clks[MPC512x_CLK_LPC] = mpc512x_clk_gated("lpc", "lpc-ug",
+ &clkregs->sccr1, 30);
+ clks[MPC512x_CLK_NFC] = mpc512x_clk_gated("nfc", "nfc-ug",
+ &clkregs->sccr1, 29);
+ clks[MPC512x_CLK_PATA] = mpc512x_clk_gated("pata", "ips",
+ &clkregs->sccr1, 28);
+ mpc512x_clk_setup_mclks(mclk_psc_data, ARRAY_SIZE(mclk_psc_data));
+ clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips",
+ &clkregs->sccr1, 15);
+ clks[MPC512x_CLK_SATA] = mpc512x_clk_gated("sata", "ips",
+ &clkregs->sccr1, 14);
+ clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips",
+ &clkregs->sccr1, 13);
+ clks[MPC512x_CLK_PCI] = mpc512x_clk_gated("pci", "pci-ug",
+ &clkregs->sccr1, 11);
+ clks[MPC512x_CLK_DDR] = mpc512x_clk_gated("ddr", "ddr-ug",
+ &clkregs->sccr1, 10);
+
+ clks[MPC512x_CLK_DIU] = mpc512x_clk_gated("diu", "diu-ug",
+ &clkregs->sccr2, 31);
+ clks[MPC512x_CLK_AXE] = mpc512x_clk_gated("axe", "csb",
+ &clkregs->sccr2, 30);
+ clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips",
+ &clkregs->sccr2, 29);
+ clks[MPC512x_CLK_USB1] = mpc512x_clk_gated("usb1", "csb",
+ &clkregs->sccr2, 28);
+ clks[MPC512x_CLK_USB2] = mpc512x_clk_gated("usb2", "csb",
+ &clkregs->sccr2, 27);
+ clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips",
+ &clkregs->sccr2, 26);
+ mpc512x_clk_setup_mclks(mclk_mscan_data, ARRAY_SIZE(mclk_mscan_data));
+ clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug",
+ &clkregs->sccr2, 24);
+ mpc512x_clk_setup_mclks(mclk_spdif_data, ARRAY_SIZE(mclk_spdif_data));
+ clks[MPC512x_CLK_MBX_BUS] = mpc512x_clk_gated("mbx-bus", "mbx-bus-ug",
+ &clkregs->sccr2, 22);
+ clks[MPC512x_CLK_MBX] = mpc512x_clk_gated("mbx", "mbx-ug",
+ &clkregs->sccr2, 21);
+ clks[MPC512x_CLK_MBX_3D] = mpc512x_clk_gated("mbx-3d", "mbx-3d-ug",
+ &clkregs->sccr2, 20);
+ clks[MPC512x_CLK_IIM] = mpc512x_clk_gated("iim", "csb",
+ &clkregs->sccr2, 19);
+ clks[MPC512x_CLK_VIU] = mpc512x_clk_gated("viu", "csb",
+ &clkregs->sccr2, 18);
+ clks[MPC512x_CLK_SDHC_2] = mpc512x_clk_gated("sdhc-2", "sdhc-ug",
+ &clkregs->sccr2, 17);
+
+ /*
+ * externally provided clocks (when implemented in hardware,
+ * device tree may specify values which otherwise were unknown)
+ */
+ freq = get_freq_from_dt("psc_mclk_in");
+ if (!freq)
+ freq = 25000000;
+ clks[MPC512x_CLK_PSC_MCLK_IN] = mpc512x_clk_fixed("psc_mclk_in", freq);
+ freq = get_freq_from_dt("spdif_tx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_tx_in", freq);
+ freq = get_freq_from_dt("spdif_rx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_rx_in", freq);
+
+ /* fixed frequency for AC97, always 24.567MHz */
+ clks[MPC512x_CLK_AC97] = mpc512x_clk_fixed("ac97", 24567000);
+
+ pr_debug("clock tree setup complete\n");
+ freq = clk_get_rate(clks[MPC512x_CLK_E300]);
+ pr_debug("derived PPC freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_IPS]);
+ pr_debug("derived IPS freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_LPC]);
+ pr_debug("derived LPC freq [%d]\n", freq);
+
+ /* enable some of the clocks here unconditionally because ... */
+ pr_debug("automatically enabling some clocks\n");
+ /* some are essential yet never get claimed by any driver */
+ clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
+ clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */
+ clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
+ clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
+ /* some are required yet no dependencies were declared */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
+ /* some are not yet acquired by their respective drivers */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
+ clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
+ clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
+ clk_prepare_enable(clks[MPC512x_CLK_I2C]);
+ /*
+ * some have their individual clock subtree with separate clock
+ * items and their individual enable counters, yet share a
+ * common gate (refer to the same register location) while the
+ * common clock driver code is not aware of the fact and the
+ * platform's code doesn't provide specific support either
+ *
+ * what might happen is that e.g. enabling two MSCAN clock items
+ * and disabling one of them will disable the common gate and
+ * thus break the other MSCAN clock as well
+ */
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN0_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN1_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN2_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN3_MCLK]);
+}
+
+/*
+ * registers the set of public clocks (those listed in the dt-bindings/
+ * header file) for OF lookups, keeps the intermediates private to us
+ */
+static void mpc5121_clk_register_of_provider(struct device_node *np)
+{
+ clk_data.clks = clks;
+ clk_data.clk_num = MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_SIZE() */
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+int __init mpc5121_clk_init(void)
+{
+ struct device_node *clk_np;
+ int busfreq;
+
+ /* map the clock control registers */
+ clk_np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ if (!clk_np)
+ return -ENODEV;
+ clkregs = of_iomap(clk_np, 0);
+ WARN_ON(!clkregs);
+
+ /* invalidate all not yet registered clock slots */
+ mpc512x_clk_preset_data();
+
+ /*
+ * have the device tree scanned for "fixed-clock" nodes (which
+ * includes the oscillator node if the board's DT provides one)
+ */
+ of_clk_init(NULL);
+
+ /*
+ * add a dummy clock for those situations where a clock spec is
+ * required yet no real clock is involved
+ */
+ clks[MPC512x_CLK_DUMMY] = mpc512x_clk_fixed("dummy", 0);
+
+ /*
+ * have all the real nodes in the clock tree populated from REF
+ * down to all leaves, either starting from the OSC node or from
+ * a REF root that was created from the IPS bus clock input
+ */
+ busfreq = get_freq_from_dt("bus-frequency");
+ mpc512x_clk_setup_clock_tree(busfreq);
+
+ /* register as an OF clock provider */
+ mpc5121_clk_register_of_provider(clk_np);
+
+ return 0;
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c4f7799..7f8fc64 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -497,6 +497,20 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
* for improved portability across platforms
*/
+#if IS_ENABLED(CONFIG_PPC)
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return ioread32be(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ iowrite32be(val, reg);
+}
+
+#else /* platform dependent I/O accessors */
+
static inline u32 clk_readl(u32 __iomem *reg)
{
return readl(reg);
@@ -507,5 +521,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
writel(val, reg);
}
+#endif /* platform dependent I/O accessors */
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 10/24] dts: mpc512x: add clock specs for client lookups
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
this addresses the client side of device tree based clock lookups:
add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu,
viu, mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the
shared mpc5121.dtsi include
these specs map 'clock-names' encoded in drivers to their respective
'struct clk' items in the platform's clock driver; some drivers
still need to learn how to lookup OF clocks, other drivers will
transparently probe successfully on MPC512x as well (sdhc)
few 'clock-names' (nfc, viu) use strings that are encoded in their
respective drivers to keep up compatibility, an alternative approach
would be to register clkdev items in the platform's clock driver for
the migration period
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 8f4cba0..983da9c 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -51,6 +51,10 @@
compatible = "fsl,mpc5121-mbx";
reg = <0x20000000 0x4000>;
interrupts = <66 0x8>;
+ clocks = <&clks MPC512x_CLK_MBX_BUS>,
+ <&clks MPC512x_CLK_MBX_3D>,
+ <&clks MPC512x_CLK_MBX>;
+ clock-names = "mbx-bus", "mbx-3d", "mbx";
};
sram@30000000 {
@@ -64,6 +68,8 @@
interrupts = <6 8>;
#address-cells = <1>;
#size-cells = <1>;
+ clocks = <&clks MPC512x_CLK_NFC>;
+ clock-names = "nfc_clk"; /* backwards compat */
};
localbus@80000020 {
@@ -153,12 +159,22 @@
compatible = "fsl,mpc5121-mscan";
reg = <0x1300 0x80>;
interrupts = <12 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN0_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can@1380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x1380 0x80>;
interrupts = <13 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN1_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
sdhc@1500 {
@@ -167,6 +183,9 @@
interrupts = <8 0x8>;
dmas = <&dma0 30>;
dma-names = "rx-tx";
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SDHC>;
+ clock-names = "ipg", "per";
};
i2c@1700 {
@@ -175,6 +194,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c@1720 {
@@ -183,6 +204,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c@1740 {
@@ -191,6 +214,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2ccontrol@1760 {
@@ -202,30 +227,46 @@
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
+ clocks = <&clks MPC512x_CLK_AXE>;
+ clock-names = "per";
};
display@2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
+ clocks = <&clks MPC512x_CLK_DIU>;
+ clock-names = "per";
};
can@2300 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2300 0x80>;
interrupts = <90 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN2_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can@2380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2380 0x80>;
interrupts = <91 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN3_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
viu@2400 {
compatible = "fsl,mpc5121-viu";
reg = <0x2400 0x400>;
interrupts = <67 0x8>;
+ clocks = <&clks MPC512x_CLK_VIU>;
+ clock-names = "viu_clk"; /* backwards compat */
};
mdio@2800 {
@@ -233,6 +274,8 @@
reg = <0x2800 0x800>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
eth0: ethernet@2800 {
@@ -241,6 +284,8 @@
reg = <0x2800 0x800>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
/* USB1 using external ULPI PHY */
@@ -252,6 +297,8 @@
interrupts = <43 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
+ clocks = <&clks MPC512x_CLK_USB1>;
+ clock-names = "per";
};
/* USB0 using internal UTMI PHY */
@@ -263,6 +310,8 @@
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
+ clocks = <&clks MPC512x_CLK_USB2>;
+ clock-names = "per";
};
/* IO control */
@@ -281,6 +330,8 @@
compatible = "fsl,mpc5121-pata";
reg = <0x10200 0x100>;
interrupts = <5 0x8>;
+ clocks = <&clks MPC512x_CLK_PATA>;
+ clock-names = "per";
};
/* 512x PSCs are not 52xx PSC compatible */
@@ -292,6 +343,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC0_MCLK>;
+ clock-names = "mclk";
};
/* PSC1 */
@@ -301,6 +354,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC1_MCLK>;
+ clock-names = "mclk";
};
/* PSC2 */
@@ -310,6 +365,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC2_MCLK>;
+ clock-names = "mclk";
};
/* PSC3 */
@@ -319,6 +376,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC3_MCLK>;
+ clock-names = "mclk";
};
/* PSC4 */
@@ -328,6 +387,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC4_MCLK>;
+ clock-names = "mclk";
};
/* PSC5 */
@@ -337,6 +398,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC5_MCLK>;
+ clock-names = "mclk";
};
/* PSC6 */
@@ -346,6 +409,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC6_MCLK>;
+ clock-names = "mclk";
};
/* PSC7 */
@@ -355,6 +420,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC7_MCLK>;
+ clock-names = "mclk";
};
/* PSC8 */
@@ -364,6 +431,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC8_MCLK>;
+ clock-names = "mclk";
};
/* PSC9 */
@@ -373,6 +442,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC9_MCLK>;
+ clock-names = "mclk";
};
/* PSC10 */
@@ -382,6 +453,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC10_MCLK>;
+ clock-names = "mclk";
};
/* PSC11 */
@@ -391,12 +464,16 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC11_MCLK>;
+ clock-names = "mclk";
};
pscfifo@11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
+ clocks = <&clks MPC512x_CLK_PSC_FIFO>;
+ clock-names = "per";
};
dma0: dma@14000 {
@@ -414,6 +491,8 @@
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
+ clocks = <&clks MPC512x_CLK_PCI>;
+ clock-names = "per";
reg = <0x80008500 0x100 /* internal registers */
0x80008300 0x8>; /* config space access registers */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 10/24] dts: mpc512x: add clock specs for client lookups
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this addresses the client side of device tree based clock lookups:
add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu,
viu, mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the
shared mpc5121.dtsi include
these specs map 'clock-names' encoded in drivers to their respective
'struct clk' items in the platform's clock driver; some drivers
still need to learn how to lookup OF clocks, other drivers will
transparently probe successfully on MPC512x as well (sdhc)
few 'clock-names' (nfc, viu) use strings that are encoded in their
respective drivers to keep up compatibility, an alternative approach
would be to register clkdev items in the platform's clock driver for
the migration period
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 8f4cba0..983da9c 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -51,6 +51,10 @@
compatible = "fsl,mpc5121-mbx";
reg = <0x20000000 0x4000>;
interrupts = <66 0x8>;
+ clocks = <&clks MPC512x_CLK_MBX_BUS>,
+ <&clks MPC512x_CLK_MBX_3D>,
+ <&clks MPC512x_CLK_MBX>;
+ clock-names = "mbx-bus", "mbx-3d", "mbx";
};
sram@30000000 {
@@ -64,6 +68,8 @@
interrupts = <6 8>;
#address-cells = <1>;
#size-cells = <1>;
+ clocks = <&clks MPC512x_CLK_NFC>;
+ clock-names = "nfc_clk"; /* backwards compat */
};
localbus@80000020 {
@@ -153,12 +159,22 @@
compatible = "fsl,mpc5121-mscan";
reg = <0x1300 0x80>;
interrupts = <12 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN0_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can@1380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x1380 0x80>;
interrupts = <13 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN1_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
sdhc@1500 {
@@ -167,6 +183,9 @@
interrupts = <8 0x8>;
dmas = <&dma0 30>;
dma-names = "rx-tx";
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SDHC>;
+ clock-names = "ipg", "per";
};
i2c@1700 {
@@ -175,6 +194,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c@1720 {
@@ -183,6 +204,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c@1740 {
@@ -191,6 +214,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2ccontrol@1760 {
@@ -202,30 +227,46 @@
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
+ clocks = <&clks MPC512x_CLK_AXE>;
+ clock-names = "per";
};
display@2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
+ clocks = <&clks MPC512x_CLK_DIU>;
+ clock-names = "per";
};
can@2300 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2300 0x80>;
interrupts = <90 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN2_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can@2380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2380 0x80>;
interrupts = <91 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN3_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
viu@2400 {
compatible = "fsl,mpc5121-viu";
reg = <0x2400 0x400>;
interrupts = <67 0x8>;
+ clocks = <&clks MPC512x_CLK_VIU>;
+ clock-names = "viu_clk"; /* backwards compat */
};
mdio@2800 {
@@ -233,6 +274,8 @@
reg = <0x2800 0x800>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
eth0: ethernet@2800 {
@@ -241,6 +284,8 @@
reg = <0x2800 0x800>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
/* USB1 using external ULPI PHY */
@@ -252,6 +297,8 @@
interrupts = <43 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
+ clocks = <&clks MPC512x_CLK_USB1>;
+ clock-names = "per";
};
/* USB0 using internal UTMI PHY */
@@ -263,6 +310,8 @@
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
+ clocks = <&clks MPC512x_CLK_USB2>;
+ clock-names = "per";
};
/* IO control */
@@ -281,6 +330,8 @@
compatible = "fsl,mpc5121-pata";
reg = <0x10200 0x100>;
interrupts = <5 0x8>;
+ clocks = <&clks MPC512x_CLK_PATA>;
+ clock-names = "per";
};
/* 512x PSCs are not 52xx PSC compatible */
@@ -292,6 +343,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC0_MCLK>;
+ clock-names = "mclk";
};
/* PSC1 */
@@ -301,6 +354,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC1_MCLK>;
+ clock-names = "mclk";
};
/* PSC2 */
@@ -310,6 +365,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC2_MCLK>;
+ clock-names = "mclk";
};
/* PSC3 */
@@ -319,6 +376,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC3_MCLK>;
+ clock-names = "mclk";
};
/* PSC4 */
@@ -328,6 +387,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC4_MCLK>;
+ clock-names = "mclk";
};
/* PSC5 */
@@ -337,6 +398,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC5_MCLK>;
+ clock-names = "mclk";
};
/* PSC6 */
@@ -346,6 +409,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC6_MCLK>;
+ clock-names = "mclk";
};
/* PSC7 */
@@ -355,6 +420,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC7_MCLK>;
+ clock-names = "mclk";
};
/* PSC8 */
@@ -364,6 +431,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC8_MCLK>;
+ clock-names = "mclk";
};
/* PSC9 */
@@ -373,6 +442,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC9_MCLK>;
+ clock-names = "mclk";
};
/* PSC10 */
@@ -382,6 +453,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC10_MCLK>;
+ clock-names = "mclk";
};
/* PSC11 */
@@ -391,12 +464,16 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC11_MCLK>;
+ clock-names = "mclk";
};
pscfifo@11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
+ clocks = <&clks MPC512x_CLK_PSC_FIFO>;
+ clock-names = "per";
};
dma0: dma@14000 {
@@ -414,6 +491,8 @@
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
+ clocks = <&clks MPC512x_CLK_PCI>;
+ clock-names = "per";
reg = <0x80008500 0x100 /* internal registers */
0x80008300 0x8>; /* config space access registers */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 10/24] dts: mpc512x: add clock specs for client lookups
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
this addresses the client side of device tree based clock lookups:
add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu,
viu, mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the
shared mpc5121.dtsi include
these specs map 'clock-names' encoded in drivers to their respective
'struct clk' items in the platform's clock driver; some drivers
still need to learn how to lookup OF clocks, other drivers will
transparently probe successfully on MPC512x as well (sdhc)
few 'clock-names' (nfc, viu) use strings that are encoded in their
respective drivers to keep up compatibility, an alternative approach
would be to register clkdev items in the platform's clock driver for
the migration period
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 8f4cba0..983da9c 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -51,6 +51,10 @@
compatible = "fsl,mpc5121-mbx";
reg = <0x20000000 0x4000>;
interrupts = <66 0x8>;
+ clocks = <&clks MPC512x_CLK_MBX_BUS>,
+ <&clks MPC512x_CLK_MBX_3D>,
+ <&clks MPC512x_CLK_MBX>;
+ clock-names = "mbx-bus", "mbx-3d", "mbx";
};
sram at 30000000 {
@@ -64,6 +68,8 @@
interrupts = <6 8>;
#address-cells = <1>;
#size-cells = <1>;
+ clocks = <&clks MPC512x_CLK_NFC>;
+ clock-names = "nfc_clk"; /* backwards compat */
};
localbus at 80000020 {
@@ -153,12 +159,22 @@
compatible = "fsl,mpc5121-mscan";
reg = <0x1300 0x80>;
interrupts = <12 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN0_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can at 1380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x1380 0x80>;
interrupts = <13 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN1_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
sdhc at 1500 {
@@ -167,6 +183,9 @@
interrupts = <8 0x8>;
dmas = <&dma0 30>;
dma-names = "rx-tx";
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SDHC>;
+ clock-names = "ipg", "per";
};
i2c at 1700 {
@@ -175,6 +194,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c at 1720 {
@@ -183,6 +204,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c at 1740 {
@@ -191,6 +214,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2ccontrol at 1760 {
@@ -202,30 +227,46 @@
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
+ clocks = <&clks MPC512x_CLK_AXE>;
+ clock-names = "per";
};
display at 2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
+ clocks = <&clks MPC512x_CLK_DIU>;
+ clock-names = "per";
};
can at 2300 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2300 0x80>;
interrupts = <90 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN2_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can at 2380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2380 0x80>;
interrupts = <91 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN3_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
viu at 2400 {
compatible = "fsl,mpc5121-viu";
reg = <0x2400 0x400>;
interrupts = <67 0x8>;
+ clocks = <&clks MPC512x_CLK_VIU>;
+ clock-names = "viu_clk"; /* backwards compat */
};
mdio at 2800 {
@@ -233,6 +274,8 @@
reg = <0x2800 0x800>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
eth0: ethernet at 2800 {
@@ -241,6 +284,8 @@
reg = <0x2800 0x800>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
/* USB1 using external ULPI PHY */
@@ -252,6 +297,8 @@
interrupts = <43 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
+ clocks = <&clks MPC512x_CLK_USB1>;
+ clock-names = "per";
};
/* USB0 using internal UTMI PHY */
@@ -263,6 +310,8 @@
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
+ clocks = <&clks MPC512x_CLK_USB2>;
+ clock-names = "per";
};
/* IO control */
@@ -281,6 +330,8 @@
compatible = "fsl,mpc5121-pata";
reg = <0x10200 0x100>;
interrupts = <5 0x8>;
+ clocks = <&clks MPC512x_CLK_PATA>;
+ clock-names = "per";
};
/* 512x PSCs are not 52xx PSC compatible */
@@ -292,6 +343,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC0_MCLK>;
+ clock-names = "mclk";
};
/* PSC1 */
@@ -301,6 +354,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC1_MCLK>;
+ clock-names = "mclk";
};
/* PSC2 */
@@ -310,6 +365,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC2_MCLK>;
+ clock-names = "mclk";
};
/* PSC3 */
@@ -319,6 +376,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC3_MCLK>;
+ clock-names = "mclk";
};
/* PSC4 */
@@ -328,6 +387,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC4_MCLK>;
+ clock-names = "mclk";
};
/* PSC5 */
@@ -337,6 +398,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC5_MCLK>;
+ clock-names = "mclk";
};
/* PSC6 */
@@ -346,6 +409,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC6_MCLK>;
+ clock-names = "mclk";
};
/* PSC7 */
@@ -355,6 +420,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC7_MCLK>;
+ clock-names = "mclk";
};
/* PSC8 */
@@ -364,6 +431,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC8_MCLK>;
+ clock-names = "mclk";
};
/* PSC9 */
@@ -373,6 +442,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC9_MCLK>;
+ clock-names = "mclk";
};
/* PSC10 */
@@ -382,6 +453,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC10_MCLK>;
+ clock-names = "mclk";
};
/* PSC11 */
@@ -391,12 +464,16 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC11_MCLK>;
+ clock-names = "mclk";
};
pscfifo at 11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
+ clocks = <&clks MPC512x_CLK_PSC_FIFO>;
+ clock-names = "per";
};
dma0: dma at 14000 {
@@ -414,6 +491,8 @@
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
+ clocks = <&clks MPC512x_CLK_PCI>;
+ clock-names = "per";
reg = <0x80008500 0x100 /* internal registers */
0x80008300 0x8>; /* config space access registers */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 11/24] net: can: mscan: add a comment on reg to idx mapping
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
add a comment about the magic of deriving an MSCAN component index
from the peripheral's physical address / register offset
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
drivers/net/can/mscan/mpc5xxx_can.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index 5b0ee8e..bc422ba 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -148,7 +148,10 @@ static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
goto exit_put;
}
- /* Determine the MSCAN device index from the physical address */
+ /* Determine the MSCAN device index from the peripheral's
+ * physical address. Register address offsets against the
+ * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
+ */
pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
BUG_ON(!pval || plen < sizeof(*pval));
clockidx = (*pval & 0x80) ? 1 : 0;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 11/24] net: can: mscan: add a comment on reg to idx mapping
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
add a comment about the magic of deriving an MSCAN component index
from the peripheral's physical address / register offset
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index 5b0ee8e..bc422ba 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -148,7 +148,10 @@ static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
goto exit_put;
}
- /* Determine the MSCAN device index from the physical address */
+ /* Determine the MSCAN device index from the peripheral's
+ * physical address. Register address offsets against the
+ * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
+ */
pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
BUG_ON(!pval || plen < sizeof(*pval));
clockidx = (*pval & 0x80) ? 1 : 0;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 11/24] net: can: mscan: add a comment on reg to idx mapping
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
add a comment about the magic of deriving an MSCAN component index
from the peripheral's physical address / register offset
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index 5b0ee8e..bc422ba 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -148,7 +148,10 @@ static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
goto exit_put;
}
- /* Determine the MSCAN device index from the physical address */
+ /* Determine the MSCAN device index from the peripheral's
+ * physical address. Register address offsets against the
+ * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
+ */
pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
BUG_ON(!pval || plen < sizeof(*pval));
clockidx = (*pval & 0x80) ? 1 : 0;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 12/24] net: can: mscan: make mpc512x code use common clock
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
extend the mscan(4) driver with alternative support for the COMMON_CLK
approach which is an option in the MPC512x platform, keep the existing
clock support implementation in place since the driver is shared with
other MPC5xxx SoCs which don't have common clock support
one byproduct of this change is that the CAN driver no longer needs to
access the SoC's clock control registers, which shall be the domain of
the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
drivers/net/can/mscan/mpc5xxx_can.c | 139 +++++++++++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index bc422ba..dd26ab6 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -108,6 +108,143 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
#endif /* CONFIG_PPC_MPC52xx */
#ifdef CONFIG_PPC_MPC512x
+
+#if IS_ENABLED(CONFIG_COMMON_CLK)
+
+static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
+ const char *clock_source, int *mscan_clksrc)
+{
+ struct device_node *np;
+ u32 clockdiv;
+ enum {
+ CLK_FROM_AUTO,
+ CLK_FROM_IPS,
+ CLK_FROM_SYS,
+ CLK_FROM_REF,
+ } clk_from;
+ struct clk *clk_in, *clk_can;
+ unsigned long freq_calc;
+
+ /* the caller passed in the clock source spec that was read from
+ * the device tree, get the optional clock divider as well
+ */
+ np = ofdev->dev.of_node;
+ clockdiv = 1;
+ of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
+ dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
+ clock_source ? clock_source : "<NULL>", clockdiv);
+
+ /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
+ * get set, and the 'ips' clock is the input to the MSCAN
+ * component
+ *
+ * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
+ * bit needs to get cleared, an optional clock-divider may have
+ * been specified (the default value is 1), the appropriate
+ * MSCAN related MCLK is the input to the MSCAN component
+ *
+ * in the absence of a clock-source spec, first an optimal clock
+ * gets determined based on the 'sys' clock, if that fails the
+ * 'ref' clock is used
+ */
+ clk_from = CLK_FROM_AUTO;
+ if (clock_source) {
+ /* interpret the device tree's spec for the clock source */
+ if (!strcmp(clock_source, "ip"))
+ clk_from = CLK_FROM_IPS;
+ else if (!strcmp(clock_source, "sys"))
+ clk_from = CLK_FROM_SYS;
+ else if (!strcmp(clock_source, "ref"))
+ clk_from = CLK_FROM_REF;
+ else
+ goto err_invalid;
+ dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, try the 'sys' clock; round to the
+ * next MHz and see if we can get a multiple of 16MHz
+ */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc += 499999;
+ freq_calc /= 1000000;
+ freq_calc *= 1000000;
+ if ((freq_calc % 16000000) == 0) {
+ clk_from = CLK_FROM_SYS;
+ clockdiv = freq_calc / 16000000;
+ dev_dbg(&ofdev->dev,
+ "clk fit, sys[%lu] div[%d] freq[%lu]\n",
+ freq_calc, clockdiv, freq_calc / clockdiv);
+ }
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, use the 'ref' clock */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_from = CLK_FROM_REF;
+ freq_calc = clk_get_rate(clk_in);
+ dev_dbg(&ofdev->dev,
+ "clk fit, ref[%lu] (no div) freq[%lu]\n",
+ freq_calc, freq_calc);
+ }
+
+ /* select IPS or MCLK as the MSCAN input (returned to the caller),
+ * setup the MCLK mux source and rate if applicable, apply the
+ * optionally specified or derived above divider, and determine
+ * the actual resulting clock rate to return to the caller
+ */
+ switch (clk_from) {
+ case CLK_FROM_IPS:
+ clk_can = clk_get(&ofdev->dev, "ips");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_IPS;
+ dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ case CLK_FROM_SYS:
+ case CLK_FROM_REF:
+ clk_can = clk_get(&ofdev->dev, "mclk");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ if (clk_from == CLK_FROM_SYS)
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (clk_from == CLK_FROM_REF)
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_set_parent(clk_can, clk_in);
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc /= clockdiv;
+ clk_set_rate(clk_can, freq_calc);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_BUS;
+ dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ default:
+ goto err_invalid;
+ }
+
+ return freq_calc;
+
+err_invalid:
+ dev_err(&ofdev->dev, "invalid clock source specification\n");
+ return 0;
+
+err_notavail:
+ dev_err(&ofdev->dev, "cannot acquire or setup clock source\n");
+ return 0;
+}
+#else /* COMMON_CLK */
struct mpc512x_clockctl {
u32 spmr; /* System PLL Mode Reg */
u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
@@ -238,6 +375,8 @@ exit_put:
of_node_put(np_clock);
return freq;
}
+#endif /* COMMON_CLK */
+
#else /* !CONFIG_PPC_MPC512x */
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_name, int *mscan_clksrc)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 12/24] net: can: mscan: make mpc512x code use common clock
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
extend the mscan(4) driver with alternative support for the COMMON_CLK
approach which is an option in the MPC512x platform, keep the existing
clock support implementation in place since the driver is shared with
other MPC5xxx SoCs which don't have common clock support
one byproduct of this change is that the CAN driver no longer needs to
access the SoC's clock control registers, which shall be the domain of
the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 139 +++++++++++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index bc422ba..dd26ab6 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -108,6 +108,143 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
#endif /* CONFIG_PPC_MPC52xx */
#ifdef CONFIG_PPC_MPC512x
+
+#if IS_ENABLED(CONFIG_COMMON_CLK)
+
+static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
+ const char *clock_source, int *mscan_clksrc)
+{
+ struct device_node *np;
+ u32 clockdiv;
+ enum {
+ CLK_FROM_AUTO,
+ CLK_FROM_IPS,
+ CLK_FROM_SYS,
+ CLK_FROM_REF,
+ } clk_from;
+ struct clk *clk_in, *clk_can;
+ unsigned long freq_calc;
+
+ /* the caller passed in the clock source spec that was read from
+ * the device tree, get the optional clock divider as well
+ */
+ np = ofdev->dev.of_node;
+ clockdiv = 1;
+ of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
+ dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
+ clock_source ? clock_source : "<NULL>", clockdiv);
+
+ /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
+ * get set, and the 'ips' clock is the input to the MSCAN
+ * component
+ *
+ * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
+ * bit needs to get cleared, an optional clock-divider may have
+ * been specified (the default value is 1), the appropriate
+ * MSCAN related MCLK is the input to the MSCAN component
+ *
+ * in the absence of a clock-source spec, first an optimal clock
+ * gets determined based on the 'sys' clock, if that fails the
+ * 'ref' clock is used
+ */
+ clk_from = CLK_FROM_AUTO;
+ if (clock_source) {
+ /* interpret the device tree's spec for the clock source */
+ if (!strcmp(clock_source, "ip"))
+ clk_from = CLK_FROM_IPS;
+ else if (!strcmp(clock_source, "sys"))
+ clk_from = CLK_FROM_SYS;
+ else if (!strcmp(clock_source, "ref"))
+ clk_from = CLK_FROM_REF;
+ else
+ goto err_invalid;
+ dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, try the 'sys' clock; round to the
+ * next MHz and see if we can get a multiple of 16MHz
+ */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc += 499999;
+ freq_calc /= 1000000;
+ freq_calc *= 1000000;
+ if ((freq_calc % 16000000) == 0) {
+ clk_from = CLK_FROM_SYS;
+ clockdiv = freq_calc / 16000000;
+ dev_dbg(&ofdev->dev,
+ "clk fit, sys[%lu] div[%d] freq[%lu]\n",
+ freq_calc, clockdiv, freq_calc / clockdiv);
+ }
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, use the 'ref' clock */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_from = CLK_FROM_REF;
+ freq_calc = clk_get_rate(clk_in);
+ dev_dbg(&ofdev->dev,
+ "clk fit, ref[%lu] (no div) freq[%lu]\n",
+ freq_calc, freq_calc);
+ }
+
+ /* select IPS or MCLK as the MSCAN input (returned to the caller),
+ * setup the MCLK mux source and rate if applicable, apply the
+ * optionally specified or derived above divider, and determine
+ * the actual resulting clock rate to return to the caller
+ */
+ switch (clk_from) {
+ case CLK_FROM_IPS:
+ clk_can = clk_get(&ofdev->dev, "ips");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_IPS;
+ dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ case CLK_FROM_SYS:
+ case CLK_FROM_REF:
+ clk_can = clk_get(&ofdev->dev, "mclk");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ if (clk_from == CLK_FROM_SYS)
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (clk_from == CLK_FROM_REF)
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_set_parent(clk_can, clk_in);
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc /= clockdiv;
+ clk_set_rate(clk_can, freq_calc);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_BUS;
+ dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ default:
+ goto err_invalid;
+ }
+
+ return freq_calc;
+
+err_invalid:
+ dev_err(&ofdev->dev, "invalid clock source specification\n");
+ return 0;
+
+err_notavail:
+ dev_err(&ofdev->dev, "cannot acquire or setup clock source\n");
+ return 0;
+}
+#else /* COMMON_CLK */
struct mpc512x_clockctl {
u32 spmr; /* System PLL Mode Reg */
u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
@@ -238,6 +375,8 @@ exit_put:
of_node_put(np_clock);
return freq;
}
+#endif /* COMMON_CLK */
+
#else /* !CONFIG_PPC_MPC512x */
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_name, int *mscan_clksrc)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 12/24] net: can: mscan: make mpc512x code use common clock
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
extend the mscan(4) driver with alternative support for the COMMON_CLK
approach which is an option in the MPC512x platform, keep the existing
clock support implementation in place since the driver is shared with
other MPC5xxx SoCs which don't have common clock support
one byproduct of this change is that the CAN driver no longer needs to
access the SoC's clock control registers, which shall be the domain of
the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 139 +++++++++++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index bc422ba..dd26ab6 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -108,6 +108,143 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
#endif /* CONFIG_PPC_MPC52xx */
#ifdef CONFIG_PPC_MPC512x
+
+#if IS_ENABLED(CONFIG_COMMON_CLK)
+
+static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
+ const char *clock_source, int *mscan_clksrc)
+{
+ struct device_node *np;
+ u32 clockdiv;
+ enum {
+ CLK_FROM_AUTO,
+ CLK_FROM_IPS,
+ CLK_FROM_SYS,
+ CLK_FROM_REF,
+ } clk_from;
+ struct clk *clk_in, *clk_can;
+ unsigned long freq_calc;
+
+ /* the caller passed in the clock source spec that was read from
+ * the device tree, get the optional clock divider as well
+ */
+ np = ofdev->dev.of_node;
+ clockdiv = 1;
+ of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
+ dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
+ clock_source ? clock_source : "<NULL>", clockdiv);
+
+ /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
+ * get set, and the 'ips' clock is the input to the MSCAN
+ * component
+ *
+ * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
+ * bit needs to get cleared, an optional clock-divider may have
+ * been specified (the default value is 1), the appropriate
+ * MSCAN related MCLK is the input to the MSCAN component
+ *
+ * in the absence of a clock-source spec, first an optimal clock
+ * gets determined based on the 'sys' clock, if that fails the
+ * 'ref' clock is used
+ */
+ clk_from = CLK_FROM_AUTO;
+ if (clock_source) {
+ /* interpret the device tree's spec for the clock source */
+ if (!strcmp(clock_source, "ip"))
+ clk_from = CLK_FROM_IPS;
+ else if (!strcmp(clock_source, "sys"))
+ clk_from = CLK_FROM_SYS;
+ else if (!strcmp(clock_source, "ref"))
+ clk_from = CLK_FROM_REF;
+ else
+ goto err_invalid;
+ dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, try the 'sys' clock; round to the
+ * next MHz and see if we can get a multiple of 16MHz
+ */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc += 499999;
+ freq_calc /= 1000000;
+ freq_calc *= 1000000;
+ if ((freq_calc % 16000000) == 0) {
+ clk_from = CLK_FROM_SYS;
+ clockdiv = freq_calc / 16000000;
+ dev_dbg(&ofdev->dev,
+ "clk fit, sys[%lu] div[%d] freq[%lu]\n",
+ freq_calc, clockdiv, freq_calc / clockdiv);
+ }
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, use the 'ref' clock */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_from = CLK_FROM_REF;
+ freq_calc = clk_get_rate(clk_in);
+ dev_dbg(&ofdev->dev,
+ "clk fit, ref[%lu] (no div) freq[%lu]\n",
+ freq_calc, freq_calc);
+ }
+
+ /* select IPS or MCLK as the MSCAN input (returned to the caller),
+ * setup the MCLK mux source and rate if applicable, apply the
+ * optionally specified or derived above divider, and determine
+ * the actual resulting clock rate to return to the caller
+ */
+ switch (clk_from) {
+ case CLK_FROM_IPS:
+ clk_can = clk_get(&ofdev->dev, "ips");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_IPS;
+ dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ case CLK_FROM_SYS:
+ case CLK_FROM_REF:
+ clk_can = clk_get(&ofdev->dev, "mclk");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ if (clk_from == CLK_FROM_SYS)
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (clk_from == CLK_FROM_REF)
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_set_parent(clk_can, clk_in);
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc /= clockdiv;
+ clk_set_rate(clk_can, freq_calc);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_BUS;
+ dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ default:
+ goto err_invalid;
+ }
+
+ return freq_calc;
+
+err_invalid:
+ dev_err(&ofdev->dev, "invalid clock source specification\n");
+ return 0;
+
+err_notavail:
+ dev_err(&ofdev->dev, "cannot acquire or setup clock source\n");
+ return 0;
+}
+#else /* COMMON_CLK */
struct mpc512x_clockctl {
u32 spmr; /* System PLL Mode Reg */
u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
@@ -238,6 +375,8 @@ exit_put:
of_node_put(np_clock);
return freq;
}
+#endif /* COMMON_CLK */
+
#else /* !CONFIG_PPC_MPC512x */
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_name, int *mscan_clksrc)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 13/24] spi: mpc512x: OF clock lookup, use the 'mclk' name
2013-07-15 18:47 ` Gerhard Sittig
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
after PSC related clock specifiers were added to the device tree,
the former 'psc%d_mclk' isn't needed any longer to lookup clock items
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/spi/spi-mpc512x-psc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 76b20ea..3e30e52 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -388,13 +388,11 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
struct clk *spiclk;
int ret = 0;
- char name[32];
u32 sicr;
u32 ccr;
u16 bclkdiv;
- sprintf(name, "psc%d_mclk", master->bus_num);
- spiclk = clk_get(&master->dev, name);
+ spiclk = clk_get(&master->dev, "mclk");
clk_prepare_enable(spiclk);
mps->mclk = clk_get_rate(spiclk);
clk_put(spiclk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 13/24] spi: mpc512x: OF clock lookup, use the 'mclk' name
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
after PSC related clock specifiers were added to the device tree,
the former 'psc%d_mclk' isn't needed any longer to lookup clock items
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/spi/spi-mpc512x-psc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 76b20ea..3e30e52 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -388,13 +388,11 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
struct clk *spiclk;
int ret = 0;
- char name[32];
u32 sicr;
u32 ccr;
u16 bclkdiv;
- sprintf(name, "psc%d_mclk", master->bus_num);
- spiclk = clk_get(&master->dev, name);
+ spiclk = clk_get(&master->dev, "mclk");
clk_prepare_enable(spiclk);
mps->mclk = clk_get_rate(spiclk);
clk_put(spiclk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 14/24] powerpc/mpc512x: improve DIU related clock setup
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 18:47 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
adapt the DIU clock initialization to the COMMON_CLK approach: device
tree based clock lookup, prepare and unprepare for clocks, work with
frequencies not dividers, call the appropriate clk_*() routines and
don't access CCM registers, remove the pre-enable workaround in the
platform's clock driver
the "best clock" determination now completely relies on the platform's
clock driver to pick a frequency close to what the caller requests, and
merely checks whether the desired frequency was met (is acceptable since
it meets the tolerance of the monitor) -- this approach shall succeed
upon first try in the usual case, will test a few less desirable yet
acceptable frequencies in edge cases, and will fallback to "best effort"
if none of the previously tried frequencies pass the test
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++++++++++++------------
2 files changed, 88 insertions(+), 78 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 218f55b..f31f895 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -705,7 +705,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index a82a41b..3381eea 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -12,6 +12,7 @@
* (at your option) any later version.
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/irq.h>
@@ -70,98 +71,108 @@ struct fsl_diu_shared_fb {
bool in_use;
};
-#define DIU_DIV_MASK 0x000000ff
+/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
void mpc512x_set_pixel_clock(unsigned int pixclock)
{
- unsigned long bestval, bestfreq, speed, busfreq;
- unsigned long minpixclock, maxpixclock, pixval;
- struct mpc512x_ccm __iomem *ccm;
struct device_node *np;
- u32 temp;
- long err;
- int i;
+ struct clk *clk_diu;
+ unsigned long epsilon, minpixclock, maxpixclock;
+ unsigned long offset, want, got, delta;
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ /* lookup and enable the DIU clock */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
if (!np) {
- pr_err("Can't find clock control module.\n");
+ pr_err("Could not find DIU device tree node.\n");
return;
}
-
- ccm = of_iomap(np, 0);
+ clk_diu = of_clk_get_by_name(np, "per");
of_node_put(np);
- if (!ccm) {
- pr_err("Can't map clock control module reg.\n");
+ if (IS_ERR(clk_diu)) {
+ pr_err("Could not lookup DIU clock.\n");
return;
}
-
- np = of_find_node_by_type(NULL, "cpu");
- if (np) {
- const unsigned int *prop =
- of_get_property(np, "bus-frequency", NULL);
-
- of_node_put(np);
- if (prop) {
- busfreq = *prop;
- } else {
- pr_err("Can't get bus-frequency property\n");
- return;
- }
- } else {
- pr_err("Can't find 'cpu' node.\n");
+ if (clk_prepare_enable(clk_diu)) {
+ pr_err("Could not enable DIU clock.\n");
return;
}
- /* Pixel Clock configuration */
- pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
- speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
-
- /* Calculate the pixel clock with the smallest error */
- /* calculate the following in steps to avoid overflow */
- pr_debug("DIU pixclock in ps - %d\n", pixclock);
- temp = (1000000000 / pixclock) * 1000;
- pixclock = temp;
- pr_debug("DIU pixclock freq - %u\n", pixclock);
-
- temp = temp / 20; /* pixclock * 0.05 */
- pr_debug("deviation = %d\n", temp);
- minpixclock = pixclock - temp;
- maxpixclock = pixclock + temp;
- pr_debug("DIU minpixclock - %lu\n", minpixclock);
- pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
- pixval = speed/pixclock;
- pr_debug("DIU pixval = %lu\n", pixval);
-
- err = LONG_MAX;
- bestval = pixval;
- pr_debug("DIU bestval = %lu\n", bestval);
-
- bestfreq = 0;
- for (i = -1; i <= 1; i++) {
- temp = speed / (pixval+i);
- pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
- i, pixval, temp);
- if ((temp < minpixclock) || (temp > maxpixclock))
- pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
- minpixclock, maxpixclock);
- else if (abs(temp - pixclock) < err) {
- pr_debug("Entered the else if block %d\n", i);
- err = abs(temp - pixclock);
- bestval = pixval + i;
- bestfreq = temp;
- }
+ /*
+ * convert the picoseconds spec into the desired clock rate,
+ * determine the acceptable clock range for the monitor (+/- 5%),
+ * do the calculation in steps to avoid integer overflow
+ */
+ pr_debug("DIU pixclock in ps - %u\n", pixclock);
+ pixclock = (1000000000 / pixclock) * 1000;
+ pr_debug("DIU pixclock freq - %u\n", pixclock);
+ epsilon = pixclock / 20; /* pixclock * 0.05 */
+ pr_debug("DIU deviation - %lu\n", epsilon);
+ minpixclock = pixclock - epsilon;
+ maxpixclock = pixclock + epsilon;
+ pr_debug("DIU minpixclock - %lu\n", minpixclock);
+ pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+
+ /*
+ * check whether the DIU supports the desired pixel clock
+ *
+ * - simply request the desired clock and see what the
+ * platform's clock driver will make of it, assuming that it
+ * will setup the best approximation of the requested value
+ * - try other candidate frequencies in the order of decreasing
+ * preference (i.e. with increasing distance from the desired
+ * pixel clock, and checking the lower frequency before the
+ * higher frequency to not overload the hardware) until the
+ * first match is found -- any potential subsequent match
+ * would only be as good as the former match or typically
+ * would be less preferrable
+ *
+ * the offset increment of pixelclock divided by 64 is an
+ * arbitrary choice -- it's simple to calculate, in the typical
+ * case we expect the first check to succeed already, in the
+ * worst case seven frequencies get tested (the exact center and
+ * three more values each to the left and to the right) before
+ * the 5% tolerance window is exceeded, resulting in fast enough
+ * execution yet high enough probability of finding a suitable
+ * value, while the error rate will be in the order of single
+ * percents
+ */
+ for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
+ want = pixclock - offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
+ if (!offset)
+ continue;
+ want = pixclock + offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
}
+ if (offset <= epsilon) {
+ pr_debug("DIU clock accepted - %lu\n", want);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
+ return;
+ }
+ pr_warn("DIU pixclock auto search unsuccessful\n");
- pr_debug("DIU chose = %lx\n", bestval);
- pr_debug("DIU error = %ld\n NomPixClk ", err);
- pr_debug("DIU: Best Freq = %lx\n", bestfreq);
- /* Modify DIU_DIV in CCM SCFR1 */
- temp = in_be32(&ccm->scfr1);
- pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
- temp &= ~DIU_DIV_MASK;
- temp |= (bestval & DIU_DIV_MASK);
- out_be32(&ccm->scfr1, temp);
- pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
- iounmap(ccm);
+ /*
+ * what is the most appropriate action to take when the search
+ * for an available pixel clock which is acceptable to the
+ * monitor has failed? disable the DIU (clock) or just provide
+ * a "best effort"? we go with the latter
+ */
+ pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
+ clk_set_rate(clk_diu, pixclock);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
}
enum fsl_diu_monitor_port
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 14/24] powerpc/mpc512x: improve DIU related clock setup
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
adapt the DIU clock initialization to the COMMON_CLK approach: device
tree based clock lookup, prepare and unprepare for clocks, work with
frequencies not dividers, call the appropriate clk_*() routines and
don't access CCM registers, remove the pre-enable workaround in the
platform's clock driver
the "best clock" determination now completely relies on the platform's
clock driver to pick a frequency close to what the caller requests, and
merely checks whether the desired frequency was met (is acceptable since
it meets the tolerance of the monitor) -- this approach shall succeed
upon first try in the usual case, will test a few less desirable yet
acceptable frequencies in edge cases, and will fallback to "best effort"
if none of the previously tried frequencies pass the test
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++++++++++++------------
2 files changed, 88 insertions(+), 78 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 218f55b..f31f895 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -705,7 +705,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index a82a41b..3381eea 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -12,6 +12,7 @@
* (at your option) any later version.
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/irq.h>
@@ -70,98 +71,108 @@ struct fsl_diu_shared_fb {
bool in_use;
};
-#define DIU_DIV_MASK 0x000000ff
+/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
void mpc512x_set_pixel_clock(unsigned int pixclock)
{
- unsigned long bestval, bestfreq, speed, busfreq;
- unsigned long minpixclock, maxpixclock, pixval;
- struct mpc512x_ccm __iomem *ccm;
struct device_node *np;
- u32 temp;
- long err;
- int i;
+ struct clk *clk_diu;
+ unsigned long epsilon, minpixclock, maxpixclock;
+ unsigned long offset, want, got, delta;
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ /* lookup and enable the DIU clock */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
if (!np) {
- pr_err("Can't find clock control module.\n");
+ pr_err("Could not find DIU device tree node.\n");
return;
}
-
- ccm = of_iomap(np, 0);
+ clk_diu = of_clk_get_by_name(np, "per");
of_node_put(np);
- if (!ccm) {
- pr_err("Can't map clock control module reg.\n");
+ if (IS_ERR(clk_diu)) {
+ pr_err("Could not lookup DIU clock.\n");
return;
}
-
- np = of_find_node_by_type(NULL, "cpu");
- if (np) {
- const unsigned int *prop =
- of_get_property(np, "bus-frequency", NULL);
-
- of_node_put(np);
- if (prop) {
- busfreq = *prop;
- } else {
- pr_err("Can't get bus-frequency property\n");
- return;
- }
- } else {
- pr_err("Can't find 'cpu' node.\n");
+ if (clk_prepare_enable(clk_diu)) {
+ pr_err("Could not enable DIU clock.\n");
return;
}
- /* Pixel Clock configuration */
- pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
- speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
-
- /* Calculate the pixel clock with the smallest error */
- /* calculate the following in steps to avoid overflow */
- pr_debug("DIU pixclock in ps - %d\n", pixclock);
- temp = (1000000000 / pixclock) * 1000;
- pixclock = temp;
- pr_debug("DIU pixclock freq - %u\n", pixclock);
-
- temp = temp / 20; /* pixclock * 0.05 */
- pr_debug("deviation = %d\n", temp);
- minpixclock = pixclock - temp;
- maxpixclock = pixclock + temp;
- pr_debug("DIU minpixclock - %lu\n", minpixclock);
- pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
- pixval = speed/pixclock;
- pr_debug("DIU pixval = %lu\n", pixval);
-
- err = LONG_MAX;
- bestval = pixval;
- pr_debug("DIU bestval = %lu\n", bestval);
-
- bestfreq = 0;
- for (i = -1; i <= 1; i++) {
- temp = speed / (pixval+i);
- pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
- i, pixval, temp);
- if ((temp < minpixclock) || (temp > maxpixclock))
- pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
- minpixclock, maxpixclock);
- else if (abs(temp - pixclock) < err) {
- pr_debug("Entered the else if block %d\n", i);
- err = abs(temp - pixclock);
- bestval = pixval + i;
- bestfreq = temp;
- }
+ /*
+ * convert the picoseconds spec into the desired clock rate,
+ * determine the acceptable clock range for the monitor (+/- 5%),
+ * do the calculation in steps to avoid integer overflow
+ */
+ pr_debug("DIU pixclock in ps - %u\n", pixclock);
+ pixclock = (1000000000 / pixclock) * 1000;
+ pr_debug("DIU pixclock freq - %u\n", pixclock);
+ epsilon = pixclock / 20; /* pixclock * 0.05 */
+ pr_debug("DIU deviation - %lu\n", epsilon);
+ minpixclock = pixclock - epsilon;
+ maxpixclock = pixclock + epsilon;
+ pr_debug("DIU minpixclock - %lu\n", minpixclock);
+ pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+
+ /*
+ * check whether the DIU supports the desired pixel clock
+ *
+ * - simply request the desired clock and see what the
+ * platform's clock driver will make of it, assuming that it
+ * will setup the best approximation of the requested value
+ * - try other candidate frequencies in the order of decreasing
+ * preference (i.e. with increasing distance from the desired
+ * pixel clock, and checking the lower frequency before the
+ * higher frequency to not overload the hardware) until the
+ * first match is found -- any potential subsequent match
+ * would only be as good as the former match or typically
+ * would be less preferrable
+ *
+ * the offset increment of pixelclock divided by 64 is an
+ * arbitrary choice -- it's simple to calculate, in the typical
+ * case we expect the first check to succeed already, in the
+ * worst case seven frequencies get tested (the exact center and
+ * three more values each to the left and to the right) before
+ * the 5% tolerance window is exceeded, resulting in fast enough
+ * execution yet high enough probability of finding a suitable
+ * value, while the error rate will be in the order of single
+ * percents
+ */
+ for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
+ want = pixclock - offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
+ if (!offset)
+ continue;
+ want = pixclock + offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
}
+ if (offset <= epsilon) {
+ pr_debug("DIU clock accepted - %lu\n", want);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
+ return;
+ }
+ pr_warn("DIU pixclock auto search unsuccessful\n");
- pr_debug("DIU chose = %lx\n", bestval);
- pr_debug("DIU error = %ld\n NomPixClk ", err);
- pr_debug("DIU: Best Freq = %lx\n", bestfreq);
- /* Modify DIU_DIV in CCM SCFR1 */
- temp = in_be32(&ccm->scfr1);
- pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
- temp &= ~DIU_DIV_MASK;
- temp |= (bestval & DIU_DIV_MASK);
- out_be32(&ccm->scfr1, temp);
- pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
- iounmap(ccm);
+ /*
+ * what is the most appropriate action to take when the search
+ * for an available pixel clock which is acceptable to the
+ * monitor has failed? disable the DIU (clock) or just provide
+ * a "best effort"? we go with the latter
+ */
+ pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
+ clk_set_rate(clk_diu, pixclock);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
}
enum fsl_diu_monitor_port
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 14/24] powerpc/mpc512x: improve DIU related clock setup
@ 2013-07-15 18:47 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 18:47 UTC (permalink / raw)
To: linux-arm-kernel
adapt the DIU clock initialization to the COMMON_CLK approach: device
tree based clock lookup, prepare and unprepare for clocks, work with
frequencies not dividers, call the appropriate clk_*() routines and
don't access CCM registers, remove the pre-enable workaround in the
platform's clock driver
the "best clock" determination now completely relies on the platform's
clock driver to pick a frequency close to what the caller requests, and
merely checks whether the desired frequency was met (is acceptable since
it meets the tolerance of the monitor) -- this approach shall succeed
upon first try in the usual case, will test a few less desirable yet
acceptable frequencies in edge cases, and will fallback to "best effort"
if none of the previously tried frequencies pass the test
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++++++++++++------------
2 files changed, 88 insertions(+), 78 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 218f55b..f31f895 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -705,7 +705,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index a82a41b..3381eea 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -12,6 +12,7 @@
* (at your option) any later version.
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/irq.h>
@@ -70,98 +71,108 @@ struct fsl_diu_shared_fb {
bool in_use;
};
-#define DIU_DIV_MASK 0x000000ff
+/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
void mpc512x_set_pixel_clock(unsigned int pixclock)
{
- unsigned long bestval, bestfreq, speed, busfreq;
- unsigned long minpixclock, maxpixclock, pixval;
- struct mpc512x_ccm __iomem *ccm;
struct device_node *np;
- u32 temp;
- long err;
- int i;
+ struct clk *clk_diu;
+ unsigned long epsilon, minpixclock, maxpixclock;
+ unsigned long offset, want, got, delta;
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ /* lookup and enable the DIU clock */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
if (!np) {
- pr_err("Can't find clock control module.\n");
+ pr_err("Could not find DIU device tree node.\n");
return;
}
-
- ccm = of_iomap(np, 0);
+ clk_diu = of_clk_get_by_name(np, "per");
of_node_put(np);
- if (!ccm) {
- pr_err("Can't map clock control module reg.\n");
+ if (IS_ERR(clk_diu)) {
+ pr_err("Could not lookup DIU clock.\n");
return;
}
-
- np = of_find_node_by_type(NULL, "cpu");
- if (np) {
- const unsigned int *prop =
- of_get_property(np, "bus-frequency", NULL);
-
- of_node_put(np);
- if (prop) {
- busfreq = *prop;
- } else {
- pr_err("Can't get bus-frequency property\n");
- return;
- }
- } else {
- pr_err("Can't find 'cpu' node.\n");
+ if (clk_prepare_enable(clk_diu)) {
+ pr_err("Could not enable DIU clock.\n");
return;
}
- /* Pixel Clock configuration */
- pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
- speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
-
- /* Calculate the pixel clock with the smallest error */
- /* calculate the following in steps to avoid overflow */
- pr_debug("DIU pixclock in ps - %d\n", pixclock);
- temp = (1000000000 / pixclock) * 1000;
- pixclock = temp;
- pr_debug("DIU pixclock freq - %u\n", pixclock);
-
- temp = temp / 20; /* pixclock * 0.05 */
- pr_debug("deviation = %d\n", temp);
- minpixclock = pixclock - temp;
- maxpixclock = pixclock + temp;
- pr_debug("DIU minpixclock - %lu\n", minpixclock);
- pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
- pixval = speed/pixclock;
- pr_debug("DIU pixval = %lu\n", pixval);
-
- err = LONG_MAX;
- bestval = pixval;
- pr_debug("DIU bestval = %lu\n", bestval);
-
- bestfreq = 0;
- for (i = -1; i <= 1; i++) {
- temp = speed / (pixval+i);
- pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
- i, pixval, temp);
- if ((temp < minpixclock) || (temp > maxpixclock))
- pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
- minpixclock, maxpixclock);
- else if (abs(temp - pixclock) < err) {
- pr_debug("Entered the else if block %d\n", i);
- err = abs(temp - pixclock);
- bestval = pixval + i;
- bestfreq = temp;
- }
+ /*
+ * convert the picoseconds spec into the desired clock rate,
+ * determine the acceptable clock range for the monitor (+/- 5%),
+ * do the calculation in steps to avoid integer overflow
+ */
+ pr_debug("DIU pixclock in ps - %u\n", pixclock);
+ pixclock = (1000000000 / pixclock) * 1000;
+ pr_debug("DIU pixclock freq - %u\n", pixclock);
+ epsilon = pixclock / 20; /* pixclock * 0.05 */
+ pr_debug("DIU deviation - %lu\n", epsilon);
+ minpixclock = pixclock - epsilon;
+ maxpixclock = pixclock + epsilon;
+ pr_debug("DIU minpixclock - %lu\n", minpixclock);
+ pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+
+ /*
+ * check whether the DIU supports the desired pixel clock
+ *
+ * - simply request the desired clock and see what the
+ * platform's clock driver will make of it, assuming that it
+ * will setup the best approximation of the requested value
+ * - try other candidate frequencies in the order of decreasing
+ * preference (i.e. with increasing distance from the desired
+ * pixel clock, and checking the lower frequency before the
+ * higher frequency to not overload the hardware) until the
+ * first match is found -- any potential subsequent match
+ * would only be as good as the former match or typically
+ * would be less preferrable
+ *
+ * the offset increment of pixelclock divided by 64 is an
+ * arbitrary choice -- it's simple to calculate, in the typical
+ * case we expect the first check to succeed already, in the
+ * worst case seven frequencies get tested (the exact center and
+ * three more values each to the left and to the right) before
+ * the 5% tolerance window is exceeded, resulting in fast enough
+ * execution yet high enough probability of finding a suitable
+ * value, while the error rate will be in the order of single
+ * percents
+ */
+ for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
+ want = pixclock - offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
+ if (!offset)
+ continue;
+ want = pixclock + offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
}
+ if (offset <= epsilon) {
+ pr_debug("DIU clock accepted - %lu\n", want);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
+ return;
+ }
+ pr_warn("DIU pixclock auto search unsuccessful\n");
- pr_debug("DIU chose = %lx\n", bestval);
- pr_debug("DIU error = %ld\n NomPixClk ", err);
- pr_debug("DIU: Best Freq = %lx\n", bestfreq);
- /* Modify DIU_DIV in CCM SCFR1 */
- temp = in_be32(&ccm->scfr1);
- pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
- temp &= ~DIU_DIV_MASK;
- temp |= (bestval & DIU_DIV_MASK);
- out_be32(&ccm->scfr1, temp);
- pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
- iounmap(ccm);
+ /*
+ * what is the most appropriate action to take when the search
+ * for an available pixel clock which is acceptable to the
+ * monitor has failed? disable the DIU (clock) or just provide
+ * a "best effort"? we go with the latter
+ */
+ pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
+ clk_set_rate(clk_diu, pixclock);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
}
enum fsl_diu_monitor_port
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
2013-07-15 18:47 ` Gerhard Sittig
@ 2013-07-15 19:38 ` Sascha Hauer
-1 siblings, 0 replies; 432+ messages in thread
From: Sascha Hauer @ 2013-07-15 19:38 UTC (permalink / raw)
To: Gerhard Sittig
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss, Rob Herring, Mark Brown, Marc Kleine-Budde,
Wolfgang Grandegger, Anatolij Gustschin, linuxppc-dev,
David Woodhouse, linux-arm-kernel, Mauro Carvalho Chehab
On Mon, Jul 15, 2013 at 08:47:34PM +0200, Gerhard Sittig wrote:
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 6d55eb2..2c07061 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> struct clk_divider *divider = to_clk_divider(hw);
> unsigned int div, val;
>
> - val = readl(divider->reg) >> divider->shift;
> + val = clk_readl(divider->reg) >> divider->shift;
> val &= div_mask(divider);
Would it be an option to use regmap for the generic dividers/muxes
instead? This should be suitable for ppc and also for people who want to
use the generic clocks on i2c devices.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-15 19:38 ` Sascha Hauer
0 siblings, 0 replies; 432+ messages in thread
From: Sascha Hauer @ 2013-07-15 19:38 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 15, 2013 at 08:47:34PM +0200, Gerhard Sittig wrote:
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 6d55eb2..2c07061 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> struct clk_divider *divider = to_clk_divider(hw);
> unsigned int div, val;
>
> - val = readl(divider->reg) >> divider->shift;
> + val = clk_readl(divider->reg) >> divider->shift;
> val &= div_mask(divider);
Would it be an option to use regmap for the generic dividers/muxes
instead? This should be suitable for ppc and also for people who want to
use the generic clocks on i2c devices.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 20:17 ` Mark Brown
-1 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-15 20:17 UTC (permalink / raw)
To: Gerhard Sittig
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, David Woodhouse,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Greg Kroah-Hartman,
Rob Herring, Marc Kleine-Budde, Wolfgang Grandegger,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Mauro Carvalho Chehab
[-- Attachment #1.1: Type: text/plain, Size: 1065 bytes --]
On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
> clocks need to get prepared before they can get enabled,
> fix the MPC512x PSC SPI master's initialization
> Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
> ---
> drivers/spi/spi-mpc512x-psc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
> index 29fce6a..76b20ea 100644
> --- a/drivers/spi/spi-mpc512x-psc.c
> +++ b/drivers/spi/spi-mpc512x-psc.c
> @@ -395,7 +395,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
>
> sprintf(name, "psc%d_mclk", master->bus_num);
> spiclk = clk_get(&master->dev, name);
> - clk_enable(spiclk);
> + clk_prepare_enable(spiclk);
> mps->mclk = clk_get_rate(spiclk);
> clk_put(spiclk);
This code is *clearly* buggy and should be fixed rather than papered
over. Not only is there no matching put the driver is also dropping the
reference to the clock rather than holding on to it while it's in use.
[-- Attachment #1.2: Digital signature --]
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[-- Attachment #2: Type: text/plain, Size: 192 bytes --]
_______________________________________________
devicetree-discuss mailing list
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-15 20:17 ` Mark Brown
0 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-15 20:17 UTC (permalink / raw)
To: Gerhard Sittig
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, David Woodhouse,
devicetree-discuss, Greg Kroah-Hartman, Rob Herring,
Marc Kleine-Budde, Wolfgang Grandegger, Anatolij Gustschin,
linuxppc-dev, linux-arm-kernel, Mauro Carvalho Chehab
[-- Attachment #1: Type: text/plain, Size: 1044 bytes --]
On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
> clocks need to get prepared before they can get enabled,
> fix the MPC512x PSC SPI master's initialization
> Signed-off-by: Gerhard Sittig <gsi@denx.de>
> ---
> drivers/spi/spi-mpc512x-psc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
> index 29fce6a..76b20ea 100644
> --- a/drivers/spi/spi-mpc512x-psc.c
> +++ b/drivers/spi/spi-mpc512x-psc.c
> @@ -395,7 +395,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
>
> sprintf(name, "psc%d_mclk", master->bus_num);
> spiclk = clk_get(&master->dev, name);
> - clk_enable(spiclk);
> + clk_prepare_enable(spiclk);
> mps->mclk = clk_get_rate(spiclk);
> clk_put(spiclk);
This code is *clearly* buggy and should be fixed rather than papered
over. Not only is there no matching put the driver is also dropping the
reference to the clock rather than holding on to it while it's in use.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-15 20:17 ` Mark Brown
0 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-15 20:17 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
> clocks need to get prepared before they can get enabled,
> fix the MPC512x PSC SPI master's initialization
> Signed-off-by: Gerhard Sittig <gsi@denx.de>
> ---
> drivers/spi/spi-mpc512x-psc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
> index 29fce6a..76b20ea 100644
> --- a/drivers/spi/spi-mpc512x-psc.c
> +++ b/drivers/spi/spi-mpc512x-psc.c
> @@ -395,7 +395,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
>
> sprintf(name, "psc%d_mclk", master->bus_num);
> spiclk = clk_get(&master->dev, name);
> - clk_enable(spiclk);
> + clk_prepare_enable(spiclk);
> mps->mclk = clk_get_rate(spiclk);
> clk_put(spiclk);
This code is *clearly* buggy and should be fixed rather than papered
over. Not only is there no matching put the driver is also dropping the
reference to the clock rather than holding on to it while it's in use.
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^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 15/24] serial: mpc512x: OF clock lookup, use the 'mclk' name
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-15 21:46 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 21:46 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
with device tree based clock lookup, the MCLK name no longer
depends on the PSC index
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
drivers/tty/serial/mpc52xx_uart.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index 53c1093..221fb89 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -619,21 +619,17 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
static int mpc512x_psc_clock(struct uart_port *port, int enable)
{
struct clk *psc_clk;
- int psc_num;
- char clk_name[10];
if (uart_console(port))
return 0;
- psc_num = (port->mapbase & 0xf00) >> 8;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- psc_clk = clk_get(port->dev, clk_name);
+ psc_clk = clk_get(port->dev, "mclk");
if (IS_ERR(psc_clk)) {
dev_err(port->dev, "Failed to get PSC clock entry!\n");
return -ENODEV;
}
- dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
+ dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
if (enable)
clk_prepare_enable(psc_clk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 15/24] serial: mpc512x: OF clock lookup, use the 'mclk' name
@ 2013-07-15 21:46 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 21:46 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
with device tree based clock lookup, the MCLK name no longer
depends on the PSC index
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/tty/serial/mpc52xx_uart.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index 53c1093..221fb89 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -619,21 +619,17 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
static int mpc512x_psc_clock(struct uart_port *port, int enable)
{
struct clk *psc_clk;
- int psc_num;
- char clk_name[10];
if (uart_console(port))
return 0;
- psc_num = (port->mapbase & 0xf00) >> 8;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- psc_clk = clk_get(port->dev, clk_name);
+ psc_clk = clk_get(port->dev, "mclk");
if (IS_ERR(psc_clk)) {
dev_err(port->dev, "Failed to get PSC clock entry!\n");
return -ENODEV;
}
- dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
+ dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
if (enable)
clk_prepare_enable(psc_clk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 15/24] serial: mpc512x: OF clock lookup, use the 'mclk' name
@ 2013-07-15 21:46 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-15 21:46 UTC (permalink / raw)
To: linux-arm-kernel
with device tree based clock lookup, the MCLK name no longer
depends on the PSC index
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/tty/serial/mpc52xx_uart.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index 53c1093..221fb89 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -619,21 +619,17 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
static int mpc512x_psc_clock(struct uart_port *port, int enable)
{
struct clk *psc_clk;
- int psc_num;
- char clk_name[10];
if (uart_console(port))
return 0;
- psc_num = (port->mapbase & 0xf00) >> 8;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- psc_clk = clk_get(port->dev, clk_name);
+ psc_clk = clk_get(port->dev, "mclk");
if (IS_ERR(psc_clk)) {
dev_err(port->dev, "Failed to get PSC clock entry!\n");
return -ENODEV;
}
- dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
+ dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
if (enable)
clk_prepare_enable(psc_clk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* Re: [PATCH v1 15/24] serial: mpc512x: OF clock lookup, use the 'mclk' name
2013-07-15 21:46 ` Gerhard Sittig
@ 2013-07-15 21:54 ` Sascha Hauer
-1 siblings, 0 replies; 432+ messages in thread
From: Sascha Hauer @ 2013-07-15 21:54 UTC (permalink / raw)
To: Gerhard Sittig
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss, Rob Herring, Mark Brown, Marc Kleine-Budde,
Wolfgang Grandegger, Anatolij Gustschin, linuxppc-dev,
David Woodhouse, linux-arm-kernel, Mauro Carvalho Chehab
On Mon, Jul 15, 2013 at 11:46:01PM +0200, Gerhard Sittig wrote:
> with device tree based clock lookup, the MCLK name no longer
> depends on the PSC index
>
> Signed-off-by: Gerhard Sittig <gsi@denx.de>
> ---
> drivers/tty/serial/mpc52xx_uart.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
> index 53c1093..221fb89 100644
> --- a/drivers/tty/serial/mpc52xx_uart.c
> +++ b/drivers/tty/serial/mpc52xx_uart.c
> @@ -619,21 +619,17 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
> static int mpc512x_psc_clock(struct uart_port *port, int enable)
> {
> struct clk *psc_clk;
> - int psc_num;
> - char clk_name[10];
>
> if (uart_console(port))
> return 0;
>
> - psc_num = (port->mapbase & 0xf00) >> 8;
> - snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
> - psc_clk = clk_get(port->dev, clk_name);
> + psc_clk = clk_get(port->dev, "mclk");
Same comment applies here as Mark made to the spi driver.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 15/24] serial: mpc512x: OF clock lookup, use the 'mclk' name
@ 2013-07-15 21:54 ` Sascha Hauer
0 siblings, 0 replies; 432+ messages in thread
From: Sascha Hauer @ 2013-07-15 21:54 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 15, 2013 at 11:46:01PM +0200, Gerhard Sittig wrote:
> with device tree based clock lookup, the MCLK name no longer
> depends on the PSC index
>
> Signed-off-by: Gerhard Sittig <gsi@denx.de>
> ---
> drivers/tty/serial/mpc52xx_uart.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
> index 53c1093..221fb89 100644
> --- a/drivers/tty/serial/mpc52xx_uart.c
> +++ b/drivers/tty/serial/mpc52xx_uart.c
> @@ -619,21 +619,17 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
> static int mpc512x_psc_clock(struct uart_port *port, int enable)
> {
> struct clk *psc_clk;
> - int psc_num;
> - char clk_name[10];
>
> if (uart_console(port))
> return 0;
>
> - psc_num = (port->mapbase & 0xf00) >> 8;
> - snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
> - psc_clk = clk_get(port->dev, clk_name);
> + psc_clk = clk_get(port->dev, "mclk");
Same comment applies here as Mark made to the spi driver.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 16/24] clk: mpc512x: remove now obsolete clkdev registration
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-16 6:05 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
after the PSC drivers for UART and SPI mode got converted to device tree
based clock lookup, the former MCLK name which depends on the PSC index
isn't needed any longer -- remove the clk_register_clkdev() invocation
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index f31f895..31707b5 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -529,16 +529,6 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
entry->name_mclk,
entry->name_mux1, 1, 1);
}
-
- /*
- * without this "clock device" registration, "simple" lookups in
- * the SPI master initialization and serial port setup will fail
- *
- * those drivers need to get adjusted to lookup their required
- * clocks from OF specs, before this clkdev registration becomes
- * obsolete
- */
- clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
}
static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 16/24] clk: mpc512x: remove now obsolete clkdev registration
@ 2013-07-16 6:05 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
after the PSC drivers for UART and SPI mode got converted to device tree
based clock lookup, the former MCLK name which depends on the PSC index
isn't needed any longer -- remove the clk_register_clkdev() invocation
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index f31f895..31707b5 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -529,16 +529,6 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
entry->name_mclk,
entry->name_mux1, 1, 1);
}
-
- /*
- * without this "clock device" registration, "simple" lookups in
- * the SPI master initialization and serial port setup will fail
- *
- * those drivers need to get adjusted to lookup their required
- * clocks from OF specs, before this clkdev registration becomes
- * obsolete
- */
- clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
}
static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 16/24] clk: mpc512x: remove now obsolete clkdev registration
@ 2013-07-16 6:05 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linux-arm-kernel
after the PSC drivers for UART and SPI mode got converted to device tree
based clock lookup, the former MCLK name which depends on the PSC index
isn't needed any longer -- remove the clk_register_clkdev() invocation
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index f31f895..31707b5 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -529,16 +529,6 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
entry->name_mclk,
entry->name_mux1, 1, 1);
}
-
- /*
- * without this "clock device" registration, "simple" lookups in
- * the SPI master initialization and serial port setup will fail
- *
- * those drivers need to get adjusted to lookup their required
- * clocks from OF specs, before this clkdev registration becomes
- * obsolete
- */
- clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
}
static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 17/24] serial: mpc512x: setup the PSC FIFO clock as well
2013-07-15 18:47 ` Gerhard Sittig
@ 2013-07-16 6:05 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
prepare and enable the FIFO clock upon PSC FIFO initialization, disable
and unprepare the FIFO clock upon PSC FIFO uninitialization, remove the
pre-enable workaround from the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 2 --
drivers/tty/serial/mpc52xx_uart.c | 47 +++++++++++++++++++++----
2 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 31707b5..2c6da07 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -690,8 +690,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
- /* some are required yet no dependencies were declared */
- clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index 221fb89..e67d4c0 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -567,35 +567,70 @@ static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
static int __init mpc512x_psc_fifoc_init(void)
{
struct device_node *np;
+ struct clk *clk;
np = of_find_compatible_node(NULL, NULL,
"fsl,mpc5121-psc-fifo");
if (!np) {
pr_err("%s: Can't find FIFOC node\n", __func__);
- return -ENODEV;
+ goto out_err;
+ }
+
+ clk = of_clk_get_by_name(np, "per");
+ if (IS_ERR(clk)) {
+ pr_err("%s: Can't lookup FIFO clock\n", __func__);
+ goto out_ofnode_put;
+ }
+ if (clk_prepare_enable(clk)) {
+ pr_err("%s: Can't enable FIFO clock\n", __func__);
+ goto out_clk_put;
}
psc_fifoc = of_iomap(np, 0);
if (!psc_fifoc) {
pr_err("%s: Can't map FIFOC\n", __func__);
- of_node_put(np);
- return -ENODEV;
+ goto out_clk_disable;
}
psc_fifoc_irq = irq_of_parse_and_map(np, 0);
- of_node_put(np);
if (psc_fifoc_irq == 0) {
pr_err("%s: Can't get FIFOC irq\n", __func__);
- iounmap(psc_fifoc);
- return -ENODEV;
+ goto out_unmap;
}
+ clk_put(clk);
+ of_node_put(np);
return 0;
+
+out_unmap:
+ iounmap(psc_fifoc);
+out_clk_disable:
+ clk_disable_unprepare(clk);
+out_clk_put:
+ clk_put(clk);
+out_ofnode_put:
+ of_node_put(np);
+out_err:
+ return -ENODEV;
}
static void __exit mpc512x_psc_fifoc_uninit(void)
{
+ struct device_node *np;
+ struct clk *clk;
+
iounmap(psc_fifoc);
+
+ /* disable the clock, errors are not fatal */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-psc-fifo");
+ if (np) {
+ clk = of_clk_get_by_name(np, "per");
+ if (!IS_ERR(clk)) {
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+ }
+ of_node_put(np);
+ }
}
/* 512x specific interrupt handler. The caller holds the port lock */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 17/24] serial: mpc512x: setup the PSC FIFO clock as well
@ 2013-07-16 6:05 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linux-arm-kernel
prepare and enable the FIFO clock upon PSC FIFO initialization, disable
and unprepare the FIFO clock upon PSC FIFO uninitialization, remove the
pre-enable workaround from the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 2 --
drivers/tty/serial/mpc52xx_uart.c | 47 +++++++++++++++++++++----
2 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 31707b5..2c6da07 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -690,8 +690,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
- /* some are required yet no dependencies were declared */
- clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index 221fb89..e67d4c0 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -567,35 +567,70 @@ static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
static int __init mpc512x_psc_fifoc_init(void)
{
struct device_node *np;
+ struct clk *clk;
np = of_find_compatible_node(NULL, NULL,
"fsl,mpc5121-psc-fifo");
if (!np) {
pr_err("%s: Can't find FIFOC node\n", __func__);
- return -ENODEV;
+ goto out_err;
+ }
+
+ clk = of_clk_get_by_name(np, "per");
+ if (IS_ERR(clk)) {
+ pr_err("%s: Can't lookup FIFO clock\n", __func__);
+ goto out_ofnode_put;
+ }
+ if (clk_prepare_enable(clk)) {
+ pr_err("%s: Can't enable FIFO clock\n", __func__);
+ goto out_clk_put;
}
psc_fifoc = of_iomap(np, 0);
if (!psc_fifoc) {
pr_err("%s: Can't map FIFOC\n", __func__);
- of_node_put(np);
- return -ENODEV;
+ goto out_clk_disable;
}
psc_fifoc_irq = irq_of_parse_and_map(np, 0);
- of_node_put(np);
if (psc_fifoc_irq == 0) {
pr_err("%s: Can't get FIFOC irq\n", __func__);
- iounmap(psc_fifoc);
- return -ENODEV;
+ goto out_unmap;
}
+ clk_put(clk);
+ of_node_put(np);
return 0;
+
+out_unmap:
+ iounmap(psc_fifoc);
+out_clk_disable:
+ clk_disable_unprepare(clk);
+out_clk_put:
+ clk_put(clk);
+out_ofnode_put:
+ of_node_put(np);
+out_err:
+ return -ENODEV;
}
static void __exit mpc512x_psc_fifoc_uninit(void)
{
+ struct device_node *np;
+ struct clk *clk;
+
iounmap(psc_fifoc);
+
+ /* disable the clock, errors are not fatal */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-psc-fifo");
+ if (np) {
+ clk = of_clk_get_by_name(np, "per");
+ if (!IS_ERR(clk)) {
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+ }
+ of_node_put(np);
+ }
}
/* 512x specific interrupt handler. The caller holds the port lock */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 18/24] i2c: mpc: OF clock lookup for MPC512x
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-16 6:05 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
make the MPC I2C driver prepare and enable the peripheral clock
('per' for register access) in the MPC512x setup routine,
make this clock setup non-fatal to allow for a migration period,
remove the pre-enabling hack in the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
drivers/i2c/busses/i2c-mpc.c | 9 +++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 2c6da07..29c51a5 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -693,7 +693,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
* items and their individual enable counters, yet share a
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 7607dc0..13d6822 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -21,6 +21,7 @@
#include <linux/of_i2c.h>
#include <linux/slab.h>
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/i2c.h>
@@ -264,11 +265,19 @@ static void mpc_i2c_setup_512x(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler)
{
+ struct clk *clk;
struct device_node *node_ctrl;
void __iomem *ctrl;
const u32 *pval;
u32 idx;
+ /* enable clock for the I2C peripheral (non fatal) */
+ clk = of_clk_get_by_name(node, "per");
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
+
/* Enable I2C interrupts for mpc5121 */
node_ctrl = of_find_compatible_node(NULL, NULL,
"fsl,mpc5121-i2c-ctrl");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 18/24] i2c: mpc: OF clock lookup for MPC512x
@ 2013-07-16 6:05 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
make the MPC I2C driver prepare and enable the peripheral clock
('per' for register access) in the MPC512x setup routine,
make this clock setup non-fatal to allow for a migration period,
remove the pre-enabling hack in the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
drivers/i2c/busses/i2c-mpc.c | 9 +++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 2c6da07..29c51a5 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -693,7 +693,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
* items and their individual enable counters, yet share a
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 7607dc0..13d6822 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -21,6 +21,7 @@
#include <linux/of_i2c.h>
#include <linux/slab.h>
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/i2c.h>
@@ -264,11 +265,19 @@ static void mpc_i2c_setup_512x(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler)
{
+ struct clk *clk;
struct device_node *node_ctrl;
void __iomem *ctrl;
const u32 *pval;
u32 idx;
+ /* enable clock for the I2C peripheral (non fatal) */
+ clk = of_clk_get_by_name(node, "per");
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
+
/* Enable I2C interrupts for mpc5121 */
node_ctrl = of_find_compatible_node(NULL, NULL,
"fsl,mpc5121-i2c-ctrl");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 18/24] i2c: mpc: OF clock lookup for MPC512x
@ 2013-07-16 6:05 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linux-arm-kernel
make the MPC I2C driver prepare and enable the peripheral clock
('per' for register access) in the MPC512x setup routine,
make this clock setup non-fatal to allow for a migration period,
remove the pre-enabling hack in the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
drivers/i2c/busses/i2c-mpc.c | 9 +++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 2c6da07..29c51a5 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -693,7 +693,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
* items and their individual enable counters, yet share a
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 7607dc0..13d6822 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -21,6 +21,7 @@
#include <linux/of_i2c.h>
#include <linux/slab.h>
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/i2c.h>
@@ -264,11 +265,19 @@ static void mpc_i2c_setup_512x(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler)
{
+ struct clk *clk;
struct device_node *node_ctrl;
void __iomem *ctrl;
const u32 *pval;
u32 idx;
+ /* enable clock for the I2C peripheral (non fatal) */
+ clk = of_clk_get_by_name(node, "per");
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
+
/* Enable I2C interrupts for mpc5121 */
node_ctrl = of_find_compatible_node(NULL, NULL,
"fsl,mpc5121-i2c-ctrl");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 19/24] USB: fsl-mph-dr-of: OF clock lookup, prepare and enable
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-16 6:05 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
device tree based clock lookup in the MPC512x initialization (lookup
'per' for register access), add error check in the clock setup, must
prepare clocks before they can get enabled, unprepare after disable
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/usb/host/fsl-mph-dr-of.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 11e0b79..eb564f3 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -260,25 +260,19 @@ int fsl_usb2_mpc5121_init(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
struct clk *clk;
- char clk_name[10];
- int base, clk_num;
-
- base = pdev->resource->start & 0xf000;
- if (base == 0x3000)
- clk_num = 1;
- else if (base == 0x4000)
- clk_num = 2;
- else
- return -ENODEV;
+ int err;
- snprintf(clk_name, sizeof(clk_name), "usb%d_clk", clk_num);
- clk = clk_get(&pdev->dev, clk_name);
+ clk = clk_get(&pdev->dev, "per");
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "failed to get clk\n");
return PTR_ERR(clk);
}
-
- clk_enable(clk);
+ err = clk_prepare_enable(clk);
+ if (err) {
+ dev_err(&pdev->dev, "failed to enable clk\n");
+ clk_put(clk);
+ return err;
+ }
pdata->clk = clk;
if (pdata->phy_mode == FSL_USB2_PHY_UTMI_WIDE) {
@@ -303,7 +297,7 @@ static void fsl_usb2_mpc5121_exit(struct platform_device *pdev)
pdata->regs = NULL;
if (pdata->clk) {
- clk_disable(pdata->clk);
+ clk_disable_unprepare(pdata->clk);
clk_put(pdata->clk);
}
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 19/24] USB: fsl-mph-dr-of: OF clock lookup, prepare and enable
@ 2013-07-16 6:05 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
device tree based clock lookup in the MPC512x initialization (lookup
'per' for register access), add error check in the clock setup, must
prepare clocks before they can get enabled, unprepare after disable
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/usb/host/fsl-mph-dr-of.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 11e0b79..eb564f3 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -260,25 +260,19 @@ int fsl_usb2_mpc5121_init(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
struct clk *clk;
- char clk_name[10];
- int base, clk_num;
-
- base = pdev->resource->start & 0xf000;
- if (base == 0x3000)
- clk_num = 1;
- else if (base == 0x4000)
- clk_num = 2;
- else
- return -ENODEV;
+ int err;
- snprintf(clk_name, sizeof(clk_name), "usb%d_clk", clk_num);
- clk = clk_get(&pdev->dev, clk_name);
+ clk = clk_get(&pdev->dev, "per");
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "failed to get clk\n");
return PTR_ERR(clk);
}
-
- clk_enable(clk);
+ err = clk_prepare_enable(clk);
+ if (err) {
+ dev_err(&pdev->dev, "failed to enable clk\n");
+ clk_put(clk);
+ return err;
+ }
pdata->clk = clk;
if (pdata->phy_mode == FSL_USB2_PHY_UTMI_WIDE) {
@@ -303,7 +297,7 @@ static void fsl_usb2_mpc5121_exit(struct platform_device *pdev)
pdata->regs = NULL;
if (pdata->clk) {
- clk_disable(pdata->clk);
+ clk_disable_unprepare(pdata->clk);
clk_put(pdata->clk);
}
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 19/24] USB: fsl-mph-dr-of: OF clock lookup, prepare and enable
@ 2013-07-16 6:05 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linux-arm-kernel
device tree based clock lookup in the MPC512x initialization (lookup
'per' for register access), add error check in the clock setup, must
prepare clocks before they can get enabled, unprepare after disable
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/usb/host/fsl-mph-dr-of.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 11e0b79..eb564f3 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -260,25 +260,19 @@ int fsl_usb2_mpc5121_init(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
struct clk *clk;
- char clk_name[10];
- int base, clk_num;
-
- base = pdev->resource->start & 0xf000;
- if (base == 0x3000)
- clk_num = 1;
- else if (base == 0x4000)
- clk_num = 2;
- else
- return -ENODEV;
+ int err;
- snprintf(clk_name, sizeof(clk_name), "usb%d_clk", clk_num);
- clk = clk_get(&pdev->dev, clk_name);
+ clk = clk_get(&pdev->dev, "per");
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "failed to get clk\n");
return PTR_ERR(clk);
}
-
- clk_enable(clk);
+ err = clk_prepare_enable(clk);
+ if (err) {
+ dev_err(&pdev->dev, "failed to enable clk\n");
+ clk_put(clk);
+ return err;
+ }
pdata->clk = clk;
if (pdata->phy_mode == FSL_USB2_PHY_UTMI_WIDE) {
@@ -303,7 +297,7 @@ static void fsl_usb2_mpc5121_exit(struct platform_device *pdev)
pdata->regs = NULL;
if (pdata->clk) {
- clk_disable(pdata->clk);
+ clk_disable_unprepare(pdata->clk);
clk_put(pdata->clk);
}
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 20/24] fs_enet: OF clock lookup (non-fatal), prepare and enable
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-16 6:05 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
device tree based clock lookup, must prepare clocks before enabling
them, unprepare after disable, error check in the clock setup, remove
the pre-enable workaround in the MPC512x platform's clock driver
this change implements non-fatal clock lookup since not all platforms
provide device tree specs for clocks, but failure to enable a specified
clock is considered fatal
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 27 +++++++++++++++++++-
include/linux/fs_enet_pd.h | 3 +++
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 29c51a5..31d0cf3 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -692,7 +692,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
- clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
/*
* some have their individual clock subtree with separate clock
* items and their individual enable counters, yet share a
diff --git a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
index 8de53a1..df92e12 100644
--- a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
+++ b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
@@ -1020,6 +1020,21 @@ static int fs_enet_probe(struct platform_device *ofdev)
fpi->cp_command = *data;
}
+ /* make clock lookup non-fatal (the driver is shared among platforms),
+ * but require enable to succeed when a clock was specified/found
+ */
+ fpi->clk_per = clk_get(&ofdev->dev, "per");
+ if (IS_ERR(fpi->clk_per))
+ fpi->clk_per = NULL;
+ if (fpi->clk_per) {
+ int err;
+ err = clk_prepare_enable(fpi->clk_per);
+ if (err) {
+ ret = err;
+ goto out_clk_put;
+ }
+ }
+
fpi->rx_ring = 32;
fpi->tx_ring = 32;
fpi->rx_copybreak = 240;
@@ -1028,7 +1043,7 @@ static int fs_enet_probe(struct platform_device *ofdev)
fpi->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0);
if ((!fpi->phy_node) && (!of_get_property(ofdev->dev.of_node, "fixed-link",
NULL)))
- goto out_free_fpi;
+ goto out_clk_dis;
if (of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc5125-fec")) {
phy_connection_type = of_get_property(ofdev->dev.of_node,
@@ -1108,6 +1123,12 @@ out_free_dev:
free_netdev(ndev);
out_put:
of_node_put(fpi->phy_node);
+out_clk_dis:
+ if (fpi->clk_per)
+ clk_disable_unprepare(fpi->clk_per);
+out_clk_put:
+ if (fpi->clk_per)
+ clk_put(fpi->clk_per);
out_free_fpi:
kfree(fpi);
return ret;
@@ -1124,6 +1145,10 @@ static int fs_enet_remove(struct platform_device *ofdev)
fep->ops->cleanup_data(ndev);
dev_set_drvdata(fep->dev, NULL);
of_node_put(fep->fpi->phy_node);
+ if (fep->fpi->clk_per) {
+ clk_disable_unprepare(fep->fpi->clk_per);
+ clk_put(fep->fpi->clk_per);
+ }
free_netdev(ndev);
return 0;
}
diff --git a/include/linux/fs_enet_pd.h b/include/linux/fs_enet_pd.h
index 51b7934..a978d0d 100644
--- a/include/linux/fs_enet_pd.h
+++ b/include/linux/fs_enet_pd.h
@@ -16,6 +16,7 @@
#ifndef FS_ENET_PD_H
#define FS_ENET_PD_H
+#include <linux/clk.h>
#include <linux/string.h>
#include <linux/of_mdio.h>
#include <asm/types.h>
@@ -142,6 +143,8 @@ struct fs_platform_info {
int use_rmii; /* use RMII mode */
int has_phy; /* if the network is phy container as well...*/
+
+ struct clk *clk_per; /* 'per' clock for register access */
};
struct fs_mii_fec_platform_info {
u32 irq[32];
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 20/24] fs_enet: OF clock lookup (non-fatal), prepare and enable
@ 2013-07-16 6:05 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
device tree based clock lookup, must prepare clocks before enabling
them, unprepare after disable, error check in the clock setup, remove
the pre-enable workaround in the MPC512x platform's clock driver
this change implements non-fatal clock lookup since not all platforms
provide device tree specs for clocks, but failure to enable a specified
clock is considered fatal
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 27 +++++++++++++++++++-
include/linux/fs_enet_pd.h | 3 +++
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 29c51a5..31d0cf3 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -692,7 +692,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
- clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
/*
* some have their individual clock subtree with separate clock
* items and their individual enable counters, yet share a
diff --git a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
index 8de53a1..df92e12 100644
--- a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
+++ b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
@@ -1020,6 +1020,21 @@ static int fs_enet_probe(struct platform_device *ofdev)
fpi->cp_command = *data;
}
+ /* make clock lookup non-fatal (the driver is shared among platforms),
+ * but require enable to succeed when a clock was specified/found
+ */
+ fpi->clk_per = clk_get(&ofdev->dev, "per");
+ if (IS_ERR(fpi->clk_per))
+ fpi->clk_per = NULL;
+ if (fpi->clk_per) {
+ int err;
+ err = clk_prepare_enable(fpi->clk_per);
+ if (err) {
+ ret = err;
+ goto out_clk_put;
+ }
+ }
+
fpi->rx_ring = 32;
fpi->tx_ring = 32;
fpi->rx_copybreak = 240;
@@ -1028,7 +1043,7 @@ static int fs_enet_probe(struct platform_device *ofdev)
fpi->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0);
if ((!fpi->phy_node) && (!of_get_property(ofdev->dev.of_node, "fixed-link",
NULL)))
- goto out_free_fpi;
+ goto out_clk_dis;
if (of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc5125-fec")) {
phy_connection_type = of_get_property(ofdev->dev.of_node,
@@ -1108,6 +1123,12 @@ out_free_dev:
free_netdev(ndev);
out_put:
of_node_put(fpi->phy_node);
+out_clk_dis:
+ if (fpi->clk_per)
+ clk_disable_unprepare(fpi->clk_per);
+out_clk_put:
+ if (fpi->clk_per)
+ clk_put(fpi->clk_per);
out_free_fpi:
kfree(fpi);
return ret;
@@ -1124,6 +1145,10 @@ static int fs_enet_remove(struct platform_device *ofdev)
fep->ops->cleanup_data(ndev);
dev_set_drvdata(fep->dev, NULL);
of_node_put(fep->fpi->phy_node);
+ if (fep->fpi->clk_per) {
+ clk_disable_unprepare(fep->fpi->clk_per);
+ clk_put(fep->fpi->clk_per);
+ }
free_netdev(ndev);
return 0;
}
diff --git a/include/linux/fs_enet_pd.h b/include/linux/fs_enet_pd.h
index 51b7934..a978d0d 100644
--- a/include/linux/fs_enet_pd.h
+++ b/include/linux/fs_enet_pd.h
@@ -16,6 +16,7 @@
#ifndef FS_ENET_PD_H
#define FS_ENET_PD_H
+#include <linux/clk.h>
#include <linux/string.h>
#include <linux/of_mdio.h>
#include <asm/types.h>
@@ -142,6 +143,8 @@ struct fs_platform_info {
int use_rmii; /* use RMII mode */
int has_phy; /* if the network is phy container as well...*/
+
+ struct clk *clk_per; /* 'per' clock for register access */
};
struct fs_mii_fec_platform_info {
u32 irq[32];
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 20/24] fs_enet: OF clock lookup (non-fatal), prepare and enable
@ 2013-07-16 6:05 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 6:05 UTC (permalink / raw)
To: linux-arm-kernel
device tree based clock lookup, must prepare clocks before enabling
them, unprepare after disable, error check in the clock setup, remove
the pre-enable workaround in the MPC512x platform's clock driver
this change implements non-fatal clock lookup since not all platforms
provide device tree specs for clocks, but failure to enable a specified
clock is considered fatal
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 27 +++++++++++++++++++-
include/linux/fs_enet_pd.h | 3 +++
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 29c51a5..31d0cf3 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -692,7 +692,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
- clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
/*
* some have their individual clock subtree with separate clock
* items and their individual enable counters, yet share a
diff --git a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
index 8de53a1..df92e12 100644
--- a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
+++ b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
@@ -1020,6 +1020,21 @@ static int fs_enet_probe(struct platform_device *ofdev)
fpi->cp_command = *data;
}
+ /* make clock lookup non-fatal (the driver is shared among platforms),
+ * but require enable to succeed when a clock was specified/found
+ */
+ fpi->clk_per = clk_get(&ofdev->dev, "per");
+ if (IS_ERR(fpi->clk_per))
+ fpi->clk_per = NULL;
+ if (fpi->clk_per) {
+ int err;
+ err = clk_prepare_enable(fpi->clk_per);
+ if (err) {
+ ret = err;
+ goto out_clk_put;
+ }
+ }
+
fpi->rx_ring = 32;
fpi->tx_ring = 32;
fpi->rx_copybreak = 240;
@@ -1028,7 +1043,7 @@ static int fs_enet_probe(struct platform_device *ofdev)
fpi->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0);
if ((!fpi->phy_node) && (!of_get_property(ofdev->dev.of_node, "fixed-link",
NULL)))
- goto out_free_fpi;
+ goto out_clk_dis;
if (of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc5125-fec")) {
phy_connection_type = of_get_property(ofdev->dev.of_node,
@@ -1108,6 +1123,12 @@ out_free_dev:
free_netdev(ndev);
out_put:
of_node_put(fpi->phy_node);
+out_clk_dis:
+ if (fpi->clk_per)
+ clk_disable_unprepare(fpi->clk_per);
+out_clk_put:
+ if (fpi->clk_per)
+ clk_put(fpi->clk_per);
out_free_fpi:
kfree(fpi);
return ret;
@@ -1124,6 +1145,10 @@ static int fs_enet_remove(struct platform_device *ofdev)
fep->ops->cleanup_data(ndev);
dev_set_drvdata(fep->dev, NULL);
of_node_put(fep->fpi->phy_node);
+ if (fep->fpi->clk_per) {
+ clk_disable_unprepare(fep->fpi->clk_per);
+ clk_put(fep->fpi->clk_per);
+ }
free_netdev(ndev);
return 0;
}
diff --git a/include/linux/fs_enet_pd.h b/include/linux/fs_enet_pd.h
index 51b7934..a978d0d 100644
--- a/include/linux/fs_enet_pd.h
+++ b/include/linux/fs_enet_pd.h
@@ -16,6 +16,7 @@
#ifndef FS_ENET_PD_H
#define FS_ENET_PD_H
+#include <linux/clk.h>
#include <linux/string.h>
#include <linux/of_mdio.h>
#include <asm/types.h>
@@ -142,6 +143,8 @@ struct fs_platform_info {
int use_rmii; /* use RMII mode */
int has_phy; /* if the network is phy container as well...*/
+
+ struct clk *clk_per; /* 'per' clock for register access */
};
struct fs_mii_fec_platform_info {
u32 irq[32];
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 21/24] [media] fsl-viu: OF clock lookup, prepare before enable
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-16 8:45 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
device tree based clock lookup, must prepare clocks before enabling
them, unprepare after disable, error check in the clock setup
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
drivers/media/platform/fsl-viu.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/fsl-viu.c b/drivers/media/platform/fsl-viu.c
index 221ec42..b95aa43 100644
--- a/drivers/media/platform/fsl-viu.c
+++ b/drivers/media/platform/fsl-viu.c
@@ -1582,8 +1582,11 @@ static int viu_of_probe(struct platform_device *op)
dev_err(&op->dev, "failed to find the clock module!\n");
ret = -ENODEV;
goto err_clk;
- } else {
- clk_enable(viu_dev->clk);
+ }
+ ret = clk_prepare_enable(viu_dev->clk);
+ if (ret) {
+ dev_err(&op->dev, "failed to enable the clock!\n");
+ goto err_clk_put;
}
/* reset VIU module */
@@ -1602,7 +1605,8 @@ static int viu_of_probe(struct platform_device *op)
return ret;
err_irq:
- clk_disable(viu_dev->clk);
+ clk_disable_unprepare(viu_dev->clk);
+err_clk_put:
clk_put(viu_dev->clk);
err_clk:
video_unregister_device(viu_dev->vdev);
@@ -1626,7 +1630,7 @@ static int viu_of_remove(struct platform_device *op)
free_irq(dev->irq, (void *)dev);
irq_dispose_mapping(dev->irq);
- clk_disable(dev->clk);
+ clk_disable_unprepare(dev->clk);
clk_put(dev->clk);
video_unregister_device(dev->vdev);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 21/24] [media] fsl-viu: OF clock lookup, prepare before enable
@ 2013-07-16 8:45 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
device tree based clock lookup, must prepare clocks before enabling
them, unprepare after disable, error check in the clock setup
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/media/platform/fsl-viu.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/fsl-viu.c b/drivers/media/platform/fsl-viu.c
index 221ec42..b95aa43 100644
--- a/drivers/media/platform/fsl-viu.c
+++ b/drivers/media/platform/fsl-viu.c
@@ -1582,8 +1582,11 @@ static int viu_of_probe(struct platform_device *op)
dev_err(&op->dev, "failed to find the clock module!\n");
ret = -ENODEV;
goto err_clk;
- } else {
- clk_enable(viu_dev->clk);
+ }
+ ret = clk_prepare_enable(viu_dev->clk);
+ if (ret) {
+ dev_err(&op->dev, "failed to enable the clock!\n");
+ goto err_clk_put;
}
/* reset VIU module */
@@ -1602,7 +1605,8 @@ static int viu_of_probe(struct platform_device *op)
return ret;
err_irq:
- clk_disable(viu_dev->clk);
+ clk_disable_unprepare(viu_dev->clk);
+err_clk_put:
clk_put(viu_dev->clk);
err_clk:
video_unregister_device(viu_dev->vdev);
@@ -1626,7 +1630,7 @@ static int viu_of_remove(struct platform_device *op)
free_irq(dev->irq, (void *)dev);
irq_dispose_mapping(dev->irq);
- clk_disable(dev->clk);
+ clk_disable_unprepare(dev->clk);
clk_put(dev->clk);
video_unregister_device(dev->vdev);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 21/24] [media] fsl-viu: OF clock lookup, prepare before enable
@ 2013-07-16 8:45 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linux-arm-kernel
device tree based clock lookup, must prepare clocks before enabling
them, unprepare after disable, error check in the clock setup
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/media/platform/fsl-viu.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/fsl-viu.c b/drivers/media/platform/fsl-viu.c
index 221ec42..b95aa43 100644
--- a/drivers/media/platform/fsl-viu.c
+++ b/drivers/media/platform/fsl-viu.c
@@ -1582,8 +1582,11 @@ static int viu_of_probe(struct platform_device *op)
dev_err(&op->dev, "failed to find the clock module!\n");
ret = -ENODEV;
goto err_clk;
- } else {
- clk_enable(viu_dev->clk);
+ }
+ ret = clk_prepare_enable(viu_dev->clk);
+ if (ret) {
+ dev_err(&op->dev, "failed to enable the clock!\n");
+ goto err_clk_put;
}
/* reset VIU module */
@@ -1602,7 +1605,8 @@ static int viu_of_probe(struct platform_device *op)
return ret;
err_irq:
- clk_disable(viu_dev->clk);
+ clk_disable_unprepare(viu_dev->clk);
+err_clk_put:
clk_put(viu_dev->clk);
err_clk:
video_unregister_device(viu_dev->vdev);
@@ -1626,7 +1630,7 @@ static int viu_of_remove(struct platform_device *op)
free_irq(dev->irq, (void *)dev);
irq_dispose_mapping(dev->irq);
- clk_disable(dev->clk);
+ clk_disable_unprepare(dev->clk);
clk_put(dev->clk);
video_unregister_device(dev->vdev);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 22/24] powerpc/fsl-pci: OF clock lookup, prepare before enable
2013-07-15 18:47 ` Gerhard Sittig
@ 2013-07-16 8:45 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
device tree based clock lookup, must prepare clocks before enabling
them, error check in the clock setup
this change implements non-fatal clock lookup for compatibility with
platforms that don't provide OF clock specs, but failure to enable a
specified clock is considered fatal
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/sysdev/fsl_pci.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 46ac1dd..cb2ed92 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -17,6 +17,8 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
+
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
@@ -741,6 +743,7 @@ err0:
int __init mpc83xx_add_bridge(struct device_node *dev)
{
+ struct clk *clk;
int ret;
int len;
struct pci_controller *hose;
@@ -758,6 +761,18 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
}
pr_debug("Adding PCI host bridge %s\n", dev->full_name);
+ /* non-fatal OF clock lookup, but fatal when a clock
+ * was specified yet could not get enabled */
+ clk = of_clk_get_by_name(dev, "per");
+ if (!IS_ERR(clk)) {
+ ret = clk_prepare_enable(clk);
+ clk_put(clk);
+ if (ret) {
+ pr_err("Could not enable peripheral clock\n");
+ return ret;
+ }
+ }
+
/* Fetch host bridge registers address */
if (of_address_to_resource(dev, 0, &rsrc_reg)) {
printk(KERN_WARNING "Can't get pci register base!\n");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 22/24] powerpc/fsl-pci: OF clock lookup, prepare before enable
@ 2013-07-16 8:45 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linux-arm-kernel
device tree based clock lookup, must prepare clocks before enabling
them, error check in the clock setup
this change implements non-fatal clock lookup for compatibility with
platforms that don't provide OF clock specs, but failure to enable a
specified clock is considered fatal
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/sysdev/fsl_pci.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 46ac1dd..cb2ed92 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -17,6 +17,8 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
+
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
@@ -741,6 +743,7 @@ err0:
int __init mpc83xx_add_bridge(struct device_node *dev)
{
+ struct clk *clk;
int ret;
int len;
struct pci_controller *hose;
@@ -758,6 +761,18 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
}
pr_debug("Adding PCI host bridge %s\n", dev->full_name);
+ /* non-fatal OF clock lookup, but fatal when a clock
+ * was specified yet could not get enabled */
+ clk = of_clk_get_by_name(dev, "per");
+ if (!IS_ERR(clk)) {
+ ret = clk_prepare_enable(clk);
+ clk_put(clk);
+ if (ret) {
+ pr_err("Could not enable peripheral clock\n");
+ return ret;
+ }
+ }
+
/* Fetch host bridge registers address */
if (of_address_to_resource(dev, 0, &rsrc_reg)) {
printk(KERN_WARNING "Can't get pci register base!\n");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 23/24] clk: mpc512x: switch to COMMON_CLK, remove PPC_CLOCK
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-16 8:45 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
completely switch to, i.e. unconditionally use COMMON_CLK for the
MPC512x platform, and retire the PPC_CLOCK implementation for that
platform after the transition has completed
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
arch/powerpc/platforms/512x/Kconfig | 14 +-
arch/powerpc/platforms/512x/Makefile | 3 +-
arch/powerpc/platforms/512x/clock.c | 753 ----------------------------------
3 files changed, 2 insertions(+), 768 deletions(-)
delete mode 100644 arch/powerpc/platforms/512x/clock.c
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index c5fcdd0..5aa3f4b 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,21 +1,9 @@
-config MPC512x_COMMON_CLK
- bool "MPC512x platform uses COMMON_CLK"
- default y
- depends on PPC_MPC512x
- help
- This option is only here to support tests and comparison
- during development and migration. This option will get
- removed after the COMMON_CLK support for MPC512x has become
- fully operational and all drivers were adjusted to explicitly
- acquire their required clocks.
-
config PPC_MPC512x
bool "512x-based boards"
depends on 6xx
+ select COMMON_CLK
select FSL_SOC
select IPIC
- select PPC_CLOCK if !MPC512x_COMMON_CLK
- select COMMON_CLK if MPC512x_COMMON_CLK
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 1e05f9d..bb20116 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,8 +1,7 @@
#
# Makefile for the Freescale PowerPC 512x linux kernel.
#
-obj-$(CONFIG_PPC_CLOCK) += clock.o
-obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
+obj-y += clock-commonclk.o
obj-y += mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
deleted file mode 100644
index e504166..0000000
--- a/arch/powerpc/platforms/512x/clock.c
+++ /dev/null
@@ -1,753 +0,0 @@
-/*
- * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: John Rigby <jrigby-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
- *
- * Implements the clk api defined in include/linux/clk.h
- *
- * Original based on linux/arch/arm/mach-integrator/clock.c
- *
- * Copyright (C) 2004 ARM Limited.
- * Written by Deep Blue Solutions Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-
-#include <linux/of_platform.h>
-#include <asm/mpc5xxx.h>
-#include <asm/mpc5121.h>
-#include <asm/clk_interface.h>
-
-#include "mpc512x.h"
-
-#undef CLK_DEBUG
-
-static int clocks_initialized;
-
-#define CLK_HAS_RATE 0x1 /* has rate in MHz */
-#define CLK_HAS_CTRL 0x2 /* has control reg and bit */
-
-struct clk {
- struct list_head node;
- char name[32];
- int flags;
- struct device *dev;
- unsigned long rate;
- struct module *owner;
- void (*calc) (struct clk *);
- struct clk *parent;
- int reg, bit; /* CLK_HAS_CTRL */
- int div_shift; /* only used by generic_div_clk_calc */
-};
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
-{
- struct clk *p, *clk = ERR_PTR(-ENOENT);
- int dev_match;
- int id_match;
-
- if (dev == NULL || id == NULL)
- return clk;
-
- mutex_lock(&clocks_mutex);
- list_for_each_entry(p, &clocks, node) {
- dev_match = id_match = 0;
-
- if (dev == p->dev)
- dev_match++;
- if (strcmp(id, p->name) == 0)
- id_match++;
- if ((dev_match || id_match) && try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
- mutex_unlock(&clocks_mutex);
-
- return clk;
-}
-
-#ifdef CLK_DEBUG
-static void dump_clocks(void)
-{
- struct clk *p;
-
- mutex_lock(&clocks_mutex);
- printk(KERN_INFO "CLOCKS:\n");
- list_for_each_entry(p, &clocks, node) {
- pr_info(" %s=%ld", p->name, p->rate);
- if (p->parent)
- pr_cont(" %s=%ld", p->parent->name,
- p->parent->rate);
- if (p->flags & CLK_HAS_CTRL)
- pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
- pr_cont("\n");
- }
- mutex_unlock(&clocks_mutex);
-}
-#define DEBUG_CLK_DUMP() dump_clocks()
-#else
-#define DEBUG_CLK_DUMP()
-#endif
-
-
-static void mpc5121_clk_put(struct clk *clk)
-{
- module_put(clk->owner);
-}
-
-#define NRPSC 12
-
-struct mpc512x_clockctl {
- u32 spmr; /* System PLL Mode Reg */
- u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
- u32 scfr1; /* System Clk Freq Reg 1 */
- u32 scfr2; /* System Clk Freq Reg 2 */
- u32 reserved;
- u32 bcr; /* Bread Crumb Reg */
- u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
- u32 spccr; /* SPDIF Clk Ctrl Reg */
- u32 cccr; /* CFM Clk Ctrl Reg */
- u32 dccr; /* DIU Clk Cnfg Reg */
-};
-
-static struct mpc512x_clockctl __iomem *clockctl;
-
-static int mpc5121_clk_enable(struct clk *clk)
-{
- unsigned int mask;
-
- if (clk->flags & CLK_HAS_CTRL) {
- mask = in_be32(&clockctl->sccr[clk->reg]);
- mask |= 1 << clk->bit;
- out_be32(&clockctl->sccr[clk->reg], mask);
- }
- return 0;
-}
-
-static void mpc5121_clk_disable(struct clk *clk)
-{
- unsigned int mask;
-
- if (clk->flags & CLK_HAS_CTRL) {
- mask = in_be32(&clockctl->sccr[clk->reg]);
- mask &= ~(1 << clk->bit);
- out_be32(&clockctl->sccr[clk->reg], mask);
- }
-}
-
-static unsigned long mpc5121_clk_get_rate(struct clk *clk)
-{
- if (clk->flags & CLK_HAS_RATE)
- return clk->rate;
- else
- return 0;
-}
-
-static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return rate;
-}
-
-static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- return 0;
-}
-
-static int clk_register(struct clk *clk)
-{
- mutex_lock(&clocks_mutex);
- list_add(&clk->node, &clocks);
- mutex_unlock(&clocks_mutex);
- return 0;
-}
-
-static unsigned long spmf_mult(void)
-{
- /*
- * Convert spmf to multiplier
- */
- static int spmf_to_mult[] = {
- 68, 1, 12, 16,
- 20, 24, 28, 32,
- 36, 40, 44, 48,
- 52, 56, 60, 64
- };
- int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
- return spmf_to_mult[spmf];
-}
-
-static unsigned long sysdiv_div_x_2(void)
-{
- /*
- * Convert sysdiv to divisor x 2
- * Some divisors have fractional parts so
- * multiply by 2 then divide by this value
- */
- static int sysdiv_to_div_x_2[] = {
- 4, 5, 6, 7,
- 8, 9, 10, 14,
- 12, 16, 18, 22,
- 20, 24, 26, 30,
- 28, 32, 34, 38,
- 36, 40, 42, 46,
- 44, 48, 50, 54,
- 52, 56, 58, 62,
- 60, 64, 66,
- };
- int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
- return sysdiv_to_div_x_2[sysdiv];
-}
-
-static unsigned long ref_to_sys(unsigned long rate)
-{
- rate *= spmf_mult();
- rate *= 2;
- rate /= sysdiv_div_x_2();
-
- return rate;
-}
-
-static unsigned long sys_to_ref(unsigned long rate)
-{
- rate *= sysdiv_div_x_2();
- rate /= 2;
- rate /= spmf_mult();
-
- return rate;
-}
-
-static long ips_to_ref(unsigned long rate)
-{
- int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
-
- rate *= ips_div; /* csb_clk = ips_clk * ips_div */
- rate *= 2; /* sys_clk = csb_clk * 2 */
- return sys_to_ref(rate);
-}
-
-static unsigned long devtree_getfreq(char *clockname)
-{
- struct device_node *np;
- const unsigned int *prop;
- unsigned int val = 0;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
- if (np) {
- prop = of_get_property(np, clockname, NULL);
- if (prop)
- val = *prop;
- of_node_put(np);
- }
- return val;
-}
-
-static void ref_clk_calc(struct clk *clk)
-{
- unsigned long rate;
-
- rate = devtree_getfreq("bus-frequency");
- if (rate == 0) {
- printk(KERN_ERR "No bus-frequency in dev tree\n");
- clk->rate = 0;
- return;
- }
- clk->rate = ips_to_ref(rate);
-}
-
-static struct clk ref_clk = {
- .name = "ref_clk",
- .calc = ref_clk_calc,
-};
-
-
-static void sys_clk_calc(struct clk *clk)
-{
- clk->rate = ref_to_sys(ref_clk.rate);
-}
-
-static struct clk sys_clk = {
- .name = "sys_clk",
- .calc = sys_clk_calc,
-};
-
-static void diu_clk_calc(struct clk *clk)
-{
- int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
- unsigned long rate;
-
- rate = sys_clk.rate;
-
- rate *= 2;
- rate /= diudiv_x_2;
-
- clk->rate = rate;
-}
-
-static void viu_clk_calc(struct clk *clk)
-{
- unsigned long rate;
-
- rate = sys_clk.rate;
- rate /= 2;
- clk->rate = rate;
-}
-
-static void half_clk_calc(struct clk *clk)
-{
- clk->rate = clk->parent->rate / 2;
-}
-
-static void generic_div_clk_calc(struct clk *clk)
-{
- int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
-
- clk->rate = clk->parent->rate / div;
-}
-
-static void unity_clk_calc(struct clk *clk)
-{
- clk->rate = clk->parent->rate;
-}
-
-static struct clk csb_clk = {
- .name = "csb_clk",
- .calc = half_clk_calc,
- .parent = &sys_clk,
-};
-
-static void e300_clk_calc(struct clk *clk)
-{
- int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
- int ratex2 = clk->parent->rate * spmf;
-
- clk->rate = ratex2 / 2;
-}
-
-static struct clk e300_clk = {
- .name = "e300_clk",
- .calc = e300_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk ips_clk = {
- .name = "ips_clk",
- .calc = generic_div_clk_calc,
- .parent = &csb_clk,
- .div_shift = 23,
-};
-
-/*
- * Clocks controlled by SCCR1 (.reg = 0)
- */
-static struct clk lpc_clk = {
- .name = "lpc_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 30,
- .calc = generic_div_clk_calc,
- .parent = &ips_clk,
- .div_shift = 11,
-};
-
-static struct clk nfc_clk = {
- .name = "nfc_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 29,
- .calc = generic_div_clk_calc,
- .parent = &ips_clk,
- .div_shift = 8,
-};
-
-static struct clk pata_clk = {
- .name = "pata_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 28,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-/*
- * PSC clocks (bits 27 - 16)
- * are setup elsewhere
- */
-
-static struct clk sata_clk = {
- .name = "sata_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 14,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk fec_clk = {
- .name = "fec_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 13,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk pci_clk = {
- .name = "pci_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 11,
- .calc = generic_div_clk_calc,
- .parent = &csb_clk,
- .div_shift = 20,
-};
-
-/*
- * Clocks controlled by SCCR2 (.reg = 1)
- */
-static struct clk diu_clk = {
- .name = "diu_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 31,
- .calc = diu_clk_calc,
-};
-
-static struct clk viu_clk = {
- .name = "viu_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 18,
- .calc = viu_clk_calc,
-};
-
-static struct clk axe_clk = {
- .name = "axe_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 30,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk usb1_clk = {
- .name = "usb1_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 28,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk usb2_clk = {
- .name = "usb2_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 27,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk i2c_clk = {
- .name = "i2c_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 26,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk mscan_clk = {
- .name = "mscan_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 25,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk sdhc_clk = {
- .name = "sdhc_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 24,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk mbx_bus_clk = {
- .name = "mbx_bus_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 22,
- .calc = half_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk mbx_clk = {
- .name = "mbx_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 21,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk mbx_3d_clk = {
- .name = "mbx_3d_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 20,
- .calc = generic_div_clk_calc,
- .parent = &mbx_bus_clk,
- .div_shift = 14,
-};
-
-static void psc_mclk_in_calc(struct clk *clk)
-{
- clk->rate = devtree_getfreq("psc_mclk_in");
- if (!clk->rate)
- clk->rate = 25000000;
-}
-
-static struct clk psc_mclk_in = {
- .name = "psc_mclk_in",
- .calc = psc_mclk_in_calc,
-};
-
-static struct clk spdif_txclk = {
- .name = "spdif_txclk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 23,
-};
-
-static struct clk spdif_rxclk = {
- .name = "spdif_rxclk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 23,
-};
-
-static void ac97_clk_calc(struct clk *clk)
-{
- /* ac97 bit clock is always 24.567 MHz */
- clk->rate = 24567000;
-}
-
-static struct clk ac97_clk = {
- .name = "ac97_clk_in",
- .calc = ac97_clk_calc,
-};
-
-static struct clk *rate_clks[] = {
- &ref_clk,
- &sys_clk,
- &diu_clk,
- &viu_clk,
- &csb_clk,
- &e300_clk,
- &ips_clk,
- &fec_clk,
- &sata_clk,
- &pata_clk,
- &nfc_clk,
- &lpc_clk,
- &mbx_bus_clk,
- &mbx_clk,
- &mbx_3d_clk,
- &axe_clk,
- &usb1_clk,
- &usb2_clk,
- &i2c_clk,
- &mscan_clk,
- &sdhc_clk,
- &pci_clk,
- &psc_mclk_in,
- &spdif_txclk,
- &spdif_rxclk,
- &ac97_clk,
- NULL
-};
-
-static void rate_clk_init(struct clk *clk)
-{
- if (clk->calc) {
- clk->calc(clk);
- clk->flags |= CLK_HAS_RATE;
- clk_register(clk);
- } else {
- printk(KERN_WARNING
- "Could not initialize clk %s without a calc routine\n",
- clk->name);
- }
-}
-
-static void rate_clks_init(void)
-{
- struct clk **cpp, *clk;
-
- cpp = rate_clks;
- while ((clk = *cpp++))
- rate_clk_init(clk);
-}
-
-/*
- * There are two clk enable registers with 32 enable bits each
- * psc clocks and device clocks are all stored in dev_clks
- */
-static struct clk dev_clks[2][32];
-
-/*
- * Given a psc number return the dev_clk
- * associated with it
- */
-static struct clk *psc_dev_clk(int pscnum)
-{
- int reg, bit;
- struct clk *clk;
-
- reg = 0;
- bit = 27 - pscnum;
-
- clk = &dev_clks[reg][bit];
- clk->reg = 0;
- clk->bit = bit;
- return clk;
-}
-
-/*
- * PSC clock rate calculation
- */
-static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
-{
- unsigned long mclk_src = sys_clk.rate;
- unsigned long mclk_div;
-
- /*
- * Can only change value of mclk divider
- * when the divider is disabled.
- *
- * Zero is not a valid divider so minimum
- * divider is 1
- *
- * disable/set divider/enable
- */
- out_be32(&clockctl->pccr[pscnum], 0);
- out_be32(&clockctl->pccr[pscnum], 0x00020000);
- out_be32(&clockctl->pccr[pscnum], 0x00030000);
-
- if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
- clk->rate = spdif_rxclk.rate;
- return;
- }
-
- switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
- case 0:
- mclk_src = sys_clk.rate;
- break;
- case 1:
- mclk_src = ref_clk.rate;
- break;
- case 2:
- mclk_src = psc_mclk_in.rate;
- break;
- case 3:
- mclk_src = spdif_txclk.rate;
- break;
- }
-
- mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
- clk->rate = mclk_src / mclk_div;
-}
-
-/*
- * Find all psc nodes in device tree and assign a clock
- * with name "psc%d_mclk" and dev pointing at the device
- * returned from of_find_device_by_node
- */
-static void psc_clks_init(void)
-{
- struct device_node *np;
- struct platform_device *ofdev;
- u32 reg;
- const char *psc_compat;
-
- psc_compat = mpc512x_select_psc_compat();
- if (!psc_compat)
- return;
-
- for_each_compatible_node(np, NULL, psc_compat) {
- if (!of_property_read_u32(np, "reg", ®)) {
- int pscnum = (reg & 0xf00) >> 8;
- struct clk *clk = psc_dev_clk(pscnum);
-
- clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
- ofdev = of_find_device_by_node(np);
- clk->dev = &ofdev->dev;
- /*
- * AC97 is special rate clock does
- * not go through normal path
- */
- if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
- clk->rate = ac97_clk.rate;
- else
- psc_calc_rate(clk, pscnum, np);
- sprintf(clk->name, "psc%d_mclk", pscnum);
- clk_register(clk);
- clk_enable(clk);
- }
- }
-}
-
-static struct clk_interface mpc5121_clk_functions = {
- .clk_get = mpc5121_clk_get,
- .clk_enable = mpc5121_clk_enable,
- .clk_disable = mpc5121_clk_disable,
- .clk_get_rate = mpc5121_clk_get_rate,
- .clk_put = mpc5121_clk_put,
- .clk_round_rate = mpc5121_clk_round_rate,
- .clk_set_rate = mpc5121_clk_set_rate,
- .clk_set_parent = NULL,
- .clk_get_parent = NULL,
-};
-
-int __init mpc5121_clk_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
- if (np) {
- clockctl = of_iomap(np, 0);
- of_node_put(np);
- }
-
- if (!clockctl) {
- printk(KERN_ERR "Could not map clock control registers\n");
- return 0;
- }
-
- rate_clks_init();
- psc_clks_init();
-
- /* leave clockctl mapped forever */
- /*iounmap(clockctl); */
- DEBUG_CLK_DUMP();
- clocks_initialized++;
- clk_functions = mpc5121_clk_functions;
- return 0;
-}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 23/24] clk: mpc512x: switch to COMMON_CLK, remove PPC_CLOCK
@ 2013-07-16 8:45 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
completely switch to, i.e. unconditionally use COMMON_CLK for the
MPC512x platform, and retire the PPC_CLOCK implementation for that
platform after the transition has completed
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/Kconfig | 14 +-
arch/powerpc/platforms/512x/Makefile | 3 +-
arch/powerpc/platforms/512x/clock.c | 753 ----------------------------------
3 files changed, 2 insertions(+), 768 deletions(-)
delete mode 100644 arch/powerpc/platforms/512x/clock.c
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index c5fcdd0..5aa3f4b 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,21 +1,9 @@
-config MPC512x_COMMON_CLK
- bool "MPC512x platform uses COMMON_CLK"
- default y
- depends on PPC_MPC512x
- help
- This option is only here to support tests and comparison
- during development and migration. This option will get
- removed after the COMMON_CLK support for MPC512x has become
- fully operational and all drivers were adjusted to explicitly
- acquire their required clocks.
-
config PPC_MPC512x
bool "512x-based boards"
depends on 6xx
+ select COMMON_CLK
select FSL_SOC
select IPIC
- select PPC_CLOCK if !MPC512x_COMMON_CLK
- select COMMON_CLK if MPC512x_COMMON_CLK
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 1e05f9d..bb20116 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,8 +1,7 @@
#
# Makefile for the Freescale PowerPC 512x linux kernel.
#
-obj-$(CONFIG_PPC_CLOCK) += clock.o
-obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
+obj-y += clock-commonclk.o
obj-y += mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
deleted file mode 100644
index e504166..0000000
--- a/arch/powerpc/platforms/512x/clock.c
+++ /dev/null
@@ -1,753 +0,0 @@
-/*
- * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: John Rigby <jrigby@freescale.com>
- *
- * Implements the clk api defined in include/linux/clk.h
- *
- * Original based on linux/arch/arm/mach-integrator/clock.c
- *
- * Copyright (C) 2004 ARM Limited.
- * Written by Deep Blue Solutions Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-
-#include <linux/of_platform.h>
-#include <asm/mpc5xxx.h>
-#include <asm/mpc5121.h>
-#include <asm/clk_interface.h>
-
-#include "mpc512x.h"
-
-#undef CLK_DEBUG
-
-static int clocks_initialized;
-
-#define CLK_HAS_RATE 0x1 /* has rate in MHz */
-#define CLK_HAS_CTRL 0x2 /* has control reg and bit */
-
-struct clk {
- struct list_head node;
- char name[32];
- int flags;
- struct device *dev;
- unsigned long rate;
- struct module *owner;
- void (*calc) (struct clk *);
- struct clk *parent;
- int reg, bit; /* CLK_HAS_CTRL */
- int div_shift; /* only used by generic_div_clk_calc */
-};
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
-{
- struct clk *p, *clk = ERR_PTR(-ENOENT);
- int dev_match;
- int id_match;
-
- if (dev == NULL || id == NULL)
- return clk;
-
- mutex_lock(&clocks_mutex);
- list_for_each_entry(p, &clocks, node) {
- dev_match = id_match = 0;
-
- if (dev == p->dev)
- dev_match++;
- if (strcmp(id, p->name) == 0)
- id_match++;
- if ((dev_match || id_match) && try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
- mutex_unlock(&clocks_mutex);
-
- return clk;
-}
-
-#ifdef CLK_DEBUG
-static void dump_clocks(void)
-{
- struct clk *p;
-
- mutex_lock(&clocks_mutex);
- printk(KERN_INFO "CLOCKS:\n");
- list_for_each_entry(p, &clocks, node) {
- pr_info(" %s=%ld", p->name, p->rate);
- if (p->parent)
- pr_cont(" %s=%ld", p->parent->name,
- p->parent->rate);
- if (p->flags & CLK_HAS_CTRL)
- pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
- pr_cont("\n");
- }
- mutex_unlock(&clocks_mutex);
-}
-#define DEBUG_CLK_DUMP() dump_clocks()
-#else
-#define DEBUG_CLK_DUMP()
-#endif
-
-
-static void mpc5121_clk_put(struct clk *clk)
-{
- module_put(clk->owner);
-}
-
-#define NRPSC 12
-
-struct mpc512x_clockctl {
- u32 spmr; /* System PLL Mode Reg */
- u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
- u32 scfr1; /* System Clk Freq Reg 1 */
- u32 scfr2; /* System Clk Freq Reg 2 */
- u32 reserved;
- u32 bcr; /* Bread Crumb Reg */
- u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
- u32 spccr; /* SPDIF Clk Ctrl Reg */
- u32 cccr; /* CFM Clk Ctrl Reg */
- u32 dccr; /* DIU Clk Cnfg Reg */
-};
-
-static struct mpc512x_clockctl __iomem *clockctl;
-
-static int mpc5121_clk_enable(struct clk *clk)
-{
- unsigned int mask;
-
- if (clk->flags & CLK_HAS_CTRL) {
- mask = in_be32(&clockctl->sccr[clk->reg]);
- mask |= 1 << clk->bit;
- out_be32(&clockctl->sccr[clk->reg], mask);
- }
- return 0;
-}
-
-static void mpc5121_clk_disable(struct clk *clk)
-{
- unsigned int mask;
-
- if (clk->flags & CLK_HAS_CTRL) {
- mask = in_be32(&clockctl->sccr[clk->reg]);
- mask &= ~(1 << clk->bit);
- out_be32(&clockctl->sccr[clk->reg], mask);
- }
-}
-
-static unsigned long mpc5121_clk_get_rate(struct clk *clk)
-{
- if (clk->flags & CLK_HAS_RATE)
- return clk->rate;
- else
- return 0;
-}
-
-static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return rate;
-}
-
-static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- return 0;
-}
-
-static int clk_register(struct clk *clk)
-{
- mutex_lock(&clocks_mutex);
- list_add(&clk->node, &clocks);
- mutex_unlock(&clocks_mutex);
- return 0;
-}
-
-static unsigned long spmf_mult(void)
-{
- /*
- * Convert spmf to multiplier
- */
- static int spmf_to_mult[] = {
- 68, 1, 12, 16,
- 20, 24, 28, 32,
- 36, 40, 44, 48,
- 52, 56, 60, 64
- };
- int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
- return spmf_to_mult[spmf];
-}
-
-static unsigned long sysdiv_div_x_2(void)
-{
- /*
- * Convert sysdiv to divisor x 2
- * Some divisors have fractional parts so
- * multiply by 2 then divide by this value
- */
- static int sysdiv_to_div_x_2[] = {
- 4, 5, 6, 7,
- 8, 9, 10, 14,
- 12, 16, 18, 22,
- 20, 24, 26, 30,
- 28, 32, 34, 38,
- 36, 40, 42, 46,
- 44, 48, 50, 54,
- 52, 56, 58, 62,
- 60, 64, 66,
- };
- int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
- return sysdiv_to_div_x_2[sysdiv];
-}
-
-static unsigned long ref_to_sys(unsigned long rate)
-{
- rate *= spmf_mult();
- rate *= 2;
- rate /= sysdiv_div_x_2();
-
- return rate;
-}
-
-static unsigned long sys_to_ref(unsigned long rate)
-{
- rate *= sysdiv_div_x_2();
- rate /= 2;
- rate /= spmf_mult();
-
- return rate;
-}
-
-static long ips_to_ref(unsigned long rate)
-{
- int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
-
- rate *= ips_div; /* csb_clk = ips_clk * ips_div */
- rate *= 2; /* sys_clk = csb_clk * 2 */
- return sys_to_ref(rate);
-}
-
-static unsigned long devtree_getfreq(char *clockname)
-{
- struct device_node *np;
- const unsigned int *prop;
- unsigned int val = 0;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
- if (np) {
- prop = of_get_property(np, clockname, NULL);
- if (prop)
- val = *prop;
- of_node_put(np);
- }
- return val;
-}
-
-static void ref_clk_calc(struct clk *clk)
-{
- unsigned long rate;
-
- rate = devtree_getfreq("bus-frequency");
- if (rate == 0) {
- printk(KERN_ERR "No bus-frequency in dev tree\n");
- clk->rate = 0;
- return;
- }
- clk->rate = ips_to_ref(rate);
-}
-
-static struct clk ref_clk = {
- .name = "ref_clk",
- .calc = ref_clk_calc,
-};
-
-
-static void sys_clk_calc(struct clk *clk)
-{
- clk->rate = ref_to_sys(ref_clk.rate);
-}
-
-static struct clk sys_clk = {
- .name = "sys_clk",
- .calc = sys_clk_calc,
-};
-
-static void diu_clk_calc(struct clk *clk)
-{
- int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
- unsigned long rate;
-
- rate = sys_clk.rate;
-
- rate *= 2;
- rate /= diudiv_x_2;
-
- clk->rate = rate;
-}
-
-static void viu_clk_calc(struct clk *clk)
-{
- unsigned long rate;
-
- rate = sys_clk.rate;
- rate /= 2;
- clk->rate = rate;
-}
-
-static void half_clk_calc(struct clk *clk)
-{
- clk->rate = clk->parent->rate / 2;
-}
-
-static void generic_div_clk_calc(struct clk *clk)
-{
- int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
-
- clk->rate = clk->parent->rate / div;
-}
-
-static void unity_clk_calc(struct clk *clk)
-{
- clk->rate = clk->parent->rate;
-}
-
-static struct clk csb_clk = {
- .name = "csb_clk",
- .calc = half_clk_calc,
- .parent = &sys_clk,
-};
-
-static void e300_clk_calc(struct clk *clk)
-{
- int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
- int ratex2 = clk->parent->rate * spmf;
-
- clk->rate = ratex2 / 2;
-}
-
-static struct clk e300_clk = {
- .name = "e300_clk",
- .calc = e300_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk ips_clk = {
- .name = "ips_clk",
- .calc = generic_div_clk_calc,
- .parent = &csb_clk,
- .div_shift = 23,
-};
-
-/*
- * Clocks controlled by SCCR1 (.reg = 0)
- */
-static struct clk lpc_clk = {
- .name = "lpc_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 30,
- .calc = generic_div_clk_calc,
- .parent = &ips_clk,
- .div_shift = 11,
-};
-
-static struct clk nfc_clk = {
- .name = "nfc_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 29,
- .calc = generic_div_clk_calc,
- .parent = &ips_clk,
- .div_shift = 8,
-};
-
-static struct clk pata_clk = {
- .name = "pata_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 28,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-/*
- * PSC clocks (bits 27 - 16)
- * are setup elsewhere
- */
-
-static struct clk sata_clk = {
- .name = "sata_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 14,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk fec_clk = {
- .name = "fec_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 13,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk pci_clk = {
- .name = "pci_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 11,
- .calc = generic_div_clk_calc,
- .parent = &csb_clk,
- .div_shift = 20,
-};
-
-/*
- * Clocks controlled by SCCR2 (.reg = 1)
- */
-static struct clk diu_clk = {
- .name = "diu_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 31,
- .calc = diu_clk_calc,
-};
-
-static struct clk viu_clk = {
- .name = "viu_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 18,
- .calc = viu_clk_calc,
-};
-
-static struct clk axe_clk = {
- .name = "axe_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 30,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk usb1_clk = {
- .name = "usb1_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 28,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk usb2_clk = {
- .name = "usb2_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 27,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk i2c_clk = {
- .name = "i2c_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 26,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk mscan_clk = {
- .name = "mscan_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 25,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk sdhc_clk = {
- .name = "sdhc_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 24,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk mbx_bus_clk = {
- .name = "mbx_bus_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 22,
- .calc = half_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk mbx_clk = {
- .name = "mbx_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 21,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk mbx_3d_clk = {
- .name = "mbx_3d_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 20,
- .calc = generic_div_clk_calc,
- .parent = &mbx_bus_clk,
- .div_shift = 14,
-};
-
-static void psc_mclk_in_calc(struct clk *clk)
-{
- clk->rate = devtree_getfreq("psc_mclk_in");
- if (!clk->rate)
- clk->rate = 25000000;
-}
-
-static struct clk psc_mclk_in = {
- .name = "psc_mclk_in",
- .calc = psc_mclk_in_calc,
-};
-
-static struct clk spdif_txclk = {
- .name = "spdif_txclk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 23,
-};
-
-static struct clk spdif_rxclk = {
- .name = "spdif_rxclk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 23,
-};
-
-static void ac97_clk_calc(struct clk *clk)
-{
- /* ac97 bit clock is always 24.567 MHz */
- clk->rate = 24567000;
-}
-
-static struct clk ac97_clk = {
- .name = "ac97_clk_in",
- .calc = ac97_clk_calc,
-};
-
-static struct clk *rate_clks[] = {
- &ref_clk,
- &sys_clk,
- &diu_clk,
- &viu_clk,
- &csb_clk,
- &e300_clk,
- &ips_clk,
- &fec_clk,
- &sata_clk,
- &pata_clk,
- &nfc_clk,
- &lpc_clk,
- &mbx_bus_clk,
- &mbx_clk,
- &mbx_3d_clk,
- &axe_clk,
- &usb1_clk,
- &usb2_clk,
- &i2c_clk,
- &mscan_clk,
- &sdhc_clk,
- &pci_clk,
- &psc_mclk_in,
- &spdif_txclk,
- &spdif_rxclk,
- &ac97_clk,
- NULL
-};
-
-static void rate_clk_init(struct clk *clk)
-{
- if (clk->calc) {
- clk->calc(clk);
- clk->flags |= CLK_HAS_RATE;
- clk_register(clk);
- } else {
- printk(KERN_WARNING
- "Could not initialize clk %s without a calc routine\n",
- clk->name);
- }
-}
-
-static void rate_clks_init(void)
-{
- struct clk **cpp, *clk;
-
- cpp = rate_clks;
- while ((clk = *cpp++))
- rate_clk_init(clk);
-}
-
-/*
- * There are two clk enable registers with 32 enable bits each
- * psc clocks and device clocks are all stored in dev_clks
- */
-static struct clk dev_clks[2][32];
-
-/*
- * Given a psc number return the dev_clk
- * associated with it
- */
-static struct clk *psc_dev_clk(int pscnum)
-{
- int reg, bit;
- struct clk *clk;
-
- reg = 0;
- bit = 27 - pscnum;
-
- clk = &dev_clks[reg][bit];
- clk->reg = 0;
- clk->bit = bit;
- return clk;
-}
-
-/*
- * PSC clock rate calculation
- */
-static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
-{
- unsigned long mclk_src = sys_clk.rate;
- unsigned long mclk_div;
-
- /*
- * Can only change value of mclk divider
- * when the divider is disabled.
- *
- * Zero is not a valid divider so minimum
- * divider is 1
- *
- * disable/set divider/enable
- */
- out_be32(&clockctl->pccr[pscnum], 0);
- out_be32(&clockctl->pccr[pscnum], 0x00020000);
- out_be32(&clockctl->pccr[pscnum], 0x00030000);
-
- if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
- clk->rate = spdif_rxclk.rate;
- return;
- }
-
- switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
- case 0:
- mclk_src = sys_clk.rate;
- break;
- case 1:
- mclk_src = ref_clk.rate;
- break;
- case 2:
- mclk_src = psc_mclk_in.rate;
- break;
- case 3:
- mclk_src = spdif_txclk.rate;
- break;
- }
-
- mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
- clk->rate = mclk_src / mclk_div;
-}
-
-/*
- * Find all psc nodes in device tree and assign a clock
- * with name "psc%d_mclk" and dev pointing at the device
- * returned from of_find_device_by_node
- */
-static void psc_clks_init(void)
-{
- struct device_node *np;
- struct platform_device *ofdev;
- u32 reg;
- const char *psc_compat;
-
- psc_compat = mpc512x_select_psc_compat();
- if (!psc_compat)
- return;
-
- for_each_compatible_node(np, NULL, psc_compat) {
- if (!of_property_read_u32(np, "reg", ®)) {
- int pscnum = (reg & 0xf00) >> 8;
- struct clk *clk = psc_dev_clk(pscnum);
-
- clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
- ofdev = of_find_device_by_node(np);
- clk->dev = &ofdev->dev;
- /*
- * AC97 is special rate clock does
- * not go through normal path
- */
- if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
- clk->rate = ac97_clk.rate;
- else
- psc_calc_rate(clk, pscnum, np);
- sprintf(clk->name, "psc%d_mclk", pscnum);
- clk_register(clk);
- clk_enable(clk);
- }
- }
-}
-
-static struct clk_interface mpc5121_clk_functions = {
- .clk_get = mpc5121_clk_get,
- .clk_enable = mpc5121_clk_enable,
- .clk_disable = mpc5121_clk_disable,
- .clk_get_rate = mpc5121_clk_get_rate,
- .clk_put = mpc5121_clk_put,
- .clk_round_rate = mpc5121_clk_round_rate,
- .clk_set_rate = mpc5121_clk_set_rate,
- .clk_set_parent = NULL,
- .clk_get_parent = NULL,
-};
-
-int __init mpc5121_clk_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
- if (np) {
- clockctl = of_iomap(np, 0);
- of_node_put(np);
- }
-
- if (!clockctl) {
- printk(KERN_ERR "Could not map clock control registers\n");
- return 0;
- }
-
- rate_clks_init();
- psc_clks_init();
-
- /* leave clockctl mapped forever */
- /*iounmap(clockctl); */
- DEBUG_CLK_DUMP();
- clocks_initialized++;
- clk_functions = mpc5121_clk_functions;
- return 0;
-}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 23/24] clk: mpc512x: switch to COMMON_CLK, remove PPC_CLOCK
@ 2013-07-16 8:45 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linux-arm-kernel
completely switch to, i.e. unconditionally use COMMON_CLK for the
MPC512x platform, and retire the PPC_CLOCK implementation for that
platform after the transition has completed
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/Kconfig | 14 +-
arch/powerpc/platforms/512x/Makefile | 3 +-
arch/powerpc/platforms/512x/clock.c | 753 ----------------------------------
3 files changed, 2 insertions(+), 768 deletions(-)
delete mode 100644 arch/powerpc/platforms/512x/clock.c
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index c5fcdd0..5aa3f4b 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,21 +1,9 @@
-config MPC512x_COMMON_CLK
- bool "MPC512x platform uses COMMON_CLK"
- default y
- depends on PPC_MPC512x
- help
- This option is only here to support tests and comparison
- during development and migration. This option will get
- removed after the COMMON_CLK support for MPC512x has become
- fully operational and all drivers were adjusted to explicitly
- acquire their required clocks.
-
config PPC_MPC512x
bool "512x-based boards"
depends on 6xx
+ select COMMON_CLK
select FSL_SOC
select IPIC
- select PPC_CLOCK if !MPC512x_COMMON_CLK
- select COMMON_CLK if MPC512x_COMMON_CLK
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 1e05f9d..bb20116 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,8 +1,7 @@
#
# Makefile for the Freescale PowerPC 512x linux kernel.
#
-obj-$(CONFIG_PPC_CLOCK) += clock.o
-obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
+obj-y += clock-commonclk.o
obj-y += mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
deleted file mode 100644
index e504166..0000000
--- a/arch/powerpc/platforms/512x/clock.c
+++ /dev/null
@@ -1,753 +0,0 @@
-/*
- * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: John Rigby <jrigby@freescale.com>
- *
- * Implements the clk api defined in include/linux/clk.h
- *
- * Original based on linux/arch/arm/mach-integrator/clock.c
- *
- * Copyright (C) 2004 ARM Limited.
- * Written by Deep Blue Solutions Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-
-#include <linux/of_platform.h>
-#include <asm/mpc5xxx.h>
-#include <asm/mpc5121.h>
-#include <asm/clk_interface.h>
-
-#include "mpc512x.h"
-
-#undef CLK_DEBUG
-
-static int clocks_initialized;
-
-#define CLK_HAS_RATE 0x1 /* has rate in MHz */
-#define CLK_HAS_CTRL 0x2 /* has control reg and bit */
-
-struct clk {
- struct list_head node;
- char name[32];
- int flags;
- struct device *dev;
- unsigned long rate;
- struct module *owner;
- void (*calc) (struct clk *);
- struct clk *parent;
- int reg, bit; /* CLK_HAS_CTRL */
- int div_shift; /* only used by generic_div_clk_calc */
-};
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
-{
- struct clk *p, *clk = ERR_PTR(-ENOENT);
- int dev_match;
- int id_match;
-
- if (dev == NULL || id == NULL)
- return clk;
-
- mutex_lock(&clocks_mutex);
- list_for_each_entry(p, &clocks, node) {
- dev_match = id_match = 0;
-
- if (dev == p->dev)
- dev_match++;
- if (strcmp(id, p->name) == 0)
- id_match++;
- if ((dev_match || id_match) && try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
- mutex_unlock(&clocks_mutex);
-
- return clk;
-}
-
-#ifdef CLK_DEBUG
-static void dump_clocks(void)
-{
- struct clk *p;
-
- mutex_lock(&clocks_mutex);
- printk(KERN_INFO "CLOCKS:\n");
- list_for_each_entry(p, &clocks, node) {
- pr_info(" %s=%ld", p->name, p->rate);
- if (p->parent)
- pr_cont(" %s=%ld", p->parent->name,
- p->parent->rate);
- if (p->flags & CLK_HAS_CTRL)
- pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
- pr_cont("\n");
- }
- mutex_unlock(&clocks_mutex);
-}
-#define DEBUG_CLK_DUMP() dump_clocks()
-#else
-#define DEBUG_CLK_DUMP()
-#endif
-
-
-static void mpc5121_clk_put(struct clk *clk)
-{
- module_put(clk->owner);
-}
-
-#define NRPSC 12
-
-struct mpc512x_clockctl {
- u32 spmr; /* System PLL Mode Reg */
- u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
- u32 scfr1; /* System Clk Freq Reg 1 */
- u32 scfr2; /* System Clk Freq Reg 2 */
- u32 reserved;
- u32 bcr; /* Bread Crumb Reg */
- u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
- u32 spccr; /* SPDIF Clk Ctrl Reg */
- u32 cccr; /* CFM Clk Ctrl Reg */
- u32 dccr; /* DIU Clk Cnfg Reg */
-};
-
-static struct mpc512x_clockctl __iomem *clockctl;
-
-static int mpc5121_clk_enable(struct clk *clk)
-{
- unsigned int mask;
-
- if (clk->flags & CLK_HAS_CTRL) {
- mask = in_be32(&clockctl->sccr[clk->reg]);
- mask |= 1 << clk->bit;
- out_be32(&clockctl->sccr[clk->reg], mask);
- }
- return 0;
-}
-
-static void mpc5121_clk_disable(struct clk *clk)
-{
- unsigned int mask;
-
- if (clk->flags & CLK_HAS_CTRL) {
- mask = in_be32(&clockctl->sccr[clk->reg]);
- mask &= ~(1 << clk->bit);
- out_be32(&clockctl->sccr[clk->reg], mask);
- }
-}
-
-static unsigned long mpc5121_clk_get_rate(struct clk *clk)
-{
- if (clk->flags & CLK_HAS_RATE)
- return clk->rate;
- else
- return 0;
-}
-
-static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return rate;
-}
-
-static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- return 0;
-}
-
-static int clk_register(struct clk *clk)
-{
- mutex_lock(&clocks_mutex);
- list_add(&clk->node, &clocks);
- mutex_unlock(&clocks_mutex);
- return 0;
-}
-
-static unsigned long spmf_mult(void)
-{
- /*
- * Convert spmf to multiplier
- */
- static int spmf_to_mult[] = {
- 68, 1, 12, 16,
- 20, 24, 28, 32,
- 36, 40, 44, 48,
- 52, 56, 60, 64
- };
- int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
- return spmf_to_mult[spmf];
-}
-
-static unsigned long sysdiv_div_x_2(void)
-{
- /*
- * Convert sysdiv to divisor x 2
- * Some divisors have fractional parts so
- * multiply by 2 then divide by this value
- */
- static int sysdiv_to_div_x_2[] = {
- 4, 5, 6, 7,
- 8, 9, 10, 14,
- 12, 16, 18, 22,
- 20, 24, 26, 30,
- 28, 32, 34, 38,
- 36, 40, 42, 46,
- 44, 48, 50, 54,
- 52, 56, 58, 62,
- 60, 64, 66,
- };
- int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
- return sysdiv_to_div_x_2[sysdiv];
-}
-
-static unsigned long ref_to_sys(unsigned long rate)
-{
- rate *= spmf_mult();
- rate *= 2;
- rate /= sysdiv_div_x_2();
-
- return rate;
-}
-
-static unsigned long sys_to_ref(unsigned long rate)
-{
- rate *= sysdiv_div_x_2();
- rate /= 2;
- rate /= spmf_mult();
-
- return rate;
-}
-
-static long ips_to_ref(unsigned long rate)
-{
- int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
-
- rate *= ips_div; /* csb_clk = ips_clk * ips_div */
- rate *= 2; /* sys_clk = csb_clk * 2 */
- return sys_to_ref(rate);
-}
-
-static unsigned long devtree_getfreq(char *clockname)
-{
- struct device_node *np;
- const unsigned int *prop;
- unsigned int val = 0;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
- if (np) {
- prop = of_get_property(np, clockname, NULL);
- if (prop)
- val = *prop;
- of_node_put(np);
- }
- return val;
-}
-
-static void ref_clk_calc(struct clk *clk)
-{
- unsigned long rate;
-
- rate = devtree_getfreq("bus-frequency");
- if (rate == 0) {
- printk(KERN_ERR "No bus-frequency in dev tree\n");
- clk->rate = 0;
- return;
- }
- clk->rate = ips_to_ref(rate);
-}
-
-static struct clk ref_clk = {
- .name = "ref_clk",
- .calc = ref_clk_calc,
-};
-
-
-static void sys_clk_calc(struct clk *clk)
-{
- clk->rate = ref_to_sys(ref_clk.rate);
-}
-
-static struct clk sys_clk = {
- .name = "sys_clk",
- .calc = sys_clk_calc,
-};
-
-static void diu_clk_calc(struct clk *clk)
-{
- int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
- unsigned long rate;
-
- rate = sys_clk.rate;
-
- rate *= 2;
- rate /= diudiv_x_2;
-
- clk->rate = rate;
-}
-
-static void viu_clk_calc(struct clk *clk)
-{
- unsigned long rate;
-
- rate = sys_clk.rate;
- rate /= 2;
- clk->rate = rate;
-}
-
-static void half_clk_calc(struct clk *clk)
-{
- clk->rate = clk->parent->rate / 2;
-}
-
-static void generic_div_clk_calc(struct clk *clk)
-{
- int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
-
- clk->rate = clk->parent->rate / div;
-}
-
-static void unity_clk_calc(struct clk *clk)
-{
- clk->rate = clk->parent->rate;
-}
-
-static struct clk csb_clk = {
- .name = "csb_clk",
- .calc = half_clk_calc,
- .parent = &sys_clk,
-};
-
-static void e300_clk_calc(struct clk *clk)
-{
- int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
- int ratex2 = clk->parent->rate * spmf;
-
- clk->rate = ratex2 / 2;
-}
-
-static struct clk e300_clk = {
- .name = "e300_clk",
- .calc = e300_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk ips_clk = {
- .name = "ips_clk",
- .calc = generic_div_clk_calc,
- .parent = &csb_clk,
- .div_shift = 23,
-};
-
-/*
- * Clocks controlled by SCCR1 (.reg = 0)
- */
-static struct clk lpc_clk = {
- .name = "lpc_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 30,
- .calc = generic_div_clk_calc,
- .parent = &ips_clk,
- .div_shift = 11,
-};
-
-static struct clk nfc_clk = {
- .name = "nfc_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 29,
- .calc = generic_div_clk_calc,
- .parent = &ips_clk,
- .div_shift = 8,
-};
-
-static struct clk pata_clk = {
- .name = "pata_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 28,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-/*
- * PSC clocks (bits 27 - 16)
- * are setup elsewhere
- */
-
-static struct clk sata_clk = {
- .name = "sata_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 14,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk fec_clk = {
- .name = "fec_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 13,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk pci_clk = {
- .name = "pci_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 0,
- .bit = 11,
- .calc = generic_div_clk_calc,
- .parent = &csb_clk,
- .div_shift = 20,
-};
-
-/*
- * Clocks controlled by SCCR2 (.reg = 1)
- */
-static struct clk diu_clk = {
- .name = "diu_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 31,
- .calc = diu_clk_calc,
-};
-
-static struct clk viu_clk = {
- .name = "viu_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 18,
- .calc = viu_clk_calc,
-};
-
-static struct clk axe_clk = {
- .name = "axe_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 30,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk usb1_clk = {
- .name = "usb1_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 28,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk usb2_clk = {
- .name = "usb2_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 27,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk i2c_clk = {
- .name = "i2c_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 26,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk mscan_clk = {
- .name = "mscan_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 25,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk sdhc_clk = {
- .name = "sdhc_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 24,
- .calc = unity_clk_calc,
- .parent = &ips_clk,
-};
-
-static struct clk mbx_bus_clk = {
- .name = "mbx_bus_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 22,
- .calc = half_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk mbx_clk = {
- .name = "mbx_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 21,
- .calc = unity_clk_calc,
- .parent = &csb_clk,
-};
-
-static struct clk mbx_3d_clk = {
- .name = "mbx_3d_clk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 20,
- .calc = generic_div_clk_calc,
- .parent = &mbx_bus_clk,
- .div_shift = 14,
-};
-
-static void psc_mclk_in_calc(struct clk *clk)
-{
- clk->rate = devtree_getfreq("psc_mclk_in");
- if (!clk->rate)
- clk->rate = 25000000;
-}
-
-static struct clk psc_mclk_in = {
- .name = "psc_mclk_in",
- .calc = psc_mclk_in_calc,
-};
-
-static struct clk spdif_txclk = {
- .name = "spdif_txclk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 23,
-};
-
-static struct clk spdif_rxclk = {
- .name = "spdif_rxclk",
- .flags = CLK_HAS_CTRL,
- .reg = 1,
- .bit = 23,
-};
-
-static void ac97_clk_calc(struct clk *clk)
-{
- /* ac97 bit clock is always 24.567 MHz */
- clk->rate = 24567000;
-}
-
-static struct clk ac97_clk = {
- .name = "ac97_clk_in",
- .calc = ac97_clk_calc,
-};
-
-static struct clk *rate_clks[] = {
- &ref_clk,
- &sys_clk,
- &diu_clk,
- &viu_clk,
- &csb_clk,
- &e300_clk,
- &ips_clk,
- &fec_clk,
- &sata_clk,
- &pata_clk,
- &nfc_clk,
- &lpc_clk,
- &mbx_bus_clk,
- &mbx_clk,
- &mbx_3d_clk,
- &axe_clk,
- &usb1_clk,
- &usb2_clk,
- &i2c_clk,
- &mscan_clk,
- &sdhc_clk,
- &pci_clk,
- &psc_mclk_in,
- &spdif_txclk,
- &spdif_rxclk,
- &ac97_clk,
- NULL
-};
-
-static void rate_clk_init(struct clk *clk)
-{
- if (clk->calc) {
- clk->calc(clk);
- clk->flags |= CLK_HAS_RATE;
- clk_register(clk);
- } else {
- printk(KERN_WARNING
- "Could not initialize clk %s without a calc routine\n",
- clk->name);
- }
-}
-
-static void rate_clks_init(void)
-{
- struct clk **cpp, *clk;
-
- cpp = rate_clks;
- while ((clk = *cpp++))
- rate_clk_init(clk);
-}
-
-/*
- * There are two clk enable registers with 32 enable bits each
- * psc clocks and device clocks are all stored in dev_clks
- */
-static struct clk dev_clks[2][32];
-
-/*
- * Given a psc number return the dev_clk
- * associated with it
- */
-static struct clk *psc_dev_clk(int pscnum)
-{
- int reg, bit;
- struct clk *clk;
-
- reg = 0;
- bit = 27 - pscnum;
-
- clk = &dev_clks[reg][bit];
- clk->reg = 0;
- clk->bit = bit;
- return clk;
-}
-
-/*
- * PSC clock rate calculation
- */
-static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
-{
- unsigned long mclk_src = sys_clk.rate;
- unsigned long mclk_div;
-
- /*
- * Can only change value of mclk divider
- * when the divider is disabled.
- *
- * Zero is not a valid divider so minimum
- * divider is 1
- *
- * disable/set divider/enable
- */
- out_be32(&clockctl->pccr[pscnum], 0);
- out_be32(&clockctl->pccr[pscnum], 0x00020000);
- out_be32(&clockctl->pccr[pscnum], 0x00030000);
-
- if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
- clk->rate = spdif_rxclk.rate;
- return;
- }
-
- switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
- case 0:
- mclk_src = sys_clk.rate;
- break;
- case 1:
- mclk_src = ref_clk.rate;
- break;
- case 2:
- mclk_src = psc_mclk_in.rate;
- break;
- case 3:
- mclk_src = spdif_txclk.rate;
- break;
- }
-
- mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
- clk->rate = mclk_src / mclk_div;
-}
-
-/*
- * Find all psc nodes in device tree and assign a clock
- * with name "psc%d_mclk" and dev pointing at the device
- * returned from of_find_device_by_node
- */
-static void psc_clks_init(void)
-{
- struct device_node *np;
- struct platform_device *ofdev;
- u32 reg;
- const char *psc_compat;
-
- psc_compat = mpc512x_select_psc_compat();
- if (!psc_compat)
- return;
-
- for_each_compatible_node(np, NULL, psc_compat) {
- if (!of_property_read_u32(np, "reg", ®)) {
- int pscnum = (reg & 0xf00) >> 8;
- struct clk *clk = psc_dev_clk(pscnum);
-
- clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
- ofdev = of_find_device_by_node(np);
- clk->dev = &ofdev->dev;
- /*
- * AC97 is special rate clock does
- * not go through normal path
- */
- if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
- clk->rate = ac97_clk.rate;
- else
- psc_calc_rate(clk, pscnum, np);
- sprintf(clk->name, "psc%d_mclk", pscnum);
- clk_register(clk);
- clk_enable(clk);
- }
- }
-}
-
-static struct clk_interface mpc5121_clk_functions = {
- .clk_get = mpc5121_clk_get,
- .clk_enable = mpc5121_clk_enable,
- .clk_disable = mpc5121_clk_disable,
- .clk_get_rate = mpc5121_clk_get_rate,
- .clk_put = mpc5121_clk_put,
- .clk_round_rate = mpc5121_clk_round_rate,
- .clk_set_rate = mpc5121_clk_set_rate,
- .clk_set_parent = NULL,
- .clk_get_parent = NULL,
-};
-
-int __init mpc5121_clk_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
- if (np) {
- clockctl = of_iomap(np, 0);
- of_node_put(np);
- }
-
- if (!clockctl) {
- printk(KERN_ERR "Could not map clock control registers\n");
- return 0;
- }
-
- rate_clks_init();
- psc_clks_init();
-
- /* leave clockctl mapped forever */
- /*iounmap(clockctl); */
- DEBUG_CLK_DUMP();
- clocks_initialized++;
- clk_functions = mpc5121_clk_functions;
- return 0;
-}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 24/24] net: can: mscan: remove MPC512x non-COMMON_CLK code path
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-16 8:45 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
transition to the COMMON_CLK framework has completed for the MPC512x
platform, remove the now obsolete code path of the mpc5xxx mscan
driver which accessed clock control module registers directly
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 136 -----------------------------------
1 file changed, 136 deletions(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index dd26ab6..cf5e4cfc 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -108,9 +108,6 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
#endif /* CONFIG_PPC_MPC52xx */
#ifdef CONFIG_PPC_MPC512x
-
-#if IS_ENABLED(CONFIG_COMMON_CLK)
-
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_source, int *mscan_clksrc)
{
@@ -244,139 +241,6 @@ err_notavail:
dev_err(&ofdev->dev, "cannot acquire or setup clock source\n");
return 0;
}
-#else /* COMMON_CLK */
-struct mpc512x_clockctl {
- u32 spmr; /* System PLL Mode Reg */
- u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
- u32 scfr1; /* System Clk Freq Reg 1 */
- u32 scfr2; /* System Clk Freq Reg 2 */
- u32 reserved;
- u32 bcr; /* Bread Crumb Reg */
- u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */
- u32 spccr; /* SPDIF Clk Ctrl Reg */
- u32 cccr; /* CFM Clk Ctrl Reg */
- u32 dccr; /* DIU Clk Cnfg Reg */
- u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */
-};
-
-static struct of_device_id mpc512x_clock_ids[] = {
- { .compatible = "fsl,mpc5121-clock", },
- {}
-};
-
-static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
- const char *clock_name, int *mscan_clksrc)
-{
- struct mpc512x_clockctl __iomem *clockctl;
- struct device_node *np_clock;
- struct clk *sys_clk, *ref_clk;
- int plen, clockidx, clocksrc = -1;
- u32 sys_freq, val, clockdiv = 1, freq = 0;
- const u32 *pval;
-
- np_clock = of_find_matching_node(NULL, mpc512x_clock_ids);
- if (!np_clock) {
- dev_err(&ofdev->dev, "couldn't find clock node\n");
- return 0;
- }
- clockctl = of_iomap(np_clock, 0);
- if (!clockctl) {
- dev_err(&ofdev->dev, "couldn't map clock registers\n");
- goto exit_put;
- }
-
- /* Determine the MSCAN device index from the peripheral's
- * physical address. Register address offsets against the
- * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
- */
- pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
- BUG_ON(!pval || plen < sizeof(*pval));
- clockidx = (*pval & 0x80) ? 1 : 0;
- if (*pval & 0x2000)
- clockidx += 2;
-
- /*
- * Clock source and divider selection: 3 different clock sources
- * can be selected: "ip", "ref" or "sys". For the latter two, a
- * clock divider can be defined as well. If the clock source is
- * not specified by the device tree, we first try to find an
- * optimal CAN source clock based on the system clock. If that
- * is not posslible, the reference clock will be used.
- */
- if (clock_name && !strcmp(clock_name, "ip")) {
- *mscan_clksrc = MSCAN_CLKSRC_IPS;
- freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
- } else {
- *mscan_clksrc = MSCAN_CLKSRC_BUS;
-
- pval = of_get_property(ofdev->dev.of_node,
- "fsl,mscan-clock-divider", &plen);
- if (pval && plen == sizeof(*pval))
- clockdiv = *pval;
- if (!clockdiv)
- clockdiv = 1;
-
- if (!clock_name || !strcmp(clock_name, "sys")) {
- sys_clk = clk_get(&ofdev->dev, "sys_clk");
- if (IS_ERR(sys_clk)) {
- dev_err(&ofdev->dev, "couldn't get sys_clk\n");
- goto exit_unmap;
- }
- /* Get and round up/down sys clock rate */
- sys_freq = 1000000 *
- ((clk_get_rate(sys_clk) + 499999) / 1000000);
-
- if (!clock_name) {
- /* A multiple of 16 MHz would be optimal */
- if ((sys_freq % 16000000) == 0) {
- clocksrc = 0;
- clockdiv = sys_freq / 16000000;
- freq = sys_freq / clockdiv;
- }
- } else {
- clocksrc = 0;
- freq = sys_freq / clockdiv;
- }
- }
-
- if (clocksrc < 0) {
- ref_clk = clk_get(&ofdev->dev, "ref_clk");
- if (IS_ERR(ref_clk)) {
- dev_err(&ofdev->dev, "couldn't get ref_clk\n");
- goto exit_unmap;
- }
- clocksrc = 1;
- freq = clk_get_rate(ref_clk) / clockdiv;
- }
- }
-
- /* Disable clock */
- out_be32(&clockctl->mccr[clockidx], 0x0);
- if (clocksrc >= 0) {
- /* Set source and divider */
- val = (clocksrc << 14) | ((clockdiv - 1) << 17);
- out_be32(&clockctl->mccr[clockidx], val);
- /* Enable clock */
- out_be32(&clockctl->mccr[clockidx], val | 0x10000);
- }
-
- /* Enable MSCAN clock domain */
- val = in_be32(&clockctl->sccr[1]);
- if (!(val & (1 << 25)))
- out_be32(&clockctl->sccr[1], val | (1 << 25));
-
- dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n",
- *mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" :
- clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv);
-
-exit_unmap:
- iounmap(clockctl);
-exit_put:
- of_node_put(np_clock);
- return freq;
-}
-#endif /* COMMON_CLK */
-
#else /* !CONFIG_PPC_MPC512x */
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_name, int *mscan_clksrc)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 24/24] net: can: mscan: remove MPC512x non-COMMON_CLK code path
@ 2013-07-16 8:45 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
transition to the COMMON_CLK framework has completed for the MPC512x
platform, remove the now obsolete code path of the mpc5xxx mscan
driver which accessed clock control module registers directly
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 136 -----------------------------------
1 file changed, 136 deletions(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index dd26ab6..cf5e4cfc 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -108,9 +108,6 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
#endif /* CONFIG_PPC_MPC52xx */
#ifdef CONFIG_PPC_MPC512x
-
-#if IS_ENABLED(CONFIG_COMMON_CLK)
-
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_source, int *mscan_clksrc)
{
@@ -244,139 +241,6 @@ err_notavail:
dev_err(&ofdev->dev, "cannot acquire or setup clock source\n");
return 0;
}
-#else /* COMMON_CLK */
-struct mpc512x_clockctl {
- u32 spmr; /* System PLL Mode Reg */
- u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
- u32 scfr1; /* System Clk Freq Reg 1 */
- u32 scfr2; /* System Clk Freq Reg 2 */
- u32 reserved;
- u32 bcr; /* Bread Crumb Reg */
- u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */
- u32 spccr; /* SPDIF Clk Ctrl Reg */
- u32 cccr; /* CFM Clk Ctrl Reg */
- u32 dccr; /* DIU Clk Cnfg Reg */
- u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */
-};
-
-static struct of_device_id mpc512x_clock_ids[] = {
- { .compatible = "fsl,mpc5121-clock", },
- {}
-};
-
-static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
- const char *clock_name, int *mscan_clksrc)
-{
- struct mpc512x_clockctl __iomem *clockctl;
- struct device_node *np_clock;
- struct clk *sys_clk, *ref_clk;
- int plen, clockidx, clocksrc = -1;
- u32 sys_freq, val, clockdiv = 1, freq = 0;
- const u32 *pval;
-
- np_clock = of_find_matching_node(NULL, mpc512x_clock_ids);
- if (!np_clock) {
- dev_err(&ofdev->dev, "couldn't find clock node\n");
- return 0;
- }
- clockctl = of_iomap(np_clock, 0);
- if (!clockctl) {
- dev_err(&ofdev->dev, "couldn't map clock registers\n");
- goto exit_put;
- }
-
- /* Determine the MSCAN device index from the peripheral's
- * physical address. Register address offsets against the
- * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
- */
- pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
- BUG_ON(!pval || plen < sizeof(*pval));
- clockidx = (*pval & 0x80) ? 1 : 0;
- if (*pval & 0x2000)
- clockidx += 2;
-
- /*
- * Clock source and divider selection: 3 different clock sources
- * can be selected: "ip", "ref" or "sys". For the latter two, a
- * clock divider can be defined as well. If the clock source is
- * not specified by the device tree, we first try to find an
- * optimal CAN source clock based on the system clock. If that
- * is not posslible, the reference clock will be used.
- */
- if (clock_name && !strcmp(clock_name, "ip")) {
- *mscan_clksrc = MSCAN_CLKSRC_IPS;
- freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
- } else {
- *mscan_clksrc = MSCAN_CLKSRC_BUS;
-
- pval = of_get_property(ofdev->dev.of_node,
- "fsl,mscan-clock-divider", &plen);
- if (pval && plen == sizeof(*pval))
- clockdiv = *pval;
- if (!clockdiv)
- clockdiv = 1;
-
- if (!clock_name || !strcmp(clock_name, "sys")) {
- sys_clk = clk_get(&ofdev->dev, "sys_clk");
- if (IS_ERR(sys_clk)) {
- dev_err(&ofdev->dev, "couldn't get sys_clk\n");
- goto exit_unmap;
- }
- /* Get and round up/down sys clock rate */
- sys_freq = 1000000 *
- ((clk_get_rate(sys_clk) + 499999) / 1000000);
-
- if (!clock_name) {
- /* A multiple of 16 MHz would be optimal */
- if ((sys_freq % 16000000) == 0) {
- clocksrc = 0;
- clockdiv = sys_freq / 16000000;
- freq = sys_freq / clockdiv;
- }
- } else {
- clocksrc = 0;
- freq = sys_freq / clockdiv;
- }
- }
-
- if (clocksrc < 0) {
- ref_clk = clk_get(&ofdev->dev, "ref_clk");
- if (IS_ERR(ref_clk)) {
- dev_err(&ofdev->dev, "couldn't get ref_clk\n");
- goto exit_unmap;
- }
- clocksrc = 1;
- freq = clk_get_rate(ref_clk) / clockdiv;
- }
- }
-
- /* Disable clock */
- out_be32(&clockctl->mccr[clockidx], 0x0);
- if (clocksrc >= 0) {
- /* Set source and divider */
- val = (clocksrc << 14) | ((clockdiv - 1) << 17);
- out_be32(&clockctl->mccr[clockidx], val);
- /* Enable clock */
- out_be32(&clockctl->mccr[clockidx], val | 0x10000);
- }
-
- /* Enable MSCAN clock domain */
- val = in_be32(&clockctl->sccr[1]);
- if (!(val & (1 << 25)))
- out_be32(&clockctl->sccr[1], val | (1 << 25));
-
- dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n",
- *mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" :
- clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv);
-
-exit_unmap:
- iounmap(clockctl);
-exit_put:
- of_node_put(np_clock);
- return freq;
-}
-#endif /* COMMON_CLK */
-
#else /* !CONFIG_PPC_MPC512x */
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_name, int *mscan_clksrc)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v1 24/24] net: can: mscan: remove MPC512x non-COMMON_CLK code path
@ 2013-07-16 8:45 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-16 8:45 UTC (permalink / raw)
To: linux-arm-kernel
transition to the COMMON_CLK framework has completed for the MPC512x
platform, remove the now obsolete code path of the mpc5xxx mscan
driver which accessed clock control module registers directly
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 136 -----------------------------------
1 file changed, 136 deletions(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index dd26ab6..cf5e4cfc 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -108,9 +108,6 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
#endif /* CONFIG_PPC_MPC52xx */
#ifdef CONFIG_PPC_MPC512x
-
-#if IS_ENABLED(CONFIG_COMMON_CLK)
-
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_source, int *mscan_clksrc)
{
@@ -244,139 +241,6 @@ err_notavail:
dev_err(&ofdev->dev, "cannot acquire or setup clock source\n");
return 0;
}
-#else /* COMMON_CLK */
-struct mpc512x_clockctl {
- u32 spmr; /* System PLL Mode Reg */
- u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
- u32 scfr1; /* System Clk Freq Reg 1 */
- u32 scfr2; /* System Clk Freq Reg 2 */
- u32 reserved;
- u32 bcr; /* Bread Crumb Reg */
- u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */
- u32 spccr; /* SPDIF Clk Ctrl Reg */
- u32 cccr; /* CFM Clk Ctrl Reg */
- u32 dccr; /* DIU Clk Cnfg Reg */
- u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */
-};
-
-static struct of_device_id mpc512x_clock_ids[] = {
- { .compatible = "fsl,mpc5121-clock", },
- {}
-};
-
-static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
- const char *clock_name, int *mscan_clksrc)
-{
- struct mpc512x_clockctl __iomem *clockctl;
- struct device_node *np_clock;
- struct clk *sys_clk, *ref_clk;
- int plen, clockidx, clocksrc = -1;
- u32 sys_freq, val, clockdiv = 1, freq = 0;
- const u32 *pval;
-
- np_clock = of_find_matching_node(NULL, mpc512x_clock_ids);
- if (!np_clock) {
- dev_err(&ofdev->dev, "couldn't find clock node\n");
- return 0;
- }
- clockctl = of_iomap(np_clock, 0);
- if (!clockctl) {
- dev_err(&ofdev->dev, "couldn't map clock registers\n");
- goto exit_put;
- }
-
- /* Determine the MSCAN device index from the peripheral's
- * physical address. Register address offsets against the
- * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
- */
- pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
- BUG_ON(!pval || plen < sizeof(*pval));
- clockidx = (*pval & 0x80) ? 1 : 0;
- if (*pval & 0x2000)
- clockidx += 2;
-
- /*
- * Clock source and divider selection: 3 different clock sources
- * can be selected: "ip", "ref" or "sys". For the latter two, a
- * clock divider can be defined as well. If the clock source is
- * not specified by the device tree, we first try to find an
- * optimal CAN source clock based on the system clock. If that
- * is not posslible, the reference clock will be used.
- */
- if (clock_name && !strcmp(clock_name, "ip")) {
- *mscan_clksrc = MSCAN_CLKSRC_IPS;
- freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
- } else {
- *mscan_clksrc = MSCAN_CLKSRC_BUS;
-
- pval = of_get_property(ofdev->dev.of_node,
- "fsl,mscan-clock-divider", &plen);
- if (pval && plen == sizeof(*pval))
- clockdiv = *pval;
- if (!clockdiv)
- clockdiv = 1;
-
- if (!clock_name || !strcmp(clock_name, "sys")) {
- sys_clk = clk_get(&ofdev->dev, "sys_clk");
- if (IS_ERR(sys_clk)) {
- dev_err(&ofdev->dev, "couldn't get sys_clk\n");
- goto exit_unmap;
- }
- /* Get and round up/down sys clock rate */
- sys_freq = 1000000 *
- ((clk_get_rate(sys_clk) + 499999) / 1000000);
-
- if (!clock_name) {
- /* A multiple of 16 MHz would be optimal */
- if ((sys_freq % 16000000) == 0) {
- clocksrc = 0;
- clockdiv = sys_freq / 16000000;
- freq = sys_freq / clockdiv;
- }
- } else {
- clocksrc = 0;
- freq = sys_freq / clockdiv;
- }
- }
-
- if (clocksrc < 0) {
- ref_clk = clk_get(&ofdev->dev, "ref_clk");
- if (IS_ERR(ref_clk)) {
- dev_err(&ofdev->dev, "couldn't get ref_clk\n");
- goto exit_unmap;
- }
- clocksrc = 1;
- freq = clk_get_rate(ref_clk) / clockdiv;
- }
- }
-
- /* Disable clock */
- out_be32(&clockctl->mccr[clockidx], 0x0);
- if (clocksrc >= 0) {
- /* Set source and divider */
- val = (clocksrc << 14) | ((clockdiv - 1) << 17);
- out_be32(&clockctl->mccr[clockidx], val);
- /* Enable clock */
- out_be32(&clockctl->mccr[clockidx], val | 0x10000);
- }
-
- /* Enable MSCAN clock domain */
- val = in_be32(&clockctl->sccr[1]);
- if (!(val & (1 << 25)))
- out_be32(&clockctl->sccr[1], val | (1 << 25));
-
- dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n",
- *mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" :
- clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv);
-
-exit_unmap:
- iounmap(clockctl);
-exit_put:
- of_node_put(np_clock);
- return freq;
-}
-#endif /* COMMON_CLK */
-
#else /* !CONFIG_PPC_MPC512x */
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_name, int *mscan_clksrc)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
2013-07-15 20:17 ` Mark Brown
(?)
@ 2013-07-17 11:22 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 11:22 UTC (permalink / raw)
To: Mark Brown
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring,
Marc Kleine-Budde,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
On Mon, Jul 15, 2013 at 21:17 +0100, Mark Brown wrote:
>
> On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
> > clocks need to get prepared before they can get enabled,
> > fix the MPC512x PSC SPI master's initialization
>
> > Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
> > ---
> > drivers/spi/spi-mpc512x-psc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
> > index 29fce6a..76b20ea 100644
> > --- a/drivers/spi/spi-mpc512x-psc.c
> > +++ b/drivers/spi/spi-mpc512x-psc.c
> > @@ -395,7 +395,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
> >
> > sprintf(name, "psc%d_mclk", master->bus_num);
> > spiclk = clk_get(&master->dev, name);
> > - clk_enable(spiclk);
> > + clk_prepare_enable(spiclk);
> > mps->mclk = clk_get_rate(spiclk);
> > clk_put(spiclk);
>
> This code is *clearly* buggy and should be fixed rather than papered
> over. Not only is there no matching put the driver is also dropping the
> reference to the clock rather than holding on to it while it's in use.
"This code" refers to the driver's original condition, right? I
agree that the driver has been suffering from incomplete clock
handling since it was born three years ago. And that this issue
shall get addressed. The question is just whether it needs to be
part of this series which has a different focus.
What the above patch addresses is prevention of an immediate and
fatal breakage, when common clock gets used but clocks aren't
prepared before getting enabled. So I consider it appropriate as
a step in preparation before introducing support for common clock
on the platform. (It's funny that I had a comment in this spirit
in the commit message, but trimmed it to not be overly verbose.)
What the patch does not address is to fix any other deficiencies
in the driver which might have been lurking there for ages. This
would be the scope of a different patch or series, as addressing
it here as well would mix orthogonal issues within one series,
and would complicate review and test (and would delay or even
potentially kill the introduction of desirable support for common
infrastructure just because other legacy non-fatal issues aren't
addressed as well in bypassing).
I will look into what I can do to address your concerns about
proper general clock handling in this specific driver. But I'm
unable to do this for all other drivers as well which I happen to
pass by as I work on platform code (partially due to lack of
knowledge). In any case I won't be able to test all of these
changes in all subsystems (mostly due to lack of hardware and
test setups).
So I suggest to leave these general cleanup activities for a
separate series. The current series certainly improves general
platform code, transparently brings new drivers into successful
operation, and keeps the quality of existing code (doesn't break
anything, does even actively prevent breakage). So it shall be
acceptable despite its not being perfect (like addressing each
and every other aspect which may arise elsewhere). Where would I
stop then?
Sorry for the lengthy reply, but I guess it's about just one
general aspect which equally applies to other parts of the
series, not just the specific SPI driver which the feedback was
provided for. And I do appreciate your looking at the
submission.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office-ynQEQJNshbs@public.gmane.org
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-17 11:22 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 11:22 UTC (permalink / raw)
To: Mark Brown
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss, linuxppc-dev, Rob Herring, Marc Kleine-Budde,
linux-arm-kernel, Anatolij Gustschin, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
On Mon, Jul 15, 2013 at 21:17 +0100, Mark Brown wrote:
>
> On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
> > clocks need to get prepared before they can get enabled,
> > fix the MPC512x PSC SPI master's initialization
>
> > Signed-off-by: Gerhard Sittig <gsi@denx.de>
> > ---
> > drivers/spi/spi-mpc512x-psc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
> > index 29fce6a..76b20ea 100644
> > --- a/drivers/spi/spi-mpc512x-psc.c
> > +++ b/drivers/spi/spi-mpc512x-psc.c
> > @@ -395,7 +395,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
> >
> > sprintf(name, "psc%d_mclk", master->bus_num);
> > spiclk = clk_get(&master->dev, name);
> > - clk_enable(spiclk);
> > + clk_prepare_enable(spiclk);
> > mps->mclk = clk_get_rate(spiclk);
> > clk_put(spiclk);
>
> This code is *clearly* buggy and should be fixed rather than papered
> over. Not only is there no matching put the driver is also dropping the
> reference to the clock rather than holding on to it while it's in use.
"This code" refers to the driver's original condition, right? I
agree that the driver has been suffering from incomplete clock
handling since it was born three years ago. And that this issue
shall get addressed. The question is just whether it needs to be
part of this series which has a different focus.
What the above patch addresses is prevention of an immediate and
fatal breakage, when common clock gets used but clocks aren't
prepared before getting enabled. So I consider it appropriate as
a step in preparation before introducing support for common clock
on the platform. (It's funny that I had a comment in this spirit
in the commit message, but trimmed it to not be overly verbose.)
What the patch does not address is to fix any other deficiencies
in the driver which might have been lurking there for ages. This
would be the scope of a different patch or series, as addressing
it here as well would mix orthogonal issues within one series,
and would complicate review and test (and would delay or even
potentially kill the introduction of desirable support for common
infrastructure just because other legacy non-fatal issues aren't
addressed as well in bypassing).
I will look into what I can do to address your concerns about
proper general clock handling in this specific driver. But I'm
unable to do this for all other drivers as well which I happen to
pass by as I work on platform code (partially due to lack of
knowledge). In any case I won't be able to test all of these
changes in all subsystems (mostly due to lack of hardware and
test setups).
So I suggest to leave these general cleanup activities for a
separate series. The current series certainly improves general
platform code, transparently brings new drivers into successful
operation, and keeps the quality of existing code (doesn't break
anything, does even actively prevent breakage). So it shall be
acceptable despite its not being perfect (like addressing each
and every other aspect which may arise elsewhere). Where would I
stop then?
Sorry for the lengthy reply, but I guess it's about just one
general aspect which equally applies to other parts of the
series, not just the specific SPI driver which the feedback was
provided for. And I do appreciate your looking at the
submission.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-17 11:22 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 11:22 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 15, 2013 at 21:17 +0100, Mark Brown wrote:
>
> On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
> > clocks need to get prepared before they can get enabled,
> > fix the MPC512x PSC SPI master's initialization
>
> > Signed-off-by: Gerhard Sittig <gsi@denx.de>
> > ---
> > drivers/spi/spi-mpc512x-psc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
> > index 29fce6a..76b20ea 100644
> > --- a/drivers/spi/spi-mpc512x-psc.c
> > +++ b/drivers/spi/spi-mpc512x-psc.c
> > @@ -395,7 +395,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
> >
> > sprintf(name, "psc%d_mclk", master->bus_num);
> > spiclk = clk_get(&master->dev, name);
> > - clk_enable(spiclk);
> > + clk_prepare_enable(spiclk);
> > mps->mclk = clk_get_rate(spiclk);
> > clk_put(spiclk);
>
> This code is *clearly* buggy and should be fixed rather than papered
> over. Not only is there no matching put the driver is also dropping the
> reference to the clock rather than holding on to it while it's in use.
"This code" refers to the driver's original condition, right? I
agree that the driver has been suffering from incomplete clock
handling since it was born three years ago. And that this issue
shall get addressed. The question is just whether it needs to be
part of this series which has a different focus.
What the above patch addresses is prevention of an immediate and
fatal breakage, when common clock gets used but clocks aren't
prepared before getting enabled. So I consider it appropriate as
a step in preparation before introducing support for common clock
on the platform. (It's funny that I had a comment in this spirit
in the commit message, but trimmed it to not be overly verbose.)
What the patch does not address is to fix any other deficiencies
in the driver which might have been lurking there for ages. This
would be the scope of a different patch or series, as addressing
it here as well would mix orthogonal issues within one series,
and would complicate review and test (and would delay or even
potentially kill the introduction of desirable support for common
infrastructure just because other legacy non-fatal issues aren't
addressed as well in bypassing).
I will look into what I can do to address your concerns about
proper general clock handling in this specific driver. But I'm
unable to do this for all other drivers as well which I happen to
pass by as I work on platform code (partially due to lack of
knowledge). In any case I won't be able to test all of these
changes in all subsystems (mostly due to lack of hardware and
test setups).
So I suggest to leave these general cleanup activities for a
separate series. The current series certainly improves general
platform code, transparently brings new drivers into successful
operation, and keeps the quality of existing code (doesn't break
anything, does even actively prevent breakage). So it shall be
acceptable despite its not being perfect (like addressing each
and every other aspect which may arise elsewhere). Where would I
stop then?
Sorry for the lengthy reply, but I guess it's about just one
general aspect which equally applies to other parts of the
series, not just the specific SPI driver which the feedback was
provided for. And I do appreciate your looking at the
submission.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 15/24] serial: mpc512x: OF clock lookup, use the 'mclk' name
2013-07-15 21:54 ` Sascha Hauer
(?)
@ 2013-07-17 11:27 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 11:27 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring,
Mark Brown, Marc Kleine-Budde, Wolfgang Grandegger,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, David Woodhouse,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Mauro Carvalho Chehab
On Mon, Jul 15, 2013 at 23:54 +0200, Sascha Hauer wrote:
>
> On Mon, Jul 15, 2013 at 11:46:01PM +0200, Gerhard Sittig wrote:
> > with device tree based clock lookup, the MCLK name no longer
> > depends on the PSC index
> >
> > Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
> > ---
> > drivers/tty/serial/mpc52xx_uart.c | 8 ++------
> > 1 file changed, 2 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
> > index 53c1093..221fb89 100644
> > --- a/drivers/tty/serial/mpc52xx_uart.c
> > +++ b/drivers/tty/serial/mpc52xx_uart.c
> > @@ -619,21 +619,17 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
> > static int mpc512x_psc_clock(struct uart_port *port, int enable)
> > {
> > struct clk *psc_clk;
> > - int psc_num;
> > - char clk_name[10];
> >
> > if (uart_console(port))
> > return 0;
> >
> > - psc_num = (port->mapbase & 0xf00) >> 8;
> > - snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
> > - psc_clk = clk_get(port->dev, clk_name);
> > + psc_clk = clk_get(port->dev, "mclk");
>
> Same comment applies here as Mark made to the spi driver.
So I'd like to respond in the same way as I did for the SPI
driver. :)
The scope of this series is the introduction of support for the
common clock framework. Addressing other (legacy non-fatal and
previously accepted) issues as they get identified in bypassing
would be the scope of a separate patch or series.
I'm not questioning the need to fix other additionally identified
issues. I'm just asking whether they shall be in the scope of
this very series.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office-ynQEQJNshbs@public.gmane.org
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 15/24] serial: mpc512x: OF clock lookup, use the 'mclk' name
@ 2013-07-17 11:27 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 11:27 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss, Rob Herring, Mark Brown, Marc Kleine-Budde,
Wolfgang Grandegger, Anatolij Gustschin, linuxppc-dev,
David Woodhouse, linux-arm-kernel, Mauro Carvalho Chehab
On Mon, Jul 15, 2013 at 23:54 +0200, Sascha Hauer wrote:
>
> On Mon, Jul 15, 2013 at 11:46:01PM +0200, Gerhard Sittig wrote:
> > with device tree based clock lookup, the MCLK name no longer
> > depends on the PSC index
> >
> > Signed-off-by: Gerhard Sittig <gsi@denx.de>
> > ---
> > drivers/tty/serial/mpc52xx_uart.c | 8 ++------
> > 1 file changed, 2 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
> > index 53c1093..221fb89 100644
> > --- a/drivers/tty/serial/mpc52xx_uart.c
> > +++ b/drivers/tty/serial/mpc52xx_uart.c
> > @@ -619,21 +619,17 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
> > static int mpc512x_psc_clock(struct uart_port *port, int enable)
> > {
> > struct clk *psc_clk;
> > - int psc_num;
> > - char clk_name[10];
> >
> > if (uart_console(port))
> > return 0;
> >
> > - psc_num = (port->mapbase & 0xf00) >> 8;
> > - snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
> > - psc_clk = clk_get(port->dev, clk_name);
> > + psc_clk = clk_get(port->dev, "mclk");
>
> Same comment applies here as Mark made to the spi driver.
So I'd like to respond in the same way as I did for the SPI
driver. :)
The scope of this series is the introduction of support for the
common clock framework. Addressing other (legacy non-fatal and
previously accepted) issues as they get identified in bypassing
would be the scope of a separate patch or series.
I'm not questioning the need to fix other additionally identified
issues. I'm just asking whether they shall be in the scope of
this very series.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 15/24] serial: mpc512x: OF clock lookup, use the 'mclk' name
@ 2013-07-17 11:27 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 11:27 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 15, 2013 at 23:54 +0200, Sascha Hauer wrote:
>
> On Mon, Jul 15, 2013 at 11:46:01PM +0200, Gerhard Sittig wrote:
> > with device tree based clock lookup, the MCLK name no longer
> > depends on the PSC index
> >
> > Signed-off-by: Gerhard Sittig <gsi@denx.de>
> > ---
> > drivers/tty/serial/mpc52xx_uart.c | 8 ++------
> > 1 file changed, 2 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
> > index 53c1093..221fb89 100644
> > --- a/drivers/tty/serial/mpc52xx_uart.c
> > +++ b/drivers/tty/serial/mpc52xx_uart.c
> > @@ -619,21 +619,17 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
> > static int mpc512x_psc_clock(struct uart_port *port, int enable)
> > {
> > struct clk *psc_clk;
> > - int psc_num;
> > - char clk_name[10];
> >
> > if (uart_console(port))
> > return 0;
> >
> > - psc_num = (port->mapbase & 0xf00) >> 8;
> > - snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
> > - psc_clk = clk_get(port->dev, clk_name);
> > + psc_clk = clk_get(port->dev, "mclk");
>
> Same comment applies here as Mark made to the spi driver.
So I'd like to respond in the same way as I did for the SPI
driver. :)
The scope of this series is the introduction of support for the
common clock framework. Addressing other (legacy non-fatal and
previously accepted) issues as they get identified in bypassing
would be the scope of a separate patch or series.
I'm not questioning the need to fix other additionally identified
issues. I'm just asking whether they shall be in the scope of
this very series.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
2013-07-15 19:38 ` Sascha Hauer
@ 2013-07-17 12:07 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 12:07 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss, Rob Herring, Mark Brown, Marc Kleine-Budde,
Wolfgang Grandegger, Anatolij Gustschin, linuxppc-dev,
David Woodhouse, linux-arm-kernel, Mauro Carvalho Chehab
On Mon, Jul 15, 2013 at 21:38 +0200, Sascha Hauer wrote:
>
> On Mon, Jul 15, 2013 at 08:47:34PM +0200, Gerhard Sittig wrote:
> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > index 6d55eb2..2c07061 100644
> > --- a/drivers/clk/clk-divider.c
> > +++ b/drivers/clk/clk-divider.c
> > @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> > struct clk_divider *divider = to_clk_divider(hw);
> > unsigned int div, val;
> >
> > - val = readl(divider->reg) >> divider->shift;
> > + val = clk_readl(divider->reg) >> divider->shift;
> > val &= div_mask(divider);
>
> Would it be an option to use regmap for the generic dividers/muxes
> instead? This should be suitable for ppc and also for people who want to
> use the generic clocks on i2c devices.
Does regmap assume that those registers form a (dense) array of
equal sized items? Does it introduce unconditional indirection
and requirement for explicit setup beyond mere mapping? What's
the overhead compared to the readl/inbe32 approach that's
currently resolved at compile time?
Neither of the above needs to be a blocker, just needs to be
acceptable after consideration. So far nobody appears to have
felt pain with the LE32 register assumption.
BTW does the common clock support that I introduce for MPC512x
only cover those parts from crystal over internal busses to
internal peripherals (register files).
It does not include bitrate generation within the peripherals --
this appears to remain the domain of individual drivers, which
keep manipulating register fields to derive wire bitrates from
internal references. Sharing drivers between platforms with and
without common clock support forbids the switch anyway, or both
CCF abstraction as well as local register manipulation need to
get implemented in parallel, as I did for the mscan(4) driver.
Some of these bitrate related registers aren't 32bit entities and
thus could not get managed by the common clock primitives in
their current form. Some of the IP blocks may even spread
integer values across several non-adjacent bit fields for legacy
reasons, but I guess that these aren't in the scope of the shared
primitives either (and they may not be popular either).
While we are at improvements for the common clock primitives:
What I missed was support for fractional dividers, i.e. dividers
with a register bitfield backed divider part but a fixed factor
multiplier part. Currently there's only dividers (bitfield
factor or bitfield with table lookup for the factor) and
fixed-factor (multiplier and divider, but both of them fixed and
not adjustable by register manipulation). This was addressed by
"intermediate" clock items ("ungated", "x4")
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-17 12:07 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 12:07 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 15, 2013 at 21:38 +0200, Sascha Hauer wrote:
>
> On Mon, Jul 15, 2013 at 08:47:34PM +0200, Gerhard Sittig wrote:
> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > index 6d55eb2..2c07061 100644
> > --- a/drivers/clk/clk-divider.c
> > +++ b/drivers/clk/clk-divider.c
> > @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> > struct clk_divider *divider = to_clk_divider(hw);
> > unsigned int div, val;
> >
> > - val = readl(divider->reg) >> divider->shift;
> > + val = clk_readl(divider->reg) >> divider->shift;
> > val &= div_mask(divider);
>
> Would it be an option to use regmap for the generic dividers/muxes
> instead? This should be suitable for ppc and also for people who want to
> use the generic clocks on i2c devices.
Does regmap assume that those registers form a (dense) array of
equal sized items? Does it introduce unconditional indirection
and requirement for explicit setup beyond mere mapping? What's
the overhead compared to the readl/inbe32 approach that's
currently resolved at compile time?
Neither of the above needs to be a blocker, just needs to be
acceptable after consideration. So far nobody appears to have
felt pain with the LE32 register assumption.
BTW does the common clock support that I introduce for MPC512x
only cover those parts from crystal over internal busses to
internal peripherals (register files).
It does not include bitrate generation within the peripherals --
this appears to remain the domain of individual drivers, which
keep manipulating register fields to derive wire bitrates from
internal references. Sharing drivers between platforms with and
without common clock support forbids the switch anyway, or both
CCF abstraction as well as local register manipulation need to
get implemented in parallel, as I did for the mscan(4) driver.
Some of these bitrate related registers aren't 32bit entities and
thus could not get managed by the common clock primitives in
their current form. Some of the IP blocks may even spread
integer values across several non-adjacent bit fields for legacy
reasons, but I guess that these aren't in the scope of the shared
primitives either (and they may not be popular either).
While we are at improvements for the common clock primitives:
What I missed was support for fractional dividers, i.e. dividers
with a register bitfield backed divider part but a fixed factor
multiplier part. Currently there's only dividers (bitfield
factor or bitfield with table lookup for the factor) and
fixed-factor (multiplier and divider, but both of them fixed and
not adjustable by register manipulation). This was addressed by
"intermediate" clock items ("ungated", "x4")
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
2013-07-17 11:22 ` Gerhard Sittig
(?)
@ 2013-07-17 12:07 ` Mark Brown
-1 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-17 12:07 UTC (permalink / raw)
To: Mike Turquette, Detlev Zundel, Wolfram Sang, David Woodhouse,
devicetree-discuss, Greg Kroah-Hartman, Rob Herring,
Marc Kleine-Budde, Wolfgang Grandegger, Anatolij Gustschin,
linuxppc-dev, linux-arm-kernel, Mauro Carvalho Chehab
[-- Attachment #1.1: Type: text/plain, Size: 1693 bytes --]
On Wed, Jul 17, 2013 at 01:22:29PM +0200, Gerhard Sittig wrote:
> On Mon, Jul 15, 2013 at 21:17 +0100, Mark Brown wrote:
> > On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
> > > sprintf(name, "psc%d_mclk", master->bus_num);
> > > spiclk = clk_get(&master->dev, name);
> > > - clk_enable(spiclk);
> > > + clk_prepare_enable(spiclk);
> > > mps->mclk = clk_get_rate(spiclk);
> > > clk_put(spiclk);
> > This code is *clearly* buggy and should be fixed rather than papered
> > over. Not only is there no matching put the driver is also dropping the
> > reference to the clock rather than holding on to it while it's in use.
> "This code" refers to the driver's original condition, right? I
> agree that the driver has been suffering from incomplete clock
> handling since it was born three years ago. And that this issue
> shall get addressed. The question is just whether it needs to be
> part of this series which has a different focus.
This is a pretty long e-mail. It'd probably have taken less time to
fix the issues than to reply to the e-mail... but anyway.
A big part of the issue with the state of the driver is that there's
obvious clock API abuse going on that isn't corrected here - the main
one is that the sprintf() for the clock name is a fairly clear warning
sign, the driver should be using a fixed value there. This raises a
warning flag for me about the quality of the common clock API
implementation that's being sent and/or the potential for bugs to be
noticed with the common clock framework. I'd not expect this code to
actually work, and looking at the rest of the series I don't see how it
does since I can't see what forces the name.
[-- Attachment #1.2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
[-- Attachment #2: Type: text/plain, Size: 150 bytes --]
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-17 12:07 ` Mark Brown
0 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-17 12:07 UTC (permalink / raw)
To: Mike Turquette, Detlev Zundel, Wolfram Sang, David Woodhouse,
devicetree-discuss, Greg Kroah-Hartman, Rob Herring,
Marc Kleine-Budde, Wolfgang Grandegger, Anatolij Gustschin,
linuxppc-dev, linux-arm-kernel, Mauro Carvalho Chehab
[-- Attachment #1: Type: text/plain, Size: 1693 bytes --]
On Wed, Jul 17, 2013 at 01:22:29PM +0200, Gerhard Sittig wrote:
> On Mon, Jul 15, 2013 at 21:17 +0100, Mark Brown wrote:
> > On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
> > > sprintf(name, "psc%d_mclk", master->bus_num);
> > > spiclk = clk_get(&master->dev, name);
> > > - clk_enable(spiclk);
> > > + clk_prepare_enable(spiclk);
> > > mps->mclk = clk_get_rate(spiclk);
> > > clk_put(spiclk);
> > This code is *clearly* buggy and should be fixed rather than papered
> > over. Not only is there no matching put the driver is also dropping the
> > reference to the clock rather than holding on to it while it's in use.
> "This code" refers to the driver's original condition, right? I
> agree that the driver has been suffering from incomplete clock
> handling since it was born three years ago. And that this issue
> shall get addressed. The question is just whether it needs to be
> part of this series which has a different focus.
This is a pretty long e-mail. It'd probably have taken less time to
fix the issues than to reply to the e-mail... but anyway.
A big part of the issue with the state of the driver is that there's
obvious clock API abuse going on that isn't corrected here - the main
one is that the sprintf() for the clock name is a fairly clear warning
sign, the driver should be using a fixed value there. This raises a
warning flag for me about the quality of the common clock API
implementation that's being sent and/or the potential for bugs to be
noticed with the common clock framework. I'd not expect this code to
actually work, and looking at the rest of the series I don't see how it
does since I can't see what forces the name.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-17 12:07 ` Mark Brown
0 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-17 12:07 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 17, 2013 at 01:22:29PM +0200, Gerhard Sittig wrote:
> On Mon, Jul 15, 2013 at 21:17 +0100, Mark Brown wrote:
> > On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
> > > sprintf(name, "psc%d_mclk", master->bus_num);
> > > spiclk = clk_get(&master->dev, name);
> > > - clk_enable(spiclk);
> > > + clk_prepare_enable(spiclk);
> > > mps->mclk = clk_get_rate(spiclk);
> > > clk_put(spiclk);
> > This code is *clearly* buggy and should be fixed rather than papered
> > over. Not only is there no matching put the driver is also dropping the
> > reference to the clock rather than holding on to it while it's in use.
> "This code" refers to the driver's original condition, right? I
> agree that the driver has been suffering from incomplete clock
> handling since it was born three years ago. And that this issue
> shall get addressed. The question is just whether it needs to be
> part of this series which has a different focus.
This is a pretty long e-mail. It'd probably have taken less time to
fix the issues than to reply to the e-mail... but anyway.
A big part of the issue with the state of the driver is that there's
obvious clock API abuse going on that isn't corrected here - the main
one is that the sprintf() for the clock name is a fairly clear warning
sign, the driver should be using a fixed value there. This raises a
warning flag for me about the quality of the common clock API
implementation that's being sent and/or the potential for bugs to be
noticed with the common clock framework. I'd not expect this code to
actually work, and looking at the rest of the series I don't see how it
does since I can't see what forces the name.
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^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
2013-07-17 12:07 ` Mark Brown
(?)
@ 2013-07-17 14:26 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 14:26 UTC (permalink / raw)
To: Mark Brown
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring,
Marc Kleine-Budde,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
On Wed, Jul 17, 2013 at 13:07 +0100, Mark Brown wrote:
>
> On Wed, Jul 17, 2013 at 01:22:29PM +0200, Gerhard Sittig wrote:
> > On Mon, Jul 15, 2013 at 21:17 +0100, Mark Brown wrote:
> > > On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
>
> > > > sprintf(name, "psc%d_mclk", master->bus_num);
> > > > spiclk = clk_get(&master->dev, name);
> > > > - clk_enable(spiclk);
> > > > + clk_prepare_enable(spiclk);
> > > > mps->mclk = clk_get_rate(spiclk);
> > > > clk_put(spiclk);
>
> > > This code is *clearly* buggy and should be fixed rather than papered
> > > over. Not only is there no matching put the driver is also dropping the
> > > reference to the clock rather than holding on to it while it's in use.
>
> > "This code" refers to the driver's original condition, right? I
> > agree that the driver has been suffering from incomplete clock
> > handling since it was born three years ago. And that this issue
> > shall get addressed. The question is just whether it needs to be
> > part of this series which has a different focus.
>
> This is a pretty long e-mail. It'd probably have taken less time to
> fix the issues than to reply to the e-mail... but anyway.
[ this is meta stuff, technical details are after the next quotation ]
Not quite. Please consider that careful submission is as
expensive as thorough review is, and that a lot of work is done
before v1 gets submitted, which you may not always notice from
looking at a concentrated series that may no longer suggest how
much it took to get there (especially when prepared carefully).
As mentioned before I did not question the need to fix issues as
they get identified. I just asked whether reworking the serial
driver is in the scope of this series which provides a different
clock driver implementation for the platform. To me these two
things are orthogonal, while I did promise to see how I can
address your concerns.
Let's provide the technical information you need to judge the
quality of the submission and see why it shall be acceptable:
> A big part of the issue with the state of the driver is that there's
> obvious clock API abuse going on that isn't corrected here - the main
> one is that the sprintf() for the clock name is a fairly clear warning
> sign, the driver should be using a fixed value there. This raises a
> warning flag for me about the quality of the common clock API
> implementation that's being sent and/or the potential for bugs to be
> noticed with the common clock framework. I'd not expect this code to
> actually work, and looking at the rest of the series I don't see how it
> does since I can't see what forces the name.
Why the code does work:
OK, here is why the driver keeps its state throughout the set and
is operational as good or as bad as it was before:
The sprintf() in the SPI driver used to construct a name which
includes the PSC index. This applies to the UART driver as well,
as they both use the PSC controller hardware to implement their
serial communication.
The corresponding clock name was found in the previous PPC_CLOCK
implementation since the clock driver provided those names which
include the PSC index (fixed strings in a table).
The initial COMMON_CLK implementation in part 09/24 registers
clkdev items for compatibility during migration. The string
isn't greppable since it's constructed by the preprocessor in the
MCLK data setup, see the MCLK_SETUP_DATA_PSC() macro.
Part 13/24 adjusts the SPI driver to no longer construct a name,
but instead use a fixed string after OF based clock lookup became
available. This shall meet your expectation and simplifies the
client side. Part 15/24 does the same for the UART driver.
Part 16/24 removes the clkdev registration in the clock driver
after both the UART and SPI clients switched to OF clock lookups.
At this stage things are the way you would expect: The client
uses a fixed string in the lookup, while lookup occurs via device
tree, and instances are supported without the clients'
constructing something based on a component index.
Remaining issues are not with the common clock support of the
platform, but in the serial driver and are identical to the
previous (actually: the initial) status. While we agree on the
existance of the remaining issue and the desire to address it.
Just not on which context that fix shall be done in.
The series' status and perspective:
The UART and SPI drivers did work before, while it's true that
clock handling wasn't complete (in non-fatal ways). This has
been the case in the past, and has been identified just now.
The serial drivers are kept operational during migration, and
still are operational after the series. But now they use common
clock and OF lookups, which is an improvement for the platform in
my eyes.
It's true that the status of the serial driver isn't improved
with the series -- but it isn't degraded either, while
(additional) breakage actively gets prevented.
Now let me see how I can improve the SPI driver with regard to
overall clock handling and beyond mere operation by coincidence
in the absence of errors. But please understand that I don't
want to stall the common clock support for a whole platform just
because some of the drivers it needs to touch to keep them
operational have other issues that weren't addressed yet, while
these issues aren't introduced with the series but preceed it.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office-ynQEQJNshbs@public.gmane.org
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-17 14:26 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 14:26 UTC (permalink / raw)
To: Mark Brown
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss, linuxppc-dev, Rob Herring, Marc Kleine-Budde,
linux-arm-kernel, Anatolij Gustschin, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
On Wed, Jul 17, 2013 at 13:07 +0100, Mark Brown wrote:
>
> On Wed, Jul 17, 2013 at 01:22:29PM +0200, Gerhard Sittig wrote:
> > On Mon, Jul 15, 2013 at 21:17 +0100, Mark Brown wrote:
> > > On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
>
> > > > sprintf(name, "psc%d_mclk", master->bus_num);
> > > > spiclk = clk_get(&master->dev, name);
> > > > - clk_enable(spiclk);
> > > > + clk_prepare_enable(spiclk);
> > > > mps->mclk = clk_get_rate(spiclk);
> > > > clk_put(spiclk);
>
> > > This code is *clearly* buggy and should be fixed rather than papered
> > > over. Not only is there no matching put the driver is also dropping the
> > > reference to the clock rather than holding on to it while it's in use.
>
> > "This code" refers to the driver's original condition, right? I
> > agree that the driver has been suffering from incomplete clock
> > handling since it was born three years ago. And that this issue
> > shall get addressed. The question is just whether it needs to be
> > part of this series which has a different focus.
>
> This is a pretty long e-mail. It'd probably have taken less time to
> fix the issues than to reply to the e-mail... but anyway.
[ this is meta stuff, technical details are after the next quotation ]
Not quite. Please consider that careful submission is as
expensive as thorough review is, and that a lot of work is done
before v1 gets submitted, which you may not always notice from
looking at a concentrated series that may no longer suggest how
much it took to get there (especially when prepared carefully).
As mentioned before I did not question the need to fix issues as
they get identified. I just asked whether reworking the serial
driver is in the scope of this series which provides a different
clock driver implementation for the platform. To me these two
things are orthogonal, while I did promise to see how I can
address your concerns.
Let's provide the technical information you need to judge the
quality of the submission and see why it shall be acceptable:
> A big part of the issue with the state of the driver is that there's
> obvious clock API abuse going on that isn't corrected here - the main
> one is that the sprintf() for the clock name is a fairly clear warning
> sign, the driver should be using a fixed value there. This raises a
> warning flag for me about the quality of the common clock API
> implementation that's being sent and/or the potential for bugs to be
> noticed with the common clock framework. I'd not expect this code to
> actually work, and looking at the rest of the series I don't see how it
> does since I can't see what forces the name.
Why the code does work:
OK, here is why the driver keeps its state throughout the set and
is operational as good or as bad as it was before:
The sprintf() in the SPI driver used to construct a name which
includes the PSC index. This applies to the UART driver as well,
as they both use the PSC controller hardware to implement their
serial communication.
The corresponding clock name was found in the previous PPC_CLOCK
implementation since the clock driver provided those names which
include the PSC index (fixed strings in a table).
The initial COMMON_CLK implementation in part 09/24 registers
clkdev items for compatibility during migration. The string
isn't greppable since it's constructed by the preprocessor in the
MCLK data setup, see the MCLK_SETUP_DATA_PSC() macro.
Part 13/24 adjusts the SPI driver to no longer construct a name,
but instead use a fixed string after OF based clock lookup became
available. This shall meet your expectation and simplifies the
client side. Part 15/24 does the same for the UART driver.
Part 16/24 removes the clkdev registration in the clock driver
after both the UART and SPI clients switched to OF clock lookups.
At this stage things are the way you would expect: The client
uses a fixed string in the lookup, while lookup occurs via device
tree, and instances are supported without the clients'
constructing something based on a component index.
Remaining issues are not with the common clock support of the
platform, but in the serial driver and are identical to the
previous (actually: the initial) status. While we agree on the
existance of the remaining issue and the desire to address it.
Just not on which context that fix shall be done in.
The series' status and perspective:
The UART and SPI drivers did work before, while it's true that
clock handling wasn't complete (in non-fatal ways). This has
been the case in the past, and has been identified just now.
The serial drivers are kept operational during migration, and
still are operational after the series. But now they use common
clock and OF lookups, which is an improvement for the platform in
my eyes.
It's true that the status of the serial driver isn't improved
with the series -- but it isn't degraded either, while
(additional) breakage actively gets prevented.
Now let me see how I can improve the SPI driver with regard to
overall clock handling and beyond mere operation by coincidence
in the absence of errors. But please understand that I don't
want to stall the common clock support for a whole platform just
because some of the drivers it needs to touch to keep them
operational have other issues that weren't addressed yet, while
these issues aren't introduced with the series but preceed it.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-17 14:26 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-17 14:26 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 17, 2013 at 13:07 +0100, Mark Brown wrote:
>
> On Wed, Jul 17, 2013 at 01:22:29PM +0200, Gerhard Sittig wrote:
> > On Mon, Jul 15, 2013 at 21:17 +0100, Mark Brown wrote:
> > > On Mon, Jul 15, 2013 at 08:47:30PM +0200, Gerhard Sittig wrote:
>
> > > > sprintf(name, "psc%d_mclk", master->bus_num);
> > > > spiclk = clk_get(&master->dev, name);
> > > > - clk_enable(spiclk);
> > > > + clk_prepare_enable(spiclk);
> > > > mps->mclk = clk_get_rate(spiclk);
> > > > clk_put(spiclk);
>
> > > This code is *clearly* buggy and should be fixed rather than papered
> > > over. Not only is there no matching put the driver is also dropping the
> > > reference to the clock rather than holding on to it while it's in use.
>
> > "This code" refers to the driver's original condition, right? I
> > agree that the driver has been suffering from incomplete clock
> > handling since it was born three years ago. And that this issue
> > shall get addressed. The question is just whether it needs to be
> > part of this series which has a different focus.
>
> This is a pretty long e-mail. It'd probably have taken less time to
> fix the issues than to reply to the e-mail... but anyway.
[ this is meta stuff, technical details are after the next quotation ]
Not quite. Please consider that careful submission is as
expensive as thorough review is, and that a lot of work is done
before v1 gets submitted, which you may not always notice from
looking at a concentrated series that may no longer suggest how
much it took to get there (especially when prepared carefully).
As mentioned before I did not question the need to fix issues as
they get identified. I just asked whether reworking the serial
driver is in the scope of this series which provides a different
clock driver implementation for the platform. To me these two
things are orthogonal, while I did promise to see how I can
address your concerns.
Let's provide the technical information you need to judge the
quality of the submission and see why it shall be acceptable:
> A big part of the issue with the state of the driver is that there's
> obvious clock API abuse going on that isn't corrected here - the main
> one is that the sprintf() for the clock name is a fairly clear warning
> sign, the driver should be using a fixed value there. This raises a
> warning flag for me about the quality of the common clock API
> implementation that's being sent and/or the potential for bugs to be
> noticed with the common clock framework. I'd not expect this code to
> actually work, and looking at the rest of the series I don't see how it
> does since I can't see what forces the name.
Why the code does work:
OK, here is why the driver keeps its state throughout the set and
is operational as good or as bad as it was before:
The sprintf() in the SPI driver used to construct a name which
includes the PSC index. This applies to the UART driver as well,
as they both use the PSC controller hardware to implement their
serial communication.
The corresponding clock name was found in the previous PPC_CLOCK
implementation since the clock driver provided those names which
include the PSC index (fixed strings in a table).
The initial COMMON_CLK implementation in part 09/24 registers
clkdev items for compatibility during migration. The string
isn't greppable since it's constructed by the preprocessor in the
MCLK data setup, see the MCLK_SETUP_DATA_PSC() macro.
Part 13/24 adjusts the SPI driver to no longer construct a name,
but instead use a fixed string after OF based clock lookup became
available. This shall meet your expectation and simplifies the
client side. Part 15/24 does the same for the UART driver.
Part 16/24 removes the clkdev registration in the clock driver
after both the UART and SPI clients switched to OF clock lookups.
At this stage things are the way you would expect: The client
uses a fixed string in the lookup, while lookup occurs via device
tree, and instances are supported without the clients'
constructing something based on a component index.
Remaining issues are not with the common clock support of the
platform, but in the serial driver and are identical to the
previous (actually: the initial) status. While we agree on the
existance of the remaining issue and the desire to address it.
Just not on which context that fix shall be done in.
The series' status and perspective:
The UART and SPI drivers did work before, while it's true that
clock handling wasn't complete (in non-fatal ways). This has
been the case in the past, and has been identified just now.
The serial drivers are kept operational during migration, and
still are operational after the series. But now they use common
clock and OF lookups, which is an improvement for the platform in
my eyes.
It's true that the status of the serial driver isn't improved
with the series -- but it isn't degraded either, while
(additional) breakage actively gets prevented.
Now let me see how I can improve the SPI driver with regard to
overall clock handling and beyond mere operation by coincidence
in the absence of errors. But please understand that I don't
want to stall the common clock support for a whole platform just
because some of the drivers it needs to touch to keep them
operational have other issues that weren't addressed yet, while
these issues aren't introduced with the series but preceed it.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
2013-07-17 14:26 ` Gerhard Sittig
(?)
@ 2013-07-17 16:53 ` Mark Brown
-1 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-17 16:53 UTC (permalink / raw)
To: Mike Turquette, Detlev Zundel, Wolfram Sang, David Woodhouse,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Greg Kroah-Hartman,
Rob Herring, Marc Kleine-Budde, Wolfgang Grandegger,
Anatolij Gustschin, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Mauro Carvalho Chehab
[-- Attachment #1.1: Type: text/plain, Size: 2415 bytes --]
On Wed, Jul 17, 2013 at 04:26:28PM +0200, Gerhard Sittig wrote:
> On Wed, Jul 17, 2013 at 13:07 +0100, Mark Brown wrote:
> > This is a pretty long e-mail. It'd probably have taken less time to
> > fix the issues than to reply to the e-mail... but anyway.
> Not quite. Please consider that careful submission is as
> expensive as thorough review is, and that a lot of work is done
> before v1 gets submitted, which you may not always notice from
> looking at a concentrated series that may no longer suggest how
> much it took to get there (especially when prepared carefully).
This is rather undermined the more time and effort gets spent pushing
back against doing trival fixes, of course... besides, the issues here
are all really simple to fix and test. It's not a major or risky
rewrite of the driver or anything like that - most of this can be tested
by just probing the driver.
> As mentioned before I did not question the need to fix issues as
> they get identified. I just asked whether reworking the serial
OK, so send patches then.
> The initial COMMON_CLK implementation in part 09/24 registers
> clkdev items for compatibility during migration. The string
> isn't greppable since it's constructed by the preprocessor in the
> MCLK data setup, see the MCLK_SETUP_DATA_PSC() macro.
Ugh, right - it didn't show up in searches due to being hidden by the
macro.
> Now let me see how I can improve the SPI driver with regard to
> overall clock handling and beyond mere operation by coincidence
> in the absence of errors. But please understand that I don't
> want to stall the common clock support for a whole platform just
> because some of the drivers it needs to touch to keep them
> operational have other issues that weren't addressed yet, while
> these issues aren't introduced with the series but preceed it.
Again, you're not being asked to implement substantial new functionality
here. From my point of view I can't test this at all so I'm looking at
code that's obviously not good for the standard clock API and wondering
if it even works or how robust it's going to be going forward as the
common clock code changes which makes me relucatant to say it'll be OK.
The fact that you're switching over to use generic code is itself a
reason to make sure that the API usage is sane, dodgy API usage against
open coded clock implementations is less risky than against the common
code.
[-- Attachment #1.2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
[-- Attachment #2: Type: text/plain, Size: 192 bytes --]
_______________________________________________
devicetree-discuss mailing list
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-17 16:53 ` Mark Brown
0 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-17 16:53 UTC (permalink / raw)
To: Mike Turquette, Detlev Zundel, Wolfram Sang, David Woodhouse,
devicetree-discuss, Greg Kroah-Hartman, Rob Herring,
Marc Kleine-Budde, Wolfgang Grandegger, Anatolij Gustschin,
linuxppc-dev, linux-arm-kernel, Mauro Carvalho Chehab
[-- Attachment #1: Type: text/plain, Size: 2415 bytes --]
On Wed, Jul 17, 2013 at 04:26:28PM +0200, Gerhard Sittig wrote:
> On Wed, Jul 17, 2013 at 13:07 +0100, Mark Brown wrote:
> > This is a pretty long e-mail. It'd probably have taken less time to
> > fix the issues than to reply to the e-mail... but anyway.
> Not quite. Please consider that careful submission is as
> expensive as thorough review is, and that a lot of work is done
> before v1 gets submitted, which you may not always notice from
> looking at a concentrated series that may no longer suggest how
> much it took to get there (especially when prepared carefully).
This is rather undermined the more time and effort gets spent pushing
back against doing trival fixes, of course... besides, the issues here
are all really simple to fix and test. It's not a major or risky
rewrite of the driver or anything like that - most of this can be tested
by just probing the driver.
> As mentioned before I did not question the need to fix issues as
> they get identified. I just asked whether reworking the serial
OK, so send patches then.
> The initial COMMON_CLK implementation in part 09/24 registers
> clkdev items for compatibility during migration. The string
> isn't greppable since it's constructed by the preprocessor in the
> MCLK data setup, see the MCLK_SETUP_DATA_PSC() macro.
Ugh, right - it didn't show up in searches due to being hidden by the
macro.
> Now let me see how I can improve the SPI driver with regard to
> overall clock handling and beyond mere operation by coincidence
> in the absence of errors. But please understand that I don't
> want to stall the common clock support for a whole platform just
> because some of the drivers it needs to touch to keep them
> operational have other issues that weren't addressed yet, while
> these issues aren't introduced with the series but preceed it.
Again, you're not being asked to implement substantial new functionality
here. From my point of view I can't test this at all so I'm looking at
code that's obviously not good for the standard clock API and wondering
if it even works or how robust it's going to be going forward as the
common clock code changes which makes me relucatant to say it'll be OK.
The fact that you're switching over to use generic code is itself a
reason to make sure that the API usage is sane, dodgy API usage against
open coded clock implementations is less risky than against the common
code.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 01/24] spi: mpc512x: prepare clocks before enabling them
@ 2013-07-17 16:53 ` Mark Brown
0 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-17 16:53 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 17, 2013 at 04:26:28PM +0200, Gerhard Sittig wrote:
> On Wed, Jul 17, 2013 at 13:07 +0100, Mark Brown wrote:
> > This is a pretty long e-mail. It'd probably have taken less time to
> > fix the issues than to reply to the e-mail... but anyway.
> Not quite. Please consider that careful submission is as
> expensive as thorough review is, and that a lot of work is done
> before v1 gets submitted, which you may not always notice from
> looking at a concentrated series that may no longer suggest how
> much it took to get there (especially when prepared carefully).
This is rather undermined the more time and effort gets spent pushing
back against doing trival fixes, of course... besides, the issues here
are all really simple to fix and test. It's not a major or risky
rewrite of the driver or anything like that - most of this can be tested
by just probing the driver.
> As mentioned before I did not question the need to fix issues as
> they get identified. I just asked whether reworking the serial
OK, so send patches then.
> The initial COMMON_CLK implementation in part 09/24 registers
> clkdev items for compatibility during migration. The string
> isn't greppable since it's constructed by the preprocessor in the
> MCLK data setup, see the MCLK_SETUP_DATA_PSC() macro.
Ugh, right - it didn't show up in searches due to being hidden by the
macro.
> Now let me see how I can improve the SPI driver with regard to
> overall clock handling and beyond mere operation by coincidence
> in the absence of errors. But please understand that I don't
> want to stall the common clock support for a whole platform just
> because some of the drivers it needs to touch to keep them
> operational have other issues that weren't addressed yet, while
> these issues aren't introduced with the series but preceed it.
Again, you're not being asked to implement substantial new functionality
here. From my point of view I can't test this at all so I'm looking at
code that's obviously not good for the standard clock API and wondering
if it even works or how robust it's going to be going forward as the
common clock code changes which makes me relucatant to say it'll be OK.
The fact that you're switching over to use generic code is itself a
reason to make sure that the API usage is sane, dodgy API usage against
open coded clock implementations is less risky than against the common
code.
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^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
2013-07-15 19:38 ` Sascha Hauer
@ 2013-07-18 7:04 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 7:04 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss, Rob Herring, Mark Brown, Marc Kleine-Budde,
Wolfgang Grandegger, Anatolij Gustschin, linuxppc-dev,
David Woodhouse, linux-arm-kernel, Mauro Carvalho Chehab
On Mon, Jul 15, 2013 at 21:38 +0200, Sascha Hauer wrote:
>
> On Mon, Jul 15, 2013 at 08:47:34PM +0200, Gerhard Sittig wrote:
> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > index 6d55eb2..2c07061 100644
> > --- a/drivers/clk/clk-divider.c
> > +++ b/drivers/clk/clk-divider.c
> > @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> > struct clk_divider *divider = to_clk_divider(hw);
> > unsigned int div, val;
> >
> > - val = readl(divider->reg) >> divider->shift;
> > + val = clk_readl(divider->reg) >> divider->shift;
> > val &= div_mask(divider);
>
> Would it be an option to use regmap for the generic dividers/muxes
> instead? This should be suitable for ppc and also for people who want to
> use the generic clocks on i2c devices.
Some other thought crossed my mind regarding access to clock
control registers that reside behind some communication channel
like I2C:
The common clock API assumes (it's part of the contract) that
there are potentially expensive operations like get, put, prepare
and unprepare, as well as swift and non-blocking operations like
enable and disable.
Would the regmap abstraction hide the potentially blocking nature
of a register access (I understand that you can implement "local"
as well as "remote" register sets by this mechanism)? Or could
you still meet the assumptions or requirements of the common
clock API?
It might as well be the responsibility of the clock driver's
implementor to arrange for the availability of non-blocking
enable/disable operations, just as it is today. Such that
expensive register access need not be forbidden in general.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-18 7:04 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 7:04 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 15, 2013 at 21:38 +0200, Sascha Hauer wrote:
>
> On Mon, Jul 15, 2013 at 08:47:34PM +0200, Gerhard Sittig wrote:
> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > index 6d55eb2..2c07061 100644
> > --- a/drivers/clk/clk-divider.c
> > +++ b/drivers/clk/clk-divider.c
> > @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> > struct clk_divider *divider = to_clk_divider(hw);
> > unsigned int div, val;
> >
> > - val = readl(divider->reg) >> divider->shift;
> > + val = clk_readl(divider->reg) >> divider->shift;
> > val &= div_mask(divider);
>
> Would it be an option to use regmap for the generic dividers/muxes
> instead? This should be suitable for ppc and also for people who want to
> use the generic clocks on i2c devices.
Some other thought crossed my mind regarding access to clock
control registers that reside behind some communication channel
like I2C:
The common clock API assumes (it's part of the contract) that
there are potentially expensive operations like get, put, prepare
and unprepare, as well as swift and non-blocking operations like
enable and disable.
Would the regmap abstraction hide the potentially blocking nature
of a register access (I understand that you can implement "local"
as well as "remote" register sets by this mechanism)? Or could
you still meet the assumptions or requirements of the common
clock API?
It might as well be the responsibility of the clock driver's
implementor to arrange for the availability of non-blocking
enable/disable operations, just as it is today. Such that
expensive register access need not be forbidden in general.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
2013-07-18 7:04 ` Gerhard Sittig
@ 2013-07-18 8:06 ` Sascha Hauer
-1 siblings, 0 replies; 432+ messages in thread
From: Sascha Hauer @ 2013-07-18 8:06 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss, Detlev Zundel,
Wolfram Sang, Greg Kroah-Hartman, Rob Herring, Mark Brown,
Marc Kleine-Budde, David Woodhouse, Wolfgang Grandegger,
Mauro Carvalho Chehab
On Thu, Jul 18, 2013 at 09:04:02AM +0200, Gerhard Sittig wrote:
> On Mon, Jul 15, 2013 at 21:38 +0200, Sascha Hauer wrote:
> >
> > On Mon, Jul 15, 2013 at 08:47:34PM +0200, Gerhard Sittig wrote:
> > > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > > index 6d55eb2..2c07061 100644
> > > --- a/drivers/clk/clk-divider.c
> > > +++ b/drivers/clk/clk-divider.c
> > > @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> > > struct clk_divider *divider = to_clk_divider(hw);
> > > unsigned int div, val;
> > >
> > > - val = readl(divider->reg) >> divider->shift;
> > > + val = clk_readl(divider->reg) >> divider->shift;
> > > val &= div_mask(divider);
> >
> > Would it be an option to use regmap for the generic dividers/muxes
> > instead? This should be suitable for ppc and also for people who want to
> > use the generic clocks on i2c devices.
>
> Some other thought crossed my mind regarding access to clock
> control registers that reside behind some communication channel
> like I2C:
>
> The common clock API assumes (it's part of the contract) that
> there are potentially expensive operations like get, put, prepare
> and unprepare, as well as swift and non-blocking operations like
> enable and disable.
>
> Would the regmap abstraction hide the potentially blocking nature
> of a register access (I understand that you can implement "local"
> as well as "remote" register sets by this mechanism)? Or could
> you still meet the assumptions or requirements of the common
> clock API?
>
> It might as well be the responsibility of the clock driver's
> implementor to arrange for the availability of non-blocking
> enable/disable operations, just as it is today. Such that
> expensive register access need not be forbidden in general.
regmap for mmio uses a spinlock for read/modify/write operations, just
like you have to use a spinlock in the common clk dividers/gates. This
part wouldn't change with regmap.
For i2c connected clocks where a spinlock doesn't work due to the
nonatomic nature of i2c devices we would have to move the enable/disble
stuff to prepare/unprepare in the common gate code. This can be left
for someone who works on i2c clocks though.
I think regmap has the potential to solve a number of issues like the
hardcoded readl/writel in the common clock blocks, issues with i2c
clocks and your endianess issue. The biggest question probably is how
to get there without putting too much of a burden on you. It's probably
not an option to convert all users to regmap, so it seems additional
functions like clk_register_gate_regmap are better to handle.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-18 8:06 ` Sascha Hauer
0 siblings, 0 replies; 432+ messages in thread
From: Sascha Hauer @ 2013-07-18 8:06 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 18, 2013 at 09:04:02AM +0200, Gerhard Sittig wrote:
> On Mon, Jul 15, 2013 at 21:38 +0200, Sascha Hauer wrote:
> >
> > On Mon, Jul 15, 2013 at 08:47:34PM +0200, Gerhard Sittig wrote:
> > > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > > index 6d55eb2..2c07061 100644
> > > --- a/drivers/clk/clk-divider.c
> > > +++ b/drivers/clk/clk-divider.c
> > > @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> > > struct clk_divider *divider = to_clk_divider(hw);
> > > unsigned int div, val;
> > >
> > > - val = readl(divider->reg) >> divider->shift;
> > > + val = clk_readl(divider->reg) >> divider->shift;
> > > val &= div_mask(divider);
> >
> > Would it be an option to use regmap for the generic dividers/muxes
> > instead? This should be suitable for ppc and also for people who want to
> > use the generic clocks on i2c devices.
>
> Some other thought crossed my mind regarding access to clock
> control registers that reside behind some communication channel
> like I2C:
>
> The common clock API assumes (it's part of the contract) that
> there are potentially expensive operations like get, put, prepare
> and unprepare, as well as swift and non-blocking operations like
> enable and disable.
>
> Would the regmap abstraction hide the potentially blocking nature
> of a register access (I understand that you can implement "local"
> as well as "remote" register sets by this mechanism)? Or could
> you still meet the assumptions or requirements of the common
> clock API?
>
> It might as well be the responsibility of the clock driver's
> implementor to arrange for the availability of non-blocking
> enable/disable operations, just as it is today. Such that
> expensive register access need not be forbidden in general.
regmap for mmio uses a spinlock for read/modify/write operations, just
like you have to use a spinlock in the common clk dividers/gates. This
part wouldn't change with regmap.
For i2c connected clocks where a spinlock doesn't work due to the
nonatomic nature of i2c devices we would have to move the enable/disble
stuff to prepare/unprepare in the common gate code. This can be left
for someone who works on i2c clocks though.
I think regmap has the potential to solve a number of issues like the
hardcoded readl/writel in the common clock blocks, issues with i2c
clocks and your endianess issue. The biggest question probably is how
to get there without putting too much of a burden on you. It's probably
not an option to convert all users to regmap, so it seems additional
functions like clk_register_gate_regmap are better to handle.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
2013-07-18 7:04 ` Gerhard Sittig
(?)
@ 2013-07-18 9:17 ` Russell King - ARM Linux
-1 siblings, 0 replies; 432+ messages in thread
From: Russell King - ARM Linux @ 2013-07-18 9:17 UTC (permalink / raw)
To: Gerhard Sittig
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
Sascha Hauer, Rob Herring, David Woodhouse, Mark Brown,
Marc Kleine-Budde,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Wolfgang Grandegger,
Mauro Carvalho Chehab
On Thu, Jul 18, 2013 at 09:04:02AM +0200, Gerhard Sittig wrote:
> The common clock API assumes (it's part of the contract) that
> there are potentially expensive operations like get, put, prepare
> and unprepare, as well as swift and non-blocking operations like
> enable and disable.
Let's get something straight here, because what you've said above is
wrong.
1. clk_get() and clk_put() are NOT part of the common clock API.
They're separate - they're part of the clk API, and the infrastructure
behind that is clkdev, which is a separately owned thing (by me.)
2. The "contract" of the clk API is defined by the clk API, not by some
random implementation like the common clock API. The clk API is
maintained by myself, and is described in include/linux/clk.h
3. clk_prepare() and clk_unprepare() are functions MUST only be called
from contexts where sleeping is permitted. These functions MAY sleep
for whatever reason they require to, and as long as they require to.
(This is the whole reason these two functions were created in the
first place.)
4. clk_enable() and clk_disable() MAY be called from any context, but
MUST never sleep. If you need to talk over a non-atomic bus for these,
then these functions should be no-ops, and the code which does that
must be executed from the clk_prepare()/clk_unprepare() operations.
That is the "clk API" contract. The CCF has no bearing on this; if it
disagrees, then the CCF is buggy and is non-conformant.
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-18 9:17 ` Russell King - ARM Linux
0 siblings, 0 replies; 432+ messages in thread
From: Russell King - ARM Linux @ 2013-07-18 9:17 UTC (permalink / raw)
To: Gerhard Sittig
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
Sascha Hauer, Rob Herring, David Woodhouse, Mark Brown,
Marc Kleine-Budde, linux-arm-kernel, Anatolij Gustschin,
linuxppc-dev, devicetree-discuss, Wolfgang Grandegger,
Mauro Carvalho Chehab
On Thu, Jul 18, 2013 at 09:04:02AM +0200, Gerhard Sittig wrote:
> The common clock API assumes (it's part of the contract) that
> there are potentially expensive operations like get, put, prepare
> and unprepare, as well as swift and non-blocking operations like
> enable and disable.
Let's get something straight here, because what you've said above is
wrong.
1. clk_get() and clk_put() are NOT part of the common clock API.
They're separate - they're part of the clk API, and the infrastructure
behind that is clkdev, which is a separately owned thing (by me.)
2. The "contract" of the clk API is defined by the clk API, not by some
random implementation like the common clock API. The clk API is
maintained by myself, and is described in include/linux/clk.h
3. clk_prepare() and clk_unprepare() are functions MUST only be called
from contexts where sleeping is permitted. These functions MAY sleep
for whatever reason they require to, and as long as they require to.
(This is the whole reason these two functions were created in the
first place.)
4. clk_enable() and clk_disable() MAY be called from any context, but
MUST never sleep. If you need to talk over a non-atomic bus for these,
then these functions should be no-ops, and the code which does that
must be executed from the clk_prepare()/clk_unprepare() operations.
That is the "clk API" contract. The CCF has no bearing on this; if it
disagrees, then the CCF is buggy and is non-conformant.
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-18 9:17 ` Russell King - ARM Linux
0 siblings, 0 replies; 432+ messages in thread
From: Russell King - ARM Linux @ 2013-07-18 9:17 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 18, 2013 at 09:04:02AM +0200, Gerhard Sittig wrote:
> The common clock API assumes (it's part of the contract) that
> there are potentially expensive operations like get, put, prepare
> and unprepare, as well as swift and non-blocking operations like
> enable and disable.
Let's get something straight here, because what you've said above is
wrong.
1. clk_get() and clk_put() are NOT part of the common clock API.
They're separate - they're part of the clk API, and the infrastructure
behind that is clkdev, which is a separately owned thing (by me.)
2. The "contract" of the clk API is defined by the clk API, not by some
random implementation like the common clock API. The clk API is
maintained by myself, and is described in include/linux/clk.h
3. clk_prepare() and clk_unprepare() are functions MUST only be called
from contexts where sleeping is permitted. These functions MAY sleep
for whatever reason they require to, and as long as they require to.
(This is the whole reason these two functions were created in the
first place.)
4. clk_enable() and clk_disable() MAY be called from any context, but
MUST never sleep. If you need to talk over a non-atomic bus for these,
then these functions should be no-ops, and the code which does that
must be executed from the clk_prepare()/clk_unprepare() operations.
That is the "clk API" contract. The CCF has no bearing on this; if it
disagrees, then the CCF is buggy and is non-conformant.
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
2013-07-18 8:06 ` Sascha Hauer
(?)
@ 2013-07-18 10:08 ` Mark Brown
-1 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-18 10:08 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring,
Marc Kleine-Budde, Wolfgang Grandegger,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, David Woodhouse,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Mauro Carvalho Chehab
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On Thu, Jul 18, 2013 at 10:06:57AM +0200, Sascha Hauer wrote:
> I think regmap has the potential to solve a number of issues like the
> hardcoded readl/writel in the common clock blocks, issues with i2c
> clocks and your endianess issue. The biggest question probably is how
> to get there without putting too much of a burden on you. It's probably
> not an option to convert all users to regmap, so it seems additional
> functions like clk_register_gate_regmap are better to handle.
That's basically what regulator does. There's versions of the ops that
all the drivers can use.
[-- Attachment #1.2: Digital signature --]
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_______________________________________________
devicetree-discuss mailing list
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 432+ messages in thread
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-18 10:08 ` Mark Brown
0 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-18 10:08 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman,
devicetree-discuss, Rob Herring, Marc Kleine-Budde,
Wolfgang Grandegger, Anatolij Gustschin, linuxppc-dev,
David Woodhouse, linux-arm-kernel, Mauro Carvalho Chehab
[-- Attachment #1: Type: text/plain, Size: 583 bytes --]
On Thu, Jul 18, 2013 at 10:06:57AM +0200, Sascha Hauer wrote:
> I think regmap has the potential to solve a number of issues like the
> hardcoded readl/writel in the common clock blocks, issues with i2c
> clocks and your endianess issue. The biggest question probably is how
> to get there without putting too much of a burden on you. It's probably
> not an option to convert all users to regmap, so it seems additional
> functions like clk_register_gate_regmap are better to handle.
That's basically what regulator does. There's versions of the ops that
all the drivers can use.
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^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-18 10:08 ` Mark Brown
0 siblings, 0 replies; 432+ messages in thread
From: Mark Brown @ 2013-07-18 10:08 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 18, 2013 at 10:06:57AM +0200, Sascha Hauer wrote:
> I think regmap has the potential to solve a number of issues like the
> hardcoded readl/writel in the common clock blocks, issues with i2c
> clocks and your endianess issue. The biggest question probably is how
> to get there without putting too much of a burden on you. It's probably
> not an option to convert all users to regmap, so it seems additional
> functions like clk_register_gate_regmap are better to handle.
That's basically what regulator does. There's versions of the ops that
all the drivers can use.
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^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v2 00/24] add COMMON_CLK support for PowerPC MPC512x
2013-07-15 18:47 ` Gerhard Sittig
(?)
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this series introduces support for the common clock framework (CCF,
COMMON_CLK Kconfig option) in the PowerPC based MPC512x platform
although the series does touch several subsystems -- serial, spi, net
(can, fs_enet), mtd (nfc), usb, i2c, media (viu), and dts -- all of the
patches are strictly clock related
it appears most appropriate to take this series through either the clk
or the powerpc trees after it has passed review and other subsystem
maintainers ACKed the clock setup related driver modifications
the series passes 'checkpatch.pl --strict' except for one warning which
cannot get resolved, since that either breaks compilation (the data type
is preset by the clk-provider.h API) or requires a cast which shadows
real mismatches:
WARNING: static const char * array should probably be static const char * const
#413: FILE: arch/powerpc/platforms/512x/clock-commonclk.c:335:
+static const char *parent_names_mux0[] = {
total: 0 errors, 1 warnings, 0 checks, 836 lines checked
each step in the series was build and run tested (with a display that is
attached to the DIU as well as SPI, with an SPI attached NOR flash, with
multiple UART ports such that one is not the boot console, with EEPROMs
attached to I2C, with an SD card, booting from network)
changes in v2:
- cleanup of the UART and SPI clock handling before the introduction of
common clock support for the platform, as incomplete clock handling
becomes fatal or more dangerous later (which in turn changes the
context of the "device tree lookup only" followup patch later)
- reordered the sequence of patches to keep the serial communication
related parts together (UART, SPI, and PSC FIFO changes after common
clock support was introduced)
- updated commit messages for the clock API use cleanup in the serial
communication drivers, updated comments and reworded commit messages
in the core clock driver to expand on the pre-enable workaround and
clkdev registration
- keep a reference to the PSC FIFO clock during use instead of looking
up the clock again in the uninit() routine
- remove the clkdev.h header file inclusion directive with the removal
of the clkdev registration call
Gerhard Sittig (24):
spi: mpc512x: cleanup clock API use
serial: mpc512x: cleanup clock API use
mtd: mpc5121_nfc: prepare clocks before enabling them
powerpc: mpc512x: array decl for MCLK registers in CCM
clk: wrap I/O access for improved portability
dts: mpc512x: prepare for preprocessor support
dts: mpc512x: introduce dt-bindings/clock/ header
dts: mpc512x: add clock related device tree specs
clk: mpc512x: introduce COMMON_CLK for MPC512x
dts: mpc512x: add clock specs for client lookups
spi: mpc512x: remove now obsolete clock lookup name
serial: mpc512x: remove now obsolete clock lookup name
clk: mpc512x: remove now obsolete clkdev registration
serial: mpc512x: setup the PSC FIFO clock as well
net: can: mscan: add a comment on reg to idx mapping
net: can: mscan: make mpc512x code use common clock
powerpc/mpc512x: improve DIU related clock setup
i2c: mpc: OF clock lookup for MPC512x
USB: fsl-mph-dr-of: OF clock lookup, prepare and enable
fs_enet: OF clock lookup (non-fatal), prepare and enable
[media] fsl-viu: OF clock lookup, prepare before enable
powerpc/fsl-pci: OF clock lookup, prepare before enable
clk: mpc512x: switch to COMMON_CLK, remove PPC_CLOCK
net: can: mscan: remove MPC512x non-COMMON_CLK code path
arch/powerpc/boot/dts/ac14xx.dts | 9 +-
arch/powerpc/boot/dts/include/dt-bindings | 1 +
arch/powerpc/boot/dts/mpc5121.dtsi | 94 ++-
arch/powerpc/boot/dts/mpc5121ads.dts | 2 +-
arch/powerpc/boot/dts/pdm360ng.dts | 2 +-
arch/powerpc/include/asm/mpc5121.h | 18 +-
arch/powerpc/platforms/512x/Kconfig | 2 +-
arch/powerpc/platforms/512x/Makefile | 3 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 761 ++++++++++++++++++++
arch/powerpc/platforms/512x/clock.c | 753 -------------------
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++--
arch/powerpc/sysdev/fsl_pci.c | 15 +
drivers/clk/clk-divider.c | 6 +-
drivers/clk/clk-gate.c | 6 +-
drivers/clk/clk-mux.c | 6 +-
drivers/i2c/busses/i2c-mpc.c | 9 +
drivers/media/platform/fsl-viu.c | 12 +-
drivers/mtd/nand/mpc5121_nfc.c | 4 +-
drivers/net/can/mscan/mpc5xxx_can.c | 234 +++---
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 27 +-
drivers/spi/spi-mpc512x-psc.c | 45 +-
drivers/tty/serial/mpc52xx_uart.c | 137 +++-
drivers/usb/host/fsl-mph-dr-of.c | 24 +-
include/dt-bindings/clock/mpc512x-clock.h | 59 ++
include/linux/clk-provider.h | 33 +
include/linux/fs_enet_pd.h | 3 +
26 files changed, 1392 insertions(+), 1038 deletions(-)
create mode 120000 arch/powerpc/boot/dts/include/dt-bindings
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
delete mode 100644 arch/powerpc/platforms/512x/clock.c
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
# uname -srm
Linux 3.11.0-rc1-00024-g96ff9fe ppc
# cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
ac97 0 0 24567000
spdif_rx_in 0 0 0
spdif_tx_in 0 0 0
psc_mclk_in 0 0 25000000
dummy 1 1 0
osc 1 1 25000000
ref 1 1 25000000
sys 10 10 320000000
spdif-mux0 0 0 320000000
spdif-en0 0 0 320000000
spdif_mclk_div 0 0 80000000
spdif_mclk_out 0 0 80000000
spdif_mclk 0 0 80000000
mscan3-mux0 1 1 320000000
mscan3-en0 1 1 320000000
mscan3_mclk_div 1 1 80000000
mscan3_mclk_out 1 1 80000000
mscan3_mclk 1 1 80000000
mscan2-mux0 1 1 320000000
mscan2-en0 1 1 320000000
mscan2_mclk_div 1 1 80000000
mscan2_mclk_out 1 1 80000000
mscan2_mclk 1 1 80000000
mscan1-mux0 1 1 320000000
mscan1-en0 1 1 320000000
mscan1_mclk_div 1 1 16000000
mscan1_mclk_out 1 1 16000000
mscan1_mclk 2 2 16000000
mscan0-mux0 1 1 320000000
mscan0-en0 1 1 320000000
mscan0_mclk_div 1 1 16000000
mscan0_mclk_out 1 1 16000000
mscan0_mclk 2 2 16000000
psc11-mux0 0 0 320000000
psc11-en0 0 0 320000000
psc11_mclk_div 0 0 80000000
psc11_mclk_out 0 0 80000000
psc11_mclk 0 0 80000000
psc10-mux0 0 0 320000000
psc10-en0 0 0 320000000
psc10_mclk_div 0 0 80000000
psc10_mclk_out 0 0 80000000
psc10_mclk 0 0 80000000
psc9-mux0 0 0 320000000
psc9-en0 0 0 320000000
psc9_mclk_div 0 0 80000000
psc9_mclk_out 0 0 80000000
psc9_mclk 0 0 80000000
psc8-mux0 0 0 320000000
psc8-en0 0 0 320000000
psc8_mclk_div 0 0 80000000
psc8_mclk_out 0 0 80000000
psc8_mclk 0 0 80000000
psc7-mux0 1 1 320000000
psc7-en0 1 1 320000000
psc7_mclk_div 1 1 80000000
psc7_mclk_out 1 1 80000000
psc7_mclk 1 1 80000000
psc6-mux0 0 0 320000000
psc6-en0 0 0 320000000
psc6_mclk_div 0 0 80000000
psc6_mclk_out 0 0 80000000
psc6_mclk 0 0 80000000
psc5-mux0 1 1 320000000
psc5-en0 1 1 320000000
psc5_mclk_div 1 1 80000000
psc5_mclk_out 1 1 80000000
psc5_mclk 1 1 80000000
psc4-mux0 1 1 320000000
psc4-en0 1 1 320000000
psc4_mclk_div 1 1 80000000
psc4_mclk_out 1 1 80000000
psc4_mclk 1 1 80000000
psc3-mux0 1 1 320000000
psc3-en0 1 1 320000000
psc3_mclk_div 1 1 80000000
psc3_mclk_out 1 1 80000000
psc3_mclk 2 2 80000000
psc2-mux0 0 0 320000000
psc2-en0 0 0 320000000
psc2_mclk_div 0 0 80000000
psc2_mclk_out 0 0 80000000
psc2_mclk 0 0 80000000
psc1-mux0 0 0 320000000
psc1-en0 0 0 320000000
psc1_mclk_div 0 0 80000000
psc1_mclk_out 0 0 80000000
psc1_mclk 0 0 80000000
psc0-mux0 0 0 320000000
psc0-en0 0 0 320000000
psc0_mclk_div 0 0 80000000
psc0_mclk_out 0 0 80000000
psc0_mclk 0 0 80000000
ddr-ug 1 1 160000000
ddr 1 1 160000000
csb 4 4 160000000
viu 0 0 160000000
iim 0 0 160000000
usb2 0 0 160000000
usb1 0 0 160000000
axe 0 0 160000000
pci-ug 0 0 26666666
pci 0 0 26666666
mbx-bus-ug 0 0 80000000
mbx-bus 0 0 80000000
mbx-ug 0 0 80000000
mbx 0 0 80000000
mbx-3d-ug 0 0 80000000
mbx-3d 0 0 80000000
e300 1 1 400000000
diu-x4 1 1 640000000
diu-ug 1 1 2509803
diu 2 2 2509803
sdhc-x4 1 1 640000000
sdhc-ug 1 1 53333333
sdhc-2 0 0 53333333
sdhc 1 1 53333333
ips 7 7 80000000
i2c 3 3 80000000
mem 1 1 80000000
fec 1 1 80000000
sata 0 0 80000000
psc-fifo 1 1 80000000
pata 0 0 80000000
lpc-ug 1 1 40000000
lpc 1 1 40000000
nfc-ug 0 0 40000000
nfc 0 0 40000000
--
1.7.10.4
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v2 00/24] add COMMON_CLK support for PowerPC MPC512x
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this series introduces support for the common clock framework (CCF,
COMMON_CLK Kconfig option) in the PowerPC based MPC512x platform
although the series does touch several subsystems -- serial, spi, net
(can, fs_enet), mtd (nfc), usb, i2c, media (viu), and dts -- all of the
patches are strictly clock related
it appears most appropriate to take this series through either the clk
or the powerpc trees after it has passed review and other subsystem
maintainers ACKed the clock setup related driver modifications
the series passes 'checkpatch.pl --strict' except for one warning which
cannot get resolved, since that either breaks compilation (the data type
is preset by the clk-provider.h API) or requires a cast which shadows
real mismatches:
WARNING: static const char * array should probably be static const char * const
#413: FILE: arch/powerpc/platforms/512x/clock-commonclk.c:335:
+static const char *parent_names_mux0[] = {
total: 0 errors, 1 warnings, 0 checks, 836 lines checked
each step in the series was build and run tested (with a display that is
attached to the DIU as well as SPI, with an SPI attached NOR flash, with
multiple UART ports such that one is not the boot console, with EEPROMs
attached to I2C, with an SD card, booting from network)
changes in v2:
- cleanup of the UART and SPI clock handling before the introduction of
common clock support for the platform, as incomplete clock handling
becomes fatal or more dangerous later (which in turn changes the
context of the "device tree lookup only" followup patch later)
- reordered the sequence of patches to keep the serial communication
related parts together (UART, SPI, and PSC FIFO changes after common
clock support was introduced)
- updated commit messages for the clock API use cleanup in the serial
communication drivers, updated comments and reworded commit messages
in the core clock driver to expand on the pre-enable workaround and
clkdev registration
- keep a reference to the PSC FIFO clock during use instead of looking
up the clock again in the uninit() routine
- remove the clkdev.h header file inclusion directive with the removal
of the clkdev registration call
Gerhard Sittig (24):
spi: mpc512x: cleanup clock API use
serial: mpc512x: cleanup clock API use
mtd: mpc5121_nfc: prepare clocks before enabling them
powerpc: mpc512x: array decl for MCLK registers in CCM
clk: wrap I/O access for improved portability
dts: mpc512x: prepare for preprocessor support
dts: mpc512x: introduce dt-bindings/clock/ header
dts: mpc512x: add clock related device tree specs
clk: mpc512x: introduce COMMON_CLK for MPC512x
dts: mpc512x: add clock specs for client lookups
spi: mpc512x: remove now obsolete clock lookup name
serial: mpc512x: remove now obsolete clock lookup name
clk: mpc512x: remove now obsolete clkdev registration
serial: mpc512x: setup the PSC FIFO clock as well
net: can: mscan: add a comment on reg to idx mapping
net: can: mscan: make mpc512x code use common clock
powerpc/mpc512x: improve DIU related clock setup
i2c: mpc: OF clock lookup for MPC512x
USB: fsl-mph-dr-of: OF clock lookup, prepare and enable
fs_enet: OF clock lookup (non-fatal), prepare and enable
[media] fsl-viu: OF clock lookup, prepare before enable
powerpc/fsl-pci: OF clock lookup, prepare before enable
clk: mpc512x: switch to COMMON_CLK, remove PPC_CLOCK
net: can: mscan: remove MPC512x non-COMMON_CLK code path
arch/powerpc/boot/dts/ac14xx.dts | 9 +-
arch/powerpc/boot/dts/include/dt-bindings | 1 +
arch/powerpc/boot/dts/mpc5121.dtsi | 94 ++-
arch/powerpc/boot/dts/mpc5121ads.dts | 2 +-
arch/powerpc/boot/dts/pdm360ng.dts | 2 +-
arch/powerpc/include/asm/mpc5121.h | 18 +-
arch/powerpc/platforms/512x/Kconfig | 2 +-
arch/powerpc/platforms/512x/Makefile | 3 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 761 ++++++++++++++++++++
arch/powerpc/platforms/512x/clock.c | 753 -------------------
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++--
arch/powerpc/sysdev/fsl_pci.c | 15 +
drivers/clk/clk-divider.c | 6 +-
drivers/clk/clk-gate.c | 6 +-
drivers/clk/clk-mux.c | 6 +-
drivers/i2c/busses/i2c-mpc.c | 9 +
drivers/media/platform/fsl-viu.c | 12 +-
drivers/mtd/nand/mpc5121_nfc.c | 4 +-
drivers/net/can/mscan/mpc5xxx_can.c | 234 +++---
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 27 +-
drivers/spi/spi-mpc512x-psc.c | 45 +-
drivers/tty/serial/mpc52xx_uart.c | 137 +++-
drivers/usb/host/fsl-mph-dr-of.c | 24 +-
include/dt-bindings/clock/mpc512x-clock.h | 59 ++
include/linux/clk-provider.h | 33 +
include/linux/fs_enet_pd.h | 3 +
26 files changed, 1392 insertions(+), 1038 deletions(-)
create mode 120000 arch/powerpc/boot/dts/include/dt-bindings
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
delete mode 100644 arch/powerpc/platforms/512x/clock.c
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
# uname -srm
Linux 3.11.0-rc1-00024-g96ff9fe ppc
# cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
ac97 0 0 24567000
spdif_rx_in 0 0 0
spdif_tx_in 0 0 0
psc_mclk_in 0 0 25000000
dummy 1 1 0
osc 1 1 25000000
ref 1 1 25000000
sys 10 10 320000000
spdif-mux0 0 0 320000000
spdif-en0 0 0 320000000
spdif_mclk_div 0 0 80000000
spdif_mclk_out 0 0 80000000
spdif_mclk 0 0 80000000
mscan3-mux0 1 1 320000000
mscan3-en0 1 1 320000000
mscan3_mclk_div 1 1 80000000
mscan3_mclk_out 1 1 80000000
mscan3_mclk 1 1 80000000
mscan2-mux0 1 1 320000000
mscan2-en0 1 1 320000000
mscan2_mclk_div 1 1 80000000
mscan2_mclk_out 1 1 80000000
mscan2_mclk 1 1 80000000
mscan1-mux0 1 1 320000000
mscan1-en0 1 1 320000000
mscan1_mclk_div 1 1 16000000
mscan1_mclk_out 1 1 16000000
mscan1_mclk 2 2 16000000
mscan0-mux0 1 1 320000000
mscan0-en0 1 1 320000000
mscan0_mclk_div 1 1 16000000
mscan0_mclk_out 1 1 16000000
mscan0_mclk 2 2 16000000
psc11-mux0 0 0 320000000
psc11-en0 0 0 320000000
psc11_mclk_div 0 0 80000000
psc11_mclk_out 0 0 80000000
psc11_mclk 0 0 80000000
psc10-mux0 0 0 320000000
psc10-en0 0 0 320000000
psc10_mclk_div 0 0 80000000
psc10_mclk_out 0 0 80000000
psc10_mclk 0 0 80000000
psc9-mux0 0 0 320000000
psc9-en0 0 0 320000000
psc9_mclk_div 0 0 80000000
psc9_mclk_out 0 0 80000000
psc9_mclk 0 0 80000000
psc8-mux0 0 0 320000000
psc8-en0 0 0 320000000
psc8_mclk_div 0 0 80000000
psc8_mclk_out 0 0 80000000
psc8_mclk 0 0 80000000
psc7-mux0 1 1 320000000
psc7-en0 1 1 320000000
psc7_mclk_div 1 1 80000000
psc7_mclk_out 1 1 80000000
psc7_mclk 1 1 80000000
psc6-mux0 0 0 320000000
psc6-en0 0 0 320000000
psc6_mclk_div 0 0 80000000
psc6_mclk_out 0 0 80000000
psc6_mclk 0 0 80000000
psc5-mux0 1 1 320000000
psc5-en0 1 1 320000000
psc5_mclk_div 1 1 80000000
psc5_mclk_out 1 1 80000000
psc5_mclk 1 1 80000000
psc4-mux0 1 1 320000000
psc4-en0 1 1 320000000
psc4_mclk_div 1 1 80000000
psc4_mclk_out 1 1 80000000
psc4_mclk 1 1 80000000
psc3-mux0 1 1 320000000
psc3-en0 1 1 320000000
psc3_mclk_div 1 1 80000000
psc3_mclk_out 1 1 80000000
psc3_mclk 2 2 80000000
psc2-mux0 0 0 320000000
psc2-en0 0 0 320000000
psc2_mclk_div 0 0 80000000
psc2_mclk_out 0 0 80000000
psc2_mclk 0 0 80000000
psc1-mux0 0 0 320000000
psc1-en0 0 0 320000000
psc1_mclk_div 0 0 80000000
psc1_mclk_out 0 0 80000000
psc1_mclk 0 0 80000000
psc0-mux0 0 0 320000000
psc0-en0 0 0 320000000
psc0_mclk_div 0 0 80000000
psc0_mclk_out 0 0 80000000
psc0_mclk 0 0 80000000
ddr-ug 1 1 160000000
ddr 1 1 160000000
csb 4 4 160000000
viu 0 0 160000000
iim 0 0 160000000
usb2 0 0 160000000
usb1 0 0 160000000
axe 0 0 160000000
pci-ug 0 0 26666666
pci 0 0 26666666
mbx-bus-ug 0 0 80000000
mbx-bus 0 0 80000000
mbx-ug 0 0 80000000
mbx 0 0 80000000
mbx-3d-ug 0 0 80000000
mbx-3d 0 0 80000000
e300 1 1 400000000
diu-x4 1 1 640000000
diu-ug 1 1 2509803
diu 2 2 2509803
sdhc-x4 1 1 640000000
sdhc-ug 1 1 53333333
sdhc-2 0 0 53333333
sdhc 1 1 53333333
ips 7 7 80000000
i2c 3 3 80000000
mem 1 1 80000000
fec 1 1 80000000
sata 0 0 80000000
psc-fifo 1 1 80000000
pata 0 0 80000000
lpc-ug 1 1 40000000
lpc 1 1 40000000
nfc-ug 0 0 40000000
nfc 0 0 40000000
--
1.7.10.4
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v2 00/24] add COMMON_CLK support for PowerPC MPC512x
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
this series introduces support for the common clock framework (CCF,
COMMON_CLK Kconfig option) in the PowerPC based MPC512x platform
although the series does touch several subsystems -- serial, spi, net
(can, fs_enet), mtd (nfc), usb, i2c, media (viu), and dts -- all of the
patches are strictly clock related
it appears most appropriate to take this series through either the clk
or the powerpc trees after it has passed review and other subsystem
maintainers ACKed the clock setup related driver modifications
the series passes 'checkpatch.pl --strict' except for one warning which
cannot get resolved, since that either breaks compilation (the data type
is preset by the clk-provider.h API) or requires a cast which shadows
real mismatches:
WARNING: static const char * array should probably be static const char * const
#413: FILE: arch/powerpc/platforms/512x/clock-commonclk.c:335:
+static const char *parent_names_mux0[] = {
total: 0 errors, 1 warnings, 0 checks, 836 lines checked
each step in the series was build and run tested (with a display that is
attached to the DIU as well as SPI, with an SPI attached NOR flash, with
multiple UART ports such that one is not the boot console, with EEPROMs
attached to I2C, with an SD card, booting from network)
changes in v2:
- cleanup of the UART and SPI clock handling before the introduction of
common clock support for the platform, as incomplete clock handling
becomes fatal or more dangerous later (which in turn changes the
context of the "device tree lookup only" followup patch later)
- reordered the sequence of patches to keep the serial communication
related parts together (UART, SPI, and PSC FIFO changes after common
clock support was introduced)
- updated commit messages for the clock API use cleanup in the serial
communication drivers, updated comments and reworded commit messages
in the core clock driver to expand on the pre-enable workaround and
clkdev registration
- keep a reference to the PSC FIFO clock during use instead of looking
up the clock again in the uninit() routine
- remove the clkdev.h header file inclusion directive with the removal
of the clkdev registration call
Gerhard Sittig (24):
spi: mpc512x: cleanup clock API use
serial: mpc512x: cleanup clock API use
mtd: mpc5121_nfc: prepare clocks before enabling them
powerpc: mpc512x: array decl for MCLK registers in CCM
clk: wrap I/O access for improved portability
dts: mpc512x: prepare for preprocessor support
dts: mpc512x: introduce dt-bindings/clock/ header
dts: mpc512x: add clock related device tree specs
clk: mpc512x: introduce COMMON_CLK for MPC512x
dts: mpc512x: add clock specs for client lookups
spi: mpc512x: remove now obsolete clock lookup name
serial: mpc512x: remove now obsolete clock lookup name
clk: mpc512x: remove now obsolete clkdev registration
serial: mpc512x: setup the PSC FIFO clock as well
net: can: mscan: add a comment on reg to idx mapping
net: can: mscan: make mpc512x code use common clock
powerpc/mpc512x: improve DIU related clock setup
i2c: mpc: OF clock lookup for MPC512x
USB: fsl-mph-dr-of: OF clock lookup, prepare and enable
fs_enet: OF clock lookup (non-fatal), prepare and enable
[media] fsl-viu: OF clock lookup, prepare before enable
powerpc/fsl-pci: OF clock lookup, prepare before enable
clk: mpc512x: switch to COMMON_CLK, remove PPC_CLOCK
net: can: mscan: remove MPC512x non-COMMON_CLK code path
arch/powerpc/boot/dts/ac14xx.dts | 9 +-
arch/powerpc/boot/dts/include/dt-bindings | 1 +
arch/powerpc/boot/dts/mpc5121.dtsi | 94 ++-
arch/powerpc/boot/dts/mpc5121ads.dts | 2 +-
arch/powerpc/boot/dts/pdm360ng.dts | 2 +-
arch/powerpc/include/asm/mpc5121.h | 18 +-
arch/powerpc/platforms/512x/Kconfig | 2 +-
arch/powerpc/platforms/512x/Makefile | 3 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 761 ++++++++++++++++++++
arch/powerpc/platforms/512x/clock.c | 753 -------------------
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++--
arch/powerpc/sysdev/fsl_pci.c | 15 +
drivers/clk/clk-divider.c | 6 +-
drivers/clk/clk-gate.c | 6 +-
drivers/clk/clk-mux.c | 6 +-
drivers/i2c/busses/i2c-mpc.c | 9 +
drivers/media/platform/fsl-viu.c | 12 +-
drivers/mtd/nand/mpc5121_nfc.c | 4 +-
drivers/net/can/mscan/mpc5xxx_can.c | 234 +++---
.../net/ethernet/freescale/fs_enet/fs_enet-main.c | 27 +-
drivers/spi/spi-mpc512x-psc.c | 45 +-
drivers/tty/serial/mpc52xx_uart.c | 137 +++-
drivers/usb/host/fsl-mph-dr-of.c | 24 +-
include/dt-bindings/clock/mpc512x-clock.h | 59 ++
include/linux/clk-provider.h | 33 +
include/linux/fs_enet_pd.h | 3 +
26 files changed, 1392 insertions(+), 1038 deletions(-)
create mode 120000 arch/powerpc/boot/dts/include/dt-bindings
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
delete mode 100644 arch/powerpc/platforms/512x/clock.c
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
# uname -srm
Linux 3.11.0-rc1-00024-g96ff9fe ppc
# cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
ac97 0 0 24567000
spdif_rx_in 0 0 0
spdif_tx_in 0 0 0
psc_mclk_in 0 0 25000000
dummy 1 1 0
osc 1 1 25000000
ref 1 1 25000000
sys 10 10 320000000
spdif-mux0 0 0 320000000
spdif-en0 0 0 320000000
spdif_mclk_div 0 0 80000000
spdif_mclk_out 0 0 80000000
spdif_mclk 0 0 80000000
mscan3-mux0 1 1 320000000
mscan3-en0 1 1 320000000
mscan3_mclk_div 1 1 80000000
mscan3_mclk_out 1 1 80000000
mscan3_mclk 1 1 80000000
mscan2-mux0 1 1 320000000
mscan2-en0 1 1 320000000
mscan2_mclk_div 1 1 80000000
mscan2_mclk_out 1 1 80000000
mscan2_mclk 1 1 80000000
mscan1-mux0 1 1 320000000
mscan1-en0 1 1 320000000
mscan1_mclk_div 1 1 16000000
mscan1_mclk_out 1 1 16000000
mscan1_mclk 2 2 16000000
mscan0-mux0 1 1 320000000
mscan0-en0 1 1 320000000
mscan0_mclk_div 1 1 16000000
mscan0_mclk_out 1 1 16000000
mscan0_mclk 2 2 16000000
psc11-mux0 0 0 320000000
psc11-en0 0 0 320000000
psc11_mclk_div 0 0 80000000
psc11_mclk_out 0 0 80000000
psc11_mclk 0 0 80000000
psc10-mux0 0 0 320000000
psc10-en0 0 0 320000000
psc10_mclk_div 0 0 80000000
psc10_mclk_out 0 0 80000000
psc10_mclk 0 0 80000000
psc9-mux0 0 0 320000000
psc9-en0 0 0 320000000
psc9_mclk_div 0 0 80000000
psc9_mclk_out 0 0 80000000
psc9_mclk 0 0 80000000
psc8-mux0 0 0 320000000
psc8-en0 0 0 320000000
psc8_mclk_div 0 0 80000000
psc8_mclk_out 0 0 80000000
psc8_mclk 0 0 80000000
psc7-mux0 1 1 320000000
psc7-en0 1 1 320000000
psc7_mclk_div 1 1 80000000
psc7_mclk_out 1 1 80000000
psc7_mclk 1 1 80000000
psc6-mux0 0 0 320000000
psc6-en0 0 0 320000000
psc6_mclk_div 0 0 80000000
psc6_mclk_out 0 0 80000000
psc6_mclk 0 0 80000000
psc5-mux0 1 1 320000000
psc5-en0 1 1 320000000
psc5_mclk_div 1 1 80000000
psc5_mclk_out 1 1 80000000
psc5_mclk 1 1 80000000
psc4-mux0 1 1 320000000
psc4-en0 1 1 320000000
psc4_mclk_div 1 1 80000000
psc4_mclk_out 1 1 80000000
psc4_mclk 1 1 80000000
psc3-mux0 1 1 320000000
psc3-en0 1 1 320000000
psc3_mclk_div 1 1 80000000
psc3_mclk_out 1 1 80000000
psc3_mclk 2 2 80000000
psc2-mux0 0 0 320000000
psc2-en0 0 0 320000000
psc2_mclk_div 0 0 80000000
psc2_mclk_out 0 0 80000000
psc2_mclk 0 0 80000000
psc1-mux0 0 0 320000000
psc1-en0 0 0 320000000
psc1_mclk_div 0 0 80000000
psc1_mclk_out 0 0 80000000
psc1_mclk 0 0 80000000
psc0-mux0 0 0 320000000
psc0-en0 0 0 320000000
psc0_mclk_div 0 0 80000000
psc0_mclk_out 0 0 80000000
psc0_mclk 0 0 80000000
ddr-ug 1 1 160000000
ddr 1 1 160000000
csb 4 4 160000000
viu 0 0 160000000
iim 0 0 160000000
usb2 0 0 160000000
usb1 0 0 160000000
axe 0 0 160000000
pci-ug 0 0 26666666
pci 0 0 26666666
mbx-bus-ug 0 0 80000000
mbx-bus 0 0 80000000
mbx-ug 0 0 80000000
mbx 0 0 80000000
mbx-3d-ug 0 0 80000000
mbx-3d 0 0 80000000
e300 1 1 400000000
diu-x4 1 1 640000000
diu-ug 1 1 2509803
diu 2 2 2509803
sdhc-x4 1 1 640000000
sdhc-ug 1 1 53333333
sdhc-2 0 0 53333333
sdhc 1 1 53333333
ips 7 7 80000000
i2c 3 3 80000000
mem 1 1 80000000
fec 1 1 80000000
sata 0 0 80000000
psc-fifo 1 1 80000000
pata 0 0 80000000
lpc-ug 1 1 40000000
lpc 1 1 40000000
nfc-ug 0 0 40000000
nfc 0 0 40000000
--
1.7.10.4
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v2 01/24] spi: mpc512x: cleanup clock API use
2013-07-18 17:00 ` Gerhard Sittig
(?)
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
cleanup the MPC512x SoC's SPI master's use of the clock API
- get, prepare, and enable the MCLK during probe; disable, unprepare and
put the MCLK upon remove; hold a reference to the clock over the
period of use
- fetch MCLK rate (reference) once during probe and slightly reword BCLK
(bitrate) determination to reduce redundancy as well as to not exceed
the maximum text line length
- stick with the PPC_CLOCK 'psc%d_mclk' name for clock lookup, only
switch to a fixed string later after device tree based clock lookup
will have become available
the omission in the clock handling previously went unnoticed, but will
become fatal in the common clock scenario
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
drivers/spi/spi-mpc512x-psc.c | 49 ++++++++++++++++++++++++++---------------
1 file changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 29fce6a..7a32373 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -38,7 +38,8 @@ struct mpc512x_psc_spi {
struct mpc512x_psc_fifo __iomem *fifo;
unsigned int irq;
u8 bits_per_word;
- u32 mclk;
+ struct clk *clk_mclk;
+ u32 mclk_rate;
struct completion txisrdone;
};
@@ -72,6 +73,7 @@ static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
struct mpc52xx_psc __iomem *psc = mps->psc;
u32 sicr;
u32 ccr;
+ int speed;
u16 bclkdiv;
sicr = in_be32(&psc->sicr);
@@ -95,10 +97,10 @@ static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
ccr = in_be32(&psc->ccr);
ccr &= 0xFF000000;
- if (cs->speed_hz)
- bclkdiv = (mps->mclk / cs->speed_hz) - 1;
- else
- bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
+ speed = cs->speed_hz;
+ if (!speed)
+ speed = 1000000; /* default 1MHz */
+ bclkdiv = (mps->mclk_rate / speed) - 1;
ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
out_be32(&psc->ccr, ccr);
@@ -386,19 +388,11 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
{
struct mpc52xx_psc __iomem *psc = mps->psc;
struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
- struct clk *spiclk;
- int ret = 0;
- char name[32];
u32 sicr;
u32 ccr;
+ int speed;
u16 bclkdiv;
- sprintf(name, "psc%d_mclk", master->bus_num);
- spiclk = clk_get(&master->dev, name);
- clk_enable(spiclk);
- mps->mclk = clk_get_rate(spiclk);
- clk_put(spiclk);
-
/* Reset the PSC into a known state */
out_8(&psc->command, MPC52xx_PSC_RST_RX);
out_8(&psc->command, MPC52xx_PSC_RST_TX);
@@ -425,7 +419,8 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
ccr = in_be32(&psc->ccr);
ccr &= 0xFF000000;
- bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
+ speed = 1000000; /* default 1MHz */
+ bclkdiv = (mps->mclk_rate / speed) - 1;
ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
out_be32(&psc->ccr, ccr);
@@ -445,7 +440,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
mps->bits_per_word = 8;
- return ret;
+ return 0;
}
static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
@@ -479,6 +474,8 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
struct spi_master *master;
int ret;
void *tempp;
+ int psc_num;
+ char clk_name[16];
master = spi_alloc_master(dev, sizeof *mps);
if (master == NULL)
@@ -521,16 +518,30 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
goto free_master;
init_completion(&mps->txisrdone);
+ psc_num = master->bus_num;
+ snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
+ mps->clk_mclk = clk_get(dev, clk_name);
+ if (IS_ERR(mps->clk_mclk))
+ goto free_irq;
+ ret = clk_prepare_enable(mps->clk_mclk);
+ if (ret)
+ goto free_putclk;
+ mps->mclk_rate = clk_get_rate(mps->clk_mclk);
+
ret = mpc512x_psc_spi_port_config(master, mps);
if (ret < 0)
- goto free_irq;
+ goto free_disclk;
ret = spi_register_master(master);
if (ret < 0)
- goto free_irq;
+ goto free_disclk;
return ret;
+free_disclk:
+ clk_disable_unprepare(mps->clk_mclk);
+free_putclk:
+ clk_put(mps->clk_mclk);
free_irq:
free_irq(mps->irq, mps);
free_master:
@@ -547,6 +558,8 @@ static int mpc512x_psc_spi_do_remove(struct device *dev)
struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
spi_unregister_master(master);
+ clk_disable_unprepare(mps->clk_mclk);
+ clk_put(mps->clk_mclk);
free_irq(mps->irq, mps);
if (mps->psc)
iounmap(mps->psc);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 01/24] spi: mpc512x: cleanup clock API use
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
cleanup the MPC512x SoC's SPI master's use of the clock API
- get, prepare, and enable the MCLK during probe; disable, unprepare and
put the MCLK upon remove; hold a reference to the clock over the
period of use
- fetch MCLK rate (reference) once during probe and slightly reword BCLK
(bitrate) determination to reduce redundancy as well as to not exceed
the maximum text line length
- stick with the PPC_CLOCK 'psc%d_mclk' name for clock lookup, only
switch to a fixed string later after device tree based clock lookup
will have become available
the omission in the clock handling previously went unnoticed, but will
become fatal in the common clock scenario
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/spi/spi-mpc512x-psc.c | 49 ++++++++++++++++++++++++++---------------
1 file changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 29fce6a..7a32373 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -38,7 +38,8 @@ struct mpc512x_psc_spi {
struct mpc512x_psc_fifo __iomem *fifo;
unsigned int irq;
u8 bits_per_word;
- u32 mclk;
+ struct clk *clk_mclk;
+ u32 mclk_rate;
struct completion txisrdone;
};
@@ -72,6 +73,7 @@ static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
struct mpc52xx_psc __iomem *psc = mps->psc;
u32 sicr;
u32 ccr;
+ int speed;
u16 bclkdiv;
sicr = in_be32(&psc->sicr);
@@ -95,10 +97,10 @@ static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
ccr = in_be32(&psc->ccr);
ccr &= 0xFF000000;
- if (cs->speed_hz)
- bclkdiv = (mps->mclk / cs->speed_hz) - 1;
- else
- bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
+ speed = cs->speed_hz;
+ if (!speed)
+ speed = 1000000; /* default 1MHz */
+ bclkdiv = (mps->mclk_rate / speed) - 1;
ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
out_be32(&psc->ccr, ccr);
@@ -386,19 +388,11 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
{
struct mpc52xx_psc __iomem *psc = mps->psc;
struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
- struct clk *spiclk;
- int ret = 0;
- char name[32];
u32 sicr;
u32 ccr;
+ int speed;
u16 bclkdiv;
- sprintf(name, "psc%d_mclk", master->bus_num);
- spiclk = clk_get(&master->dev, name);
- clk_enable(spiclk);
- mps->mclk = clk_get_rate(spiclk);
- clk_put(spiclk);
-
/* Reset the PSC into a known state */
out_8(&psc->command, MPC52xx_PSC_RST_RX);
out_8(&psc->command, MPC52xx_PSC_RST_TX);
@@ -425,7 +419,8 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
ccr = in_be32(&psc->ccr);
ccr &= 0xFF000000;
- bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
+ speed = 1000000; /* default 1MHz */
+ bclkdiv = (mps->mclk_rate / speed) - 1;
ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
out_be32(&psc->ccr, ccr);
@@ -445,7 +440,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
mps->bits_per_word = 8;
- return ret;
+ return 0;
}
static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
@@ -479,6 +474,8 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
struct spi_master *master;
int ret;
void *tempp;
+ int psc_num;
+ char clk_name[16];
master = spi_alloc_master(dev, sizeof *mps);
if (master == NULL)
@@ -521,16 +518,30 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
goto free_master;
init_completion(&mps->txisrdone);
+ psc_num = master->bus_num;
+ snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
+ mps->clk_mclk = clk_get(dev, clk_name);
+ if (IS_ERR(mps->clk_mclk))
+ goto free_irq;
+ ret = clk_prepare_enable(mps->clk_mclk);
+ if (ret)
+ goto free_putclk;
+ mps->mclk_rate = clk_get_rate(mps->clk_mclk);
+
ret = mpc512x_psc_spi_port_config(master, mps);
if (ret < 0)
- goto free_irq;
+ goto free_disclk;
ret = spi_register_master(master);
if (ret < 0)
- goto free_irq;
+ goto free_disclk;
return ret;
+free_disclk:
+ clk_disable_unprepare(mps->clk_mclk);
+free_putclk:
+ clk_put(mps->clk_mclk);
free_irq:
free_irq(mps->irq, mps);
free_master:
@@ -547,6 +558,8 @@ static int mpc512x_psc_spi_do_remove(struct device *dev)
struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
spi_unregister_master(master);
+ clk_disable_unprepare(mps->clk_mclk);
+ clk_put(mps->clk_mclk);
free_irq(mps->irq, mps);
if (mps->psc)
iounmap(mps->psc);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 01/24] spi: mpc512x: cleanup clock API use
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
cleanup the MPC512x SoC's SPI master's use of the clock API
- get, prepare, and enable the MCLK during probe; disable, unprepare and
put the MCLK upon remove; hold a reference to the clock over the
period of use
- fetch MCLK rate (reference) once during probe and slightly reword BCLK
(bitrate) determination to reduce redundancy as well as to not exceed
the maximum text line length
- stick with the PPC_CLOCK 'psc%d_mclk' name for clock lookup, only
switch to a fixed string later after device tree based clock lookup
will have become available
the omission in the clock handling previously went unnoticed, but will
become fatal in the common clock scenario
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/spi/spi-mpc512x-psc.c | 49 ++++++++++++++++++++++++++---------------
1 file changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 29fce6a..7a32373 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -38,7 +38,8 @@ struct mpc512x_psc_spi {
struct mpc512x_psc_fifo __iomem *fifo;
unsigned int irq;
u8 bits_per_word;
- u32 mclk;
+ struct clk *clk_mclk;
+ u32 mclk_rate;
struct completion txisrdone;
};
@@ -72,6 +73,7 @@ static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
struct mpc52xx_psc __iomem *psc = mps->psc;
u32 sicr;
u32 ccr;
+ int speed;
u16 bclkdiv;
sicr = in_be32(&psc->sicr);
@@ -95,10 +97,10 @@ static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
ccr = in_be32(&psc->ccr);
ccr &= 0xFF000000;
- if (cs->speed_hz)
- bclkdiv = (mps->mclk / cs->speed_hz) - 1;
- else
- bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
+ speed = cs->speed_hz;
+ if (!speed)
+ speed = 1000000; /* default 1MHz */
+ bclkdiv = (mps->mclk_rate / speed) - 1;
ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
out_be32(&psc->ccr, ccr);
@@ -386,19 +388,11 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
{
struct mpc52xx_psc __iomem *psc = mps->psc;
struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
- struct clk *spiclk;
- int ret = 0;
- char name[32];
u32 sicr;
u32 ccr;
+ int speed;
u16 bclkdiv;
- sprintf(name, "psc%d_mclk", master->bus_num);
- spiclk = clk_get(&master->dev, name);
- clk_enable(spiclk);
- mps->mclk = clk_get_rate(spiclk);
- clk_put(spiclk);
-
/* Reset the PSC into a known state */
out_8(&psc->command, MPC52xx_PSC_RST_RX);
out_8(&psc->command, MPC52xx_PSC_RST_TX);
@@ -425,7 +419,8 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
ccr = in_be32(&psc->ccr);
ccr &= 0xFF000000;
- bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
+ speed = 1000000; /* default 1MHz */
+ bclkdiv = (mps->mclk_rate / speed) - 1;
ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
out_be32(&psc->ccr, ccr);
@@ -445,7 +440,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
mps->bits_per_word = 8;
- return ret;
+ return 0;
}
static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
@@ -479,6 +474,8 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
struct spi_master *master;
int ret;
void *tempp;
+ int psc_num;
+ char clk_name[16];
master = spi_alloc_master(dev, sizeof *mps);
if (master == NULL)
@@ -521,16 +518,30 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
goto free_master;
init_completion(&mps->txisrdone);
+ psc_num = master->bus_num;
+ snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
+ mps->clk_mclk = clk_get(dev, clk_name);
+ if (IS_ERR(mps->clk_mclk))
+ goto free_irq;
+ ret = clk_prepare_enable(mps->clk_mclk);
+ if (ret)
+ goto free_putclk;
+ mps->mclk_rate = clk_get_rate(mps->clk_mclk);
+
ret = mpc512x_psc_spi_port_config(master, mps);
if (ret < 0)
- goto free_irq;
+ goto free_disclk;
ret = spi_register_master(master);
if (ret < 0)
- goto free_irq;
+ goto free_disclk;
return ret;
+free_disclk:
+ clk_disable_unprepare(mps->clk_mclk);
+free_putclk:
+ clk_put(mps->clk_mclk);
free_irq:
free_irq(mps->irq, mps);
free_master:
@@ -547,6 +558,8 @@ static int mpc512x_psc_spi_do_remove(struct device *dev)
struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
spi_unregister_master(master);
+ clk_disable_unprepare(mps->clk_mclk);
+ clk_put(mps->clk_mclk);
free_irq(mps->irq, mps);
if (mps->psc)
iounmap(mps->psc);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 02/24] serial: mpc512x: cleanup clock API use
2013-07-18 17:00 ` Gerhard Sittig
(?)
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
cleanup the clock API use of the UART driver which is shared among the
MPC512x and the MPC5200 platforms
- get, prepare, and enable the MCLK during port allocation; disable,
unprepare and put the MCLK upon port release; hold a reference to the
clock over the period of use; check for and propagate enable errors
- fix a buffer overflow for clock names with two digit PSC index numbers
- stick with the PPC_CLOCK 'psc%d_mclk' name for clock lookup, only
switch to a fixed string later after device tree based clock lookup
will have become available
the omission in the clock handling previously went unnoticed, but will
become fatal in the common clock scenario
to achieve support for MPC512x which is neutral to MPC5200, the
modification was done as follows
- introduce "clock alloc" and "clock release" routines in addition to
the previous "clock enable/disable" routine in the psc_ops struct
- make the clock allocation a part of the port request (resource
allocation), and make clock release a part of the port release, such
that essential resources get allocated early
- just enable/disable the clock from within the .clock() callback
without any allocation or preparation as the former implementation
did, since this routine is called from within the startup and shutdown
callbacks
- all of the above remains a NOP for the MPC5200 platform (no callbacks
are provided on that platform)
- implementation note: the clock gets enabled upon allocation already
just in case the clock is not only required for bitrate generation but
for register access as well
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
drivers/tty/serial/mpc52xx_uart.c | 100 ++++++++++++++++++++++++++++++-------
1 file changed, 83 insertions(+), 17 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index e1280a2..98a1f43 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -107,6 +107,8 @@ struct psc_ops {
unsigned int (*set_baudrate)(struct uart_port *port,
struct ktermios *new,
struct ktermios *old);
+ int (*clock_alloc)(struct uart_port *port);
+ void (*clock_relse)(struct uart_port *port);
int (*clock)(struct uart_port *port, int enable);
int (*fifoc_init)(void);
void (*fifoc_uninit)(void);
@@ -616,31 +618,75 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
return IRQ_NONE;
}
-static int mpc512x_psc_clock(struct uart_port *port, int enable)
+static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
+
+/* called from within the .request_port() callback (allocation) */
+static int mpc512x_psc_alloc_clock(struct uart_port *port)
{
- struct clk *psc_clk;
int psc_num;
- char clk_name[10];
+ char clk_name[16];
+ struct clk *clk;
+ int err;
+
+ psc_num = (port->mapbase & 0xf00) >> 8;
+ snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
+ clk = clk_get(port->dev, clk_name);
+ if (IS_ERR(clk)) {
+ dev_err(port->dev, "Failed to get MCLK!\n");
+ return PTR_ERR(clk);
+ }
+ err = clk_prepare_enable(clk);
+ if (err) {
+ dev_err(port->dev, "Failed to enable MCLK!\n");
+ clk_put(clk);
+ return err;
+ }
+ psc_mclk_clk[psc_num] = clk;
+ return 0;
+}
+
+/* called from within the .release_port() callback (release) */
+static void mpc512x_psc_relse_clock(struct uart_port *port)
+{
+ int psc_num;
+ struct clk *clk;
+
+ psc_num = (port->mapbase & 0xf00) >> 8;
+ clk = psc_mclk_clk[psc_num];
+ if (clk) {
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+ psc_mclk_clk[psc_num] = NULL;
+ }
+}
+
+/* implementation of the .clock() callback (enable/disable) */
+static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
+{
+ int psc_num;
+ struct clk *psc_clk;
+ int ret;
if (uart_console(port))
return 0;
psc_num = (port->mapbase & 0xf00) >> 8;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- psc_clk = clk_get(port->dev, clk_name);
- if (IS_ERR(psc_clk)) {
+ psc_clk = psc_mclk_clk[psc_num];
+ if (!psc_clk) {
dev_err(port->dev, "Failed to get PSC clock entry!\n");
return -ENODEV;
}
- dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
-
- if (enable)
- clk_enable(psc_clk);
- else
+ dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
+ if (enable) {
+ ret = clk_enable(psc_clk);
+ if (ret)
+ dev_err(port->dev, "Failed to enable MCLK!\n");
+ return ret;
+ } else {
clk_disable(psc_clk);
-
- return 0;
+ return 0;
+ }
}
static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
@@ -873,7 +919,9 @@ static struct psc_ops mpc5125_psc_ops = {
.cw_disable_ints = mpc5125_psc_cw_disable_ints,
.cw_restore_ints = mpc5125_psc_cw_restore_ints,
.set_baudrate = mpc5125_psc_set_baudrate,
- .clock = mpc512x_psc_clock,
+ .clock_alloc = mpc512x_psc_alloc_clock,
+ .clock_relse = mpc512x_psc_relse_clock,
+ .clock = mpc512x_psc_endis_clock,
.fifoc_init = mpc512x_psc_fifoc_init,
.fifoc_uninit = mpc512x_psc_fifoc_uninit,
.get_irq = mpc512x_psc_get_irq,
@@ -906,7 +954,9 @@ static struct psc_ops mpc512x_psc_ops = {
.cw_disable_ints = mpc512x_psc_cw_disable_ints,
.cw_restore_ints = mpc512x_psc_cw_restore_ints,
.set_baudrate = mpc512x_psc_set_baudrate,
- .clock = mpc512x_psc_clock,
+ .clock_alloc = mpc512x_psc_alloc_clock,
+ .clock_relse = mpc512x_psc_relse_clock,
+ .clock = mpc512x_psc_endis_clock,
.fifoc_init = mpc512x_psc_fifoc_init,
.fifoc_uninit = mpc512x_psc_fifoc_uninit,
.get_irq = mpc512x_psc_get_irq,
@@ -1166,6 +1216,9 @@ mpc52xx_uart_type(struct uart_port *port)
static void
mpc52xx_uart_release_port(struct uart_port *port)
{
+ if (psc_ops->clock_relse)
+ psc_ops->clock_relse(port);
+
/* remapped by us ? */
if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
@@ -1190,11 +1243,24 @@ mpc52xx_uart_request_port(struct uart_port *port)
err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
"mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
- if (err && (port->flags & UPF_IOREMAP)) {
+ if (err)
+ goto out_membase;
+
+ if (psc_ops->clock_alloc) {
+ err = psc_ops->clock_alloc(port);
+ if (err)
+ goto out_mapregion;
+ }
+
+ return 0;
+
+out_mapregion:
+ release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
+out_membase:
+ if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
port->membase = NULL;
}
-
return err;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 02/24] serial: mpc512x: cleanup clock API use
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
cleanup the clock API use of the UART driver which is shared among the
MPC512x and the MPC5200 platforms
- get, prepare, and enable the MCLK during port allocation; disable,
unprepare and put the MCLK upon port release; hold a reference to the
clock over the period of use; check for and propagate enable errors
- fix a buffer overflow for clock names with two digit PSC index numbers
- stick with the PPC_CLOCK 'psc%d_mclk' name for clock lookup, only
switch to a fixed string later after device tree based clock lookup
will have become available
the omission in the clock handling previously went unnoticed, but will
become fatal in the common clock scenario
to achieve support for MPC512x which is neutral to MPC5200, the
modification was done as follows
- introduce "clock alloc" and "clock release" routines in addition to
the previous "clock enable/disable" routine in the psc_ops struct
- make the clock allocation a part of the port request (resource
allocation), and make clock release a part of the port release, such
that essential resources get allocated early
- just enable/disable the clock from within the .clock() callback
without any allocation or preparation as the former implementation
did, since this routine is called from within the startup and shutdown
callbacks
- all of the above remains a NOP for the MPC5200 platform (no callbacks
are provided on that platform)
- implementation note: the clock gets enabled upon allocation already
just in case the clock is not only required for bitrate generation but
for register access as well
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/tty/serial/mpc52xx_uart.c | 100 ++++++++++++++++++++++++++++++-------
1 file changed, 83 insertions(+), 17 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index e1280a2..98a1f43 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -107,6 +107,8 @@ struct psc_ops {
unsigned int (*set_baudrate)(struct uart_port *port,
struct ktermios *new,
struct ktermios *old);
+ int (*clock_alloc)(struct uart_port *port);
+ void (*clock_relse)(struct uart_port *port);
int (*clock)(struct uart_port *port, int enable);
int (*fifoc_init)(void);
void (*fifoc_uninit)(void);
@@ -616,31 +618,75 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
return IRQ_NONE;
}
-static int mpc512x_psc_clock(struct uart_port *port, int enable)
+static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
+
+/* called from within the .request_port() callback (allocation) */
+static int mpc512x_psc_alloc_clock(struct uart_port *port)
{
- struct clk *psc_clk;
int psc_num;
- char clk_name[10];
+ char clk_name[16];
+ struct clk *clk;
+ int err;
+
+ psc_num = (port->mapbase & 0xf00) >> 8;
+ snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
+ clk = clk_get(port->dev, clk_name);
+ if (IS_ERR(clk)) {
+ dev_err(port->dev, "Failed to get MCLK!\n");
+ return PTR_ERR(clk);
+ }
+ err = clk_prepare_enable(clk);
+ if (err) {
+ dev_err(port->dev, "Failed to enable MCLK!\n");
+ clk_put(clk);
+ return err;
+ }
+ psc_mclk_clk[psc_num] = clk;
+ return 0;
+}
+
+/* called from within the .release_port() callback (release) */
+static void mpc512x_psc_relse_clock(struct uart_port *port)
+{
+ int psc_num;
+ struct clk *clk;
+
+ psc_num = (port->mapbase & 0xf00) >> 8;
+ clk = psc_mclk_clk[psc_num];
+ if (clk) {
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+ psc_mclk_clk[psc_num] = NULL;
+ }
+}
+
+/* implementation of the .clock() callback (enable/disable) */
+static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
+{
+ int psc_num;
+ struct clk *psc_clk;
+ int ret;
if (uart_console(port))
return 0;
psc_num = (port->mapbase & 0xf00) >> 8;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- psc_clk = clk_get(port->dev, clk_name);
- if (IS_ERR(psc_clk)) {
+ psc_clk = psc_mclk_clk[psc_num];
+ if (!psc_clk) {
dev_err(port->dev, "Failed to get PSC clock entry!\n");
return -ENODEV;
}
- dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
-
- if (enable)
- clk_enable(psc_clk);
- else
+ dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
+ if (enable) {
+ ret = clk_enable(psc_clk);
+ if (ret)
+ dev_err(port->dev, "Failed to enable MCLK!\n");
+ return ret;
+ } else {
clk_disable(psc_clk);
-
- return 0;
+ return 0;
+ }
}
static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
@@ -873,7 +919,9 @@ static struct psc_ops mpc5125_psc_ops = {
.cw_disable_ints = mpc5125_psc_cw_disable_ints,
.cw_restore_ints = mpc5125_psc_cw_restore_ints,
.set_baudrate = mpc5125_psc_set_baudrate,
- .clock = mpc512x_psc_clock,
+ .clock_alloc = mpc512x_psc_alloc_clock,
+ .clock_relse = mpc512x_psc_relse_clock,
+ .clock = mpc512x_psc_endis_clock,
.fifoc_init = mpc512x_psc_fifoc_init,
.fifoc_uninit = mpc512x_psc_fifoc_uninit,
.get_irq = mpc512x_psc_get_irq,
@@ -906,7 +954,9 @@ static struct psc_ops mpc512x_psc_ops = {
.cw_disable_ints = mpc512x_psc_cw_disable_ints,
.cw_restore_ints = mpc512x_psc_cw_restore_ints,
.set_baudrate = mpc512x_psc_set_baudrate,
- .clock = mpc512x_psc_clock,
+ .clock_alloc = mpc512x_psc_alloc_clock,
+ .clock_relse = mpc512x_psc_relse_clock,
+ .clock = mpc512x_psc_endis_clock,
.fifoc_init = mpc512x_psc_fifoc_init,
.fifoc_uninit = mpc512x_psc_fifoc_uninit,
.get_irq = mpc512x_psc_get_irq,
@@ -1166,6 +1216,9 @@ mpc52xx_uart_type(struct uart_port *port)
static void
mpc52xx_uart_release_port(struct uart_port *port)
{
+ if (psc_ops->clock_relse)
+ psc_ops->clock_relse(port);
+
/* remapped by us ? */
if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
@@ -1190,11 +1243,24 @@ mpc52xx_uart_request_port(struct uart_port *port)
err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
"mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
- if (err && (port->flags & UPF_IOREMAP)) {
+ if (err)
+ goto out_membase;
+
+ if (psc_ops->clock_alloc) {
+ err = psc_ops->clock_alloc(port);
+ if (err)
+ goto out_mapregion;
+ }
+
+ return 0;
+
+out_mapregion:
+ release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
+out_membase:
+ if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
port->membase = NULL;
}
-
return err;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 02/24] serial: mpc512x: cleanup clock API use
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
cleanup the clock API use of the UART driver which is shared among the
MPC512x and the MPC5200 platforms
- get, prepare, and enable the MCLK during port allocation; disable,
unprepare and put the MCLK upon port release; hold a reference to the
clock over the period of use; check for and propagate enable errors
- fix a buffer overflow for clock names with two digit PSC index numbers
- stick with the PPC_CLOCK 'psc%d_mclk' name for clock lookup, only
switch to a fixed string later after device tree based clock lookup
will have become available
the omission in the clock handling previously went unnoticed, but will
become fatal in the common clock scenario
to achieve support for MPC512x which is neutral to MPC5200, the
modification was done as follows
- introduce "clock alloc" and "clock release" routines in addition to
the previous "clock enable/disable" routine in the psc_ops struct
- make the clock allocation a part of the port request (resource
allocation), and make clock release a part of the port release, such
that essential resources get allocated early
- just enable/disable the clock from within the .clock() callback
without any allocation or preparation as the former implementation
did, since this routine is called from within the startup and shutdown
callbacks
- all of the above remains a NOP for the MPC5200 platform (no callbacks
are provided on that platform)
- implementation note: the clock gets enabled upon allocation already
just in case the clock is not only required for bitrate generation but
for register access as well
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/tty/serial/mpc52xx_uart.c | 100 ++++++++++++++++++++++++++++++-------
1 file changed, 83 insertions(+), 17 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index e1280a2..98a1f43 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -107,6 +107,8 @@ struct psc_ops {
unsigned int (*set_baudrate)(struct uart_port *port,
struct ktermios *new,
struct ktermios *old);
+ int (*clock_alloc)(struct uart_port *port);
+ void (*clock_relse)(struct uart_port *port);
int (*clock)(struct uart_port *port, int enable);
int (*fifoc_init)(void);
void (*fifoc_uninit)(void);
@@ -616,31 +618,75 @@ static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
return IRQ_NONE;
}
-static int mpc512x_psc_clock(struct uart_port *port, int enable)
+static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
+
+/* called from within the .request_port() callback (allocation) */
+static int mpc512x_psc_alloc_clock(struct uart_port *port)
{
- struct clk *psc_clk;
int psc_num;
- char clk_name[10];
+ char clk_name[16];
+ struct clk *clk;
+ int err;
+
+ psc_num = (port->mapbase & 0xf00) >> 8;
+ snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
+ clk = clk_get(port->dev, clk_name);
+ if (IS_ERR(clk)) {
+ dev_err(port->dev, "Failed to get MCLK!\n");
+ return PTR_ERR(clk);
+ }
+ err = clk_prepare_enable(clk);
+ if (err) {
+ dev_err(port->dev, "Failed to enable MCLK!\n");
+ clk_put(clk);
+ return err;
+ }
+ psc_mclk_clk[psc_num] = clk;
+ return 0;
+}
+
+/* called from within the .release_port() callback (release) */
+static void mpc512x_psc_relse_clock(struct uart_port *port)
+{
+ int psc_num;
+ struct clk *clk;
+
+ psc_num = (port->mapbase & 0xf00) >> 8;
+ clk = psc_mclk_clk[psc_num];
+ if (clk) {
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+ psc_mclk_clk[psc_num] = NULL;
+ }
+}
+
+/* implementation of the .clock() callback (enable/disable) */
+static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
+{
+ int psc_num;
+ struct clk *psc_clk;
+ int ret;
if (uart_console(port))
return 0;
psc_num = (port->mapbase & 0xf00) >> 8;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- psc_clk = clk_get(port->dev, clk_name);
- if (IS_ERR(psc_clk)) {
+ psc_clk = psc_mclk_clk[psc_num];
+ if (!psc_clk) {
dev_err(port->dev, "Failed to get PSC clock entry!\n");
return -ENODEV;
}
- dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
-
- if (enable)
- clk_enable(psc_clk);
- else
+ dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
+ if (enable) {
+ ret = clk_enable(psc_clk);
+ if (ret)
+ dev_err(port->dev, "Failed to enable MCLK!\n");
+ return ret;
+ } else {
clk_disable(psc_clk);
-
- return 0;
+ return 0;
+ }
}
static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
@@ -873,7 +919,9 @@ static struct psc_ops mpc5125_psc_ops = {
.cw_disable_ints = mpc5125_psc_cw_disable_ints,
.cw_restore_ints = mpc5125_psc_cw_restore_ints,
.set_baudrate = mpc5125_psc_set_baudrate,
- .clock = mpc512x_psc_clock,
+ .clock_alloc = mpc512x_psc_alloc_clock,
+ .clock_relse = mpc512x_psc_relse_clock,
+ .clock = mpc512x_psc_endis_clock,
.fifoc_init = mpc512x_psc_fifoc_init,
.fifoc_uninit = mpc512x_psc_fifoc_uninit,
.get_irq = mpc512x_psc_get_irq,
@@ -906,7 +954,9 @@ static struct psc_ops mpc512x_psc_ops = {
.cw_disable_ints = mpc512x_psc_cw_disable_ints,
.cw_restore_ints = mpc512x_psc_cw_restore_ints,
.set_baudrate = mpc512x_psc_set_baudrate,
- .clock = mpc512x_psc_clock,
+ .clock_alloc = mpc512x_psc_alloc_clock,
+ .clock_relse = mpc512x_psc_relse_clock,
+ .clock = mpc512x_psc_endis_clock,
.fifoc_init = mpc512x_psc_fifoc_init,
.fifoc_uninit = mpc512x_psc_fifoc_uninit,
.get_irq = mpc512x_psc_get_irq,
@@ -1166,6 +1216,9 @@ mpc52xx_uart_type(struct uart_port *port)
static void
mpc52xx_uart_release_port(struct uart_port *port)
{
+ if (psc_ops->clock_relse)
+ psc_ops->clock_relse(port);
+
/* remapped by us ? */
if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
@@ -1190,11 +1243,24 @@ mpc52xx_uart_request_port(struct uart_port *port)
err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
"mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
- if (err && (port->flags & UPF_IOREMAP)) {
+ if (err)
+ goto out_membase;
+
+ if (psc_ops->clock_alloc) {
+ err = psc_ops->clock_alloc(port);
+ if (err)
+ goto out_mapregion;
+ }
+
+ return 0;
+
+out_mapregion:
+ release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
+out_membase:
+ if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
port->membase = NULL;
}
-
return err;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 03/24] mtd: mpc5121_nfc: prepare clocks before enabling them
2013-07-18 17:00 ` Gerhard Sittig
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
must prepare clocks before enabling them, unprepare after disable
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/mtd/nand/mpc5121_nfc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 3c9cdcb..eb7771d 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -618,7 +618,7 @@ static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
struct mpc5121_nfc_prv *prv = chip->priv;
if (prv->clk) {
- clk_disable(prv->clk);
+ clk_disable_unprepare(prv->clk);
clk_put(prv->clk);
}
@@ -737,7 +737,7 @@ static int mpc5121_nfc_probe(struct platform_device *op)
goto error;
}
- clk_enable(prv->clk);
+ clk_prepare_enable(prv->clk);
/* Reset NAND Flash controller */
nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 03/24] mtd: mpc5121_nfc: prepare clocks before enabling them
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
must prepare clocks before enabling them, unprepare after disable
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/mtd/nand/mpc5121_nfc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 3c9cdcb..eb7771d 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -618,7 +618,7 @@ static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
struct mpc5121_nfc_prv *prv = chip->priv;
if (prv->clk) {
- clk_disable(prv->clk);
+ clk_disable_unprepare(prv->clk);
clk_put(prv->clk);
}
@@ -737,7 +737,7 @@ static int mpc5121_nfc_probe(struct platform_device *op)
goto error;
}
- clk_enable(prv->clk);
+ clk_prepare_enable(prv->clk);
/* Reset NAND Flash controller */
nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 04/24] powerpc: mpc512x: array decl for MCLK registers in CCM
2013-07-18 17:00 ` Gerhard Sittig
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
reword the clock control module's registers declaration such that the
MCLK related registers form an array and get indexed by PSC number
this change is in preparation to COMMON_CLK support for the MPC512x
platform, the changed declaration remains neutral to existing code since
the PSC and MSCAN CCR fields declared here aren't referenced anywhere
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/include/asm/mpc5121.h | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 8ae133e..887d3d6 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -32,25 +32,11 @@ struct mpc512x_ccm {
u32 scfr2; /* System Clock Frequency Register 2 */
u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
u32 bcr; /* Bread Crumb Register */
- u32 p0ccr; /* PSC0 Clock Control Register */
- u32 p1ccr; /* PSC1 CCR */
- u32 p2ccr; /* PSC2 CCR */
- u32 p3ccr; /* PSC3 CCR */
- u32 p4ccr; /* PSC4 CCR */
- u32 p5ccr; /* PSC5 CCR */
- u32 p6ccr; /* PSC6 CCR */
- u32 p7ccr; /* PSC7 CCR */
- u32 p8ccr; /* PSC8 CCR */
- u32 p9ccr; /* PSC9 CCR */
- u32 p10ccr; /* PSC10 CCR */
- u32 p11ccr; /* PSC11 CCR */
+ u32 psc_ccr[12]; /* PSC Clock Control Registers */
u32 spccr; /* SPDIF Clock Control Register */
u32 cccr; /* CFM Clock Control Register */
u32 dccr; /* DIU Clock Control Register */
- u32 m1ccr; /* MSCAN1 CCR */
- u32 m2ccr; /* MSCAN2 CCR */
- u32 m3ccr; /* MSCAN3 CCR */
- u32 m4ccr; /* MSCAN4 CCR */
+ u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
u8 res[0x98]; /* Reserved */
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 04/24] powerpc: mpc512x: array decl for MCLK registers in CCM
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
reword the clock control module's registers declaration such that the
MCLK related registers form an array and get indexed by PSC number
this change is in preparation to COMMON_CLK support for the MPC512x
platform, the changed declaration remains neutral to existing code since
the PSC and MSCAN CCR fields declared here aren't referenced anywhere
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/include/asm/mpc5121.h | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 8ae133e..887d3d6 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -32,25 +32,11 @@ struct mpc512x_ccm {
u32 scfr2; /* System Clock Frequency Register 2 */
u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
u32 bcr; /* Bread Crumb Register */
- u32 p0ccr; /* PSC0 Clock Control Register */
- u32 p1ccr; /* PSC1 CCR */
- u32 p2ccr; /* PSC2 CCR */
- u32 p3ccr; /* PSC3 CCR */
- u32 p4ccr; /* PSC4 CCR */
- u32 p5ccr; /* PSC5 CCR */
- u32 p6ccr; /* PSC6 CCR */
- u32 p7ccr; /* PSC7 CCR */
- u32 p8ccr; /* PSC8 CCR */
- u32 p9ccr; /* PSC9 CCR */
- u32 p10ccr; /* PSC10 CCR */
- u32 p11ccr; /* PSC11 CCR */
+ u32 psc_ccr[12]; /* PSC Clock Control Registers */
u32 spccr; /* SPDIF Clock Control Register */
u32 cccr; /* CFM Clock Control Register */
u32 dccr; /* DIU Clock Control Register */
- u32 m1ccr; /* MSCAN1 CCR */
- u32 m2ccr; /* MSCAN2 CCR */
- u32 m3ccr; /* MSCAN3 CCR */
- u32 m4ccr; /* MSCAN4 CCR */
+ u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
u8 res[0x98]; /* Reserved */
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 05/24] clk: wrap I/O access for improved portability
2013-07-18 17:00 ` Gerhard Sittig
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals
wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/clk/clk-divider.c | 6 +++---
drivers/clk/clk-gate.c | 6 +++---
drivers/clk/clk-mux.c | 6 +++---
include/linux/clk-provider.h | 17 +++++++++++++++++
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6d55eb2..2c07061 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int div, val;
- val = readl(divider->reg) >> divider->shift;
+ val = clk_readl(divider->reg) >> divider->shift;
val &= div_mask(divider);
div = _get_div(divider, val);
@@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider) << (divider->shift + 16);
} else {
- val = readl(divider->reg);
+ val = clk_readl(divider->reg);
val &= ~(div_mask(divider) << divider->shift);
}
val |= value << divider->shift;
- writel(val, divider->reg);
+ clk_writel(val, divider->reg);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 790306e..b7fbd96 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
if (set)
reg |= BIT(gate->bit_idx);
} else {
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
if (set)
reg |= BIT(gate->bit_idx);
@@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
reg &= ~BIT(gate->bit_idx);
}
- writel(reg, gate->reg);
+ clk_writel(reg, gate->reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
@@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
/* if a set bit disables this clk, flip it before masking */
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 614444c..02ef506 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
* val = 0x4 really means "bit 2, index starts at bit 0"
*/
- val = readl(mux->reg) >> mux->shift;
+ val = clk_readl(mux->reg) >> mux->shift;
val &= mux->mask;
if (mux->table) {
@@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
if (mux->flags & CLK_MUX_HIWORD_MASK) {
val = mux->mask << (mux->shift + 16);
} else {
- val = readl(mux->reg);
+ val = clk_readl(mux->reg);
val &= ~(mux->mask << mux->shift);
}
val |= index << mux->shift;
- writel(val, mux->reg);
+ clk_writel(val, mux->reg);
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1ec14a7..c4f7799 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -12,6 +12,7 @@
#define __LINUX_CLK_PROVIDER_H
#include <linux/clk.h>
+#include <linux/io.h>
#ifdef CONFIG_COMMON_CLK
@@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
#define of_clk_init(matches) \
{ while (0); }
#endif /* CONFIG_OF */
+
+/*
+ * wrap access to peripherals in accessor routines
+ * for improved portability across platforms
+ */
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return readl(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ writel(val, reg);
+}
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 05/24] clk: wrap I/O access for improved portability
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals
wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/clk/clk-divider.c | 6 +++---
drivers/clk/clk-gate.c | 6 +++---
drivers/clk/clk-mux.c | 6 +++---
include/linux/clk-provider.h | 17 +++++++++++++++++
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6d55eb2..2c07061 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int div, val;
- val = readl(divider->reg) >> divider->shift;
+ val = clk_readl(divider->reg) >> divider->shift;
val &= div_mask(divider);
div = _get_div(divider, val);
@@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider) << (divider->shift + 16);
} else {
- val = readl(divider->reg);
+ val = clk_readl(divider->reg);
val &= ~(div_mask(divider) << divider->shift);
}
val |= value << divider->shift;
- writel(val, divider->reg);
+ clk_writel(val, divider->reg);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 790306e..b7fbd96 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
if (set)
reg |= BIT(gate->bit_idx);
} else {
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
if (set)
reg |= BIT(gate->bit_idx);
@@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
reg &= ~BIT(gate->bit_idx);
}
- writel(reg, gate->reg);
+ clk_writel(reg, gate->reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
@@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
- reg = readl(gate->reg);
+ reg = clk_readl(gate->reg);
/* if a set bit disables this clk, flip it before masking */
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 614444c..02ef506 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
* val = 0x4 really means "bit 2, index starts at bit 0"
*/
- val = readl(mux->reg) >> mux->shift;
+ val = clk_readl(mux->reg) >> mux->shift;
val &= mux->mask;
if (mux->table) {
@@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
if (mux->flags & CLK_MUX_HIWORD_MASK) {
val = mux->mask << (mux->shift + 16);
} else {
- val = readl(mux->reg);
+ val = clk_readl(mux->reg);
val &= ~(mux->mask << mux->shift);
}
val |= index << mux->shift;
- writel(val, mux->reg);
+ clk_writel(val, mux->reg);
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1ec14a7..c4f7799 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -12,6 +12,7 @@
#define __LINUX_CLK_PROVIDER_H
#include <linux/clk.h>
+#include <linux/io.h>
#ifdef CONFIG_COMMON_CLK
@@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
#define of_clk_init(matches) \
{ while (0); }
#endif /* CONFIG_OF */
+
+/*
+ * wrap access to peripherals in accessor routines
+ * for improved portability across platforms
+ */
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return readl(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ writel(val, reg);
+}
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 06/24] dts: mpc512x: prepare for preprocessor support
2013-07-18 17:00 ` Gerhard Sittig
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
prepare C preprocessor support when processing MPC512x DTS files
- switch from DTS syntax to CPP syntax for include specs
- create a symlink such that DTS processing can reference includes
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/ac14xx.dts | 2 +-
arch/powerpc/boot/dts/include/dt-bindings | 1 +
arch/powerpc/boot/dts/mpc5121ads.dts | 2 +-
arch/powerpc/boot/dts/pdm360ng.dts | 2 +-
4 files changed, 4 insertions(+), 3 deletions(-)
create mode 120000 arch/powerpc/boot/dts/include/dt-bindings
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a27a460..a543c40 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -10,7 +10,7 @@
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "ac14xx";
diff --git a/arch/powerpc/boot/dts/include/dt-bindings b/arch/powerpc/boot/dts/include/dt-bindings
new file mode 120000
index 0000000..08c00e4
--- /dev/null
+++ b/arch/powerpc/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index 7d3cb79..c228a0a 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -9,7 +9,7 @@
* option) any later version.
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "mpc5121ads";
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
index 7433740..871c16d 100644
--- a/arch/powerpc/boot/dts/pdm360ng.dts
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -13,7 +13,7 @@
* option) any later version.
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "pdm360ng";
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 06/24] dts: mpc512x: prepare for preprocessor support
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
prepare C preprocessor support when processing MPC512x DTS files
- switch from DTS syntax to CPP syntax for include specs
- create a symlink such that DTS processing can reference includes
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/ac14xx.dts | 2 +-
arch/powerpc/boot/dts/include/dt-bindings | 1 +
arch/powerpc/boot/dts/mpc5121ads.dts | 2 +-
arch/powerpc/boot/dts/pdm360ng.dts | 2 +-
4 files changed, 4 insertions(+), 3 deletions(-)
create mode 120000 arch/powerpc/boot/dts/include/dt-bindings
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a27a460..a543c40 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -10,7 +10,7 @@
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "ac14xx";
diff --git a/arch/powerpc/boot/dts/include/dt-bindings b/arch/powerpc/boot/dts/include/dt-bindings
new file mode 120000
index 0000000..08c00e4
--- /dev/null
+++ b/arch/powerpc/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index 7d3cb79..c228a0a 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -9,7 +9,7 @@
* option) any later version.
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "mpc5121ads";
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
index 7433740..871c16d 100644
--- a/arch/powerpc/boot/dts/pdm360ng.dts
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -13,7 +13,7 @@
* option) any later version.
*/
-/include/ "mpc5121.dtsi"
+#include <mpc5121.dtsi>
/ {
model = "pdm360ng";
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 07/24] dts: mpc512x: introduce dt-bindings/clock/ header
2013-07-18 17:00 ` Gerhard Sittig
(?)
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
introduce a dt-bindings/ header file for MPC512x clocks,
providing symbolic identifiers for those SoC clocks which
clients will reference from their device tree nodes
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
include/dt-bindings/clock/mpc512x-clock.h | 59 +++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
diff --git a/include/dt-bindings/clock/mpc512x-clock.h b/include/dt-bindings/clock/mpc512x-clock.h
new file mode 100644
index 0000000..46c560e
--- /dev/null
+++ b/include/dt-bindings/clock/mpc512x-clock.h
@@ -0,0 +1,59 @@
+/*
+ * This header provides constants for MPC512x clock specs in DT bindings.
+ *
+ * Unfortunately the clock number declaration cannot be an enum but
+ * needs to be a list of #define directives since when referenced from
+ * within DTS files they need to get resolved "at compile time".
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+
+#define MPC512x_CLK_DUMMY 0
+#define MPC512x_CLK_REF 1
+#define MPC512x_CLK_SYS 2
+#define MPC512x_CLK_DIU 3
+#define MPC512x_CLK_VIU 4
+#define MPC512x_CLK_CSB 5
+#define MPC512x_CLK_E300 6
+#define MPC512x_CLK_IPS 7
+#define MPC512x_CLK_FEC 8
+#define MPC512x_CLK_SATA 9
+#define MPC512x_CLK_PATA 10
+#define MPC512x_CLK_NFC 11
+#define MPC512x_CLK_LPC 12
+#define MPC512x_CLK_MBX_BUS 13
+#define MPC512x_CLK_MBX 14
+#define MPC512x_CLK_MBX_3D 15
+#define MPC512x_CLK_AXE 16
+#define MPC512x_CLK_USB1 17
+#define MPC512x_CLK_USB2 18
+#define MPC512x_CLK_I2C 19
+#define MPC512x_CLK_MSCAN0_MCLK 20
+#define MPC512x_CLK_MSCAN1_MCLK 21
+#define MPC512x_CLK_MSCAN2_MCLK 22
+#define MPC512x_CLK_MSCAN3_MCLK 23
+#define MPC512x_CLK_SDHC 24
+#define MPC512x_CLK_PCI 25
+#define MPC512x_CLK_PSC_MCLK_IN 26
+#define MPC512x_CLK_SPDIF_TX 27
+#define MPC512x_CLK_SPDIF_RX 28
+#define MPC512x_CLK_SPDIF_MCLK 29
+#define MPC512x_CLK_AC97 30
+#define MPC512x_CLK_PSC0_MCLK 31
+#define MPC512x_CLK_PSC1_MCLK 32
+#define MPC512x_CLK_PSC2_MCLK 33
+#define MPC512x_CLK_PSC3_MCLK 34
+#define MPC512x_CLK_PSC4_MCLK 35
+#define MPC512x_CLK_PSC5_MCLK 36
+#define MPC512x_CLK_PSC6_MCLK 37
+#define MPC512x_CLK_PSC7_MCLK 38
+#define MPC512x_CLK_PSC8_MCLK 39
+#define MPC512x_CLK_PSC9_MCLK 40
+#define MPC512x_CLK_PSC10_MCLK 41
+#define MPC512x_CLK_PSC11_MCLK 42
+#define MPC512x_CLK_PSC_FIFO 43
+
+#define MPC512x_CLK_LAST_PUBLIC 43
+
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 07/24] dts: mpc512x: introduce dt-bindings/clock/ header
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
introduce a dt-bindings/ header file for MPC512x clocks,
providing symbolic identifiers for those SoC clocks which
clients will reference from their device tree nodes
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
include/dt-bindings/clock/mpc512x-clock.h | 59 +++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
diff --git a/include/dt-bindings/clock/mpc512x-clock.h b/include/dt-bindings/clock/mpc512x-clock.h
new file mode 100644
index 0000000..46c560e
--- /dev/null
+++ b/include/dt-bindings/clock/mpc512x-clock.h
@@ -0,0 +1,59 @@
+/*
+ * This header provides constants for MPC512x clock specs in DT bindings.
+ *
+ * Unfortunately the clock number declaration cannot be an enum but
+ * needs to be a list of #define directives since when referenced from
+ * within DTS files they need to get resolved "at compile time".
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+
+#define MPC512x_CLK_DUMMY 0
+#define MPC512x_CLK_REF 1
+#define MPC512x_CLK_SYS 2
+#define MPC512x_CLK_DIU 3
+#define MPC512x_CLK_VIU 4
+#define MPC512x_CLK_CSB 5
+#define MPC512x_CLK_E300 6
+#define MPC512x_CLK_IPS 7
+#define MPC512x_CLK_FEC 8
+#define MPC512x_CLK_SATA 9
+#define MPC512x_CLK_PATA 10
+#define MPC512x_CLK_NFC 11
+#define MPC512x_CLK_LPC 12
+#define MPC512x_CLK_MBX_BUS 13
+#define MPC512x_CLK_MBX 14
+#define MPC512x_CLK_MBX_3D 15
+#define MPC512x_CLK_AXE 16
+#define MPC512x_CLK_USB1 17
+#define MPC512x_CLK_USB2 18
+#define MPC512x_CLK_I2C 19
+#define MPC512x_CLK_MSCAN0_MCLK 20
+#define MPC512x_CLK_MSCAN1_MCLK 21
+#define MPC512x_CLK_MSCAN2_MCLK 22
+#define MPC512x_CLK_MSCAN3_MCLK 23
+#define MPC512x_CLK_SDHC 24
+#define MPC512x_CLK_PCI 25
+#define MPC512x_CLK_PSC_MCLK_IN 26
+#define MPC512x_CLK_SPDIF_TX 27
+#define MPC512x_CLK_SPDIF_RX 28
+#define MPC512x_CLK_SPDIF_MCLK 29
+#define MPC512x_CLK_AC97 30
+#define MPC512x_CLK_PSC0_MCLK 31
+#define MPC512x_CLK_PSC1_MCLK 32
+#define MPC512x_CLK_PSC2_MCLK 33
+#define MPC512x_CLK_PSC3_MCLK 34
+#define MPC512x_CLK_PSC4_MCLK 35
+#define MPC512x_CLK_PSC5_MCLK 36
+#define MPC512x_CLK_PSC6_MCLK 37
+#define MPC512x_CLK_PSC7_MCLK 38
+#define MPC512x_CLK_PSC8_MCLK 39
+#define MPC512x_CLK_PSC9_MCLK 40
+#define MPC512x_CLK_PSC10_MCLK 41
+#define MPC512x_CLK_PSC11_MCLK 42
+#define MPC512x_CLK_PSC_FIFO 43
+
+#define MPC512x_CLK_LAST_PUBLIC 43
+
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 07/24] dts: mpc512x: introduce dt-bindings/clock/ header
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
introduce a dt-bindings/ header file for MPC512x clocks,
providing symbolic identifiers for those SoC clocks which
clients will reference from their device tree nodes
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
include/dt-bindings/clock/mpc512x-clock.h | 59 +++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 include/dt-bindings/clock/mpc512x-clock.h
diff --git a/include/dt-bindings/clock/mpc512x-clock.h b/include/dt-bindings/clock/mpc512x-clock.h
new file mode 100644
index 0000000..46c560e
--- /dev/null
+++ b/include/dt-bindings/clock/mpc512x-clock.h
@@ -0,0 +1,59 @@
+/*
+ * This header provides constants for MPC512x clock specs in DT bindings.
+ *
+ * Unfortunately the clock number declaration cannot be an enum but
+ * needs to be a list of #define directives since when referenced from
+ * within DTS files they need to get resolved "at compile time".
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+
+#define MPC512x_CLK_DUMMY 0
+#define MPC512x_CLK_REF 1
+#define MPC512x_CLK_SYS 2
+#define MPC512x_CLK_DIU 3
+#define MPC512x_CLK_VIU 4
+#define MPC512x_CLK_CSB 5
+#define MPC512x_CLK_E300 6
+#define MPC512x_CLK_IPS 7
+#define MPC512x_CLK_FEC 8
+#define MPC512x_CLK_SATA 9
+#define MPC512x_CLK_PATA 10
+#define MPC512x_CLK_NFC 11
+#define MPC512x_CLK_LPC 12
+#define MPC512x_CLK_MBX_BUS 13
+#define MPC512x_CLK_MBX 14
+#define MPC512x_CLK_MBX_3D 15
+#define MPC512x_CLK_AXE 16
+#define MPC512x_CLK_USB1 17
+#define MPC512x_CLK_USB2 18
+#define MPC512x_CLK_I2C 19
+#define MPC512x_CLK_MSCAN0_MCLK 20
+#define MPC512x_CLK_MSCAN1_MCLK 21
+#define MPC512x_CLK_MSCAN2_MCLK 22
+#define MPC512x_CLK_MSCAN3_MCLK 23
+#define MPC512x_CLK_SDHC 24
+#define MPC512x_CLK_PCI 25
+#define MPC512x_CLK_PSC_MCLK_IN 26
+#define MPC512x_CLK_SPDIF_TX 27
+#define MPC512x_CLK_SPDIF_RX 28
+#define MPC512x_CLK_SPDIF_MCLK 29
+#define MPC512x_CLK_AC97 30
+#define MPC512x_CLK_PSC0_MCLK 31
+#define MPC512x_CLK_PSC1_MCLK 32
+#define MPC512x_CLK_PSC2_MCLK 33
+#define MPC512x_CLK_PSC3_MCLK 34
+#define MPC512x_CLK_PSC4_MCLK 35
+#define MPC512x_CLK_PSC5_MCLK 36
+#define MPC512x_CLK_PSC6_MCLK 37
+#define MPC512x_CLK_PSC7_MCLK 38
+#define MPC512x_CLK_PSC8_MCLK 39
+#define MPC512x_CLK_PSC9_MCLK 40
+#define MPC512x_CLK_PSC10_MCLK 41
+#define MPC512x_CLK_PSC11_MCLK 42
+#define MPC512x_CLK_PSC_FIFO 43
+
+#define MPC512x_CLK_LAST_PUBLIC 43
+
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 08/24] dts: mpc512x: add clock related device tree specs
2013-07-18 17:00 ` Gerhard Sittig
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this addresses the clock driver aka provider's side of clocks
- prepare for future '<&clks ID>' phandle references for device tree
based clock lookup in client drivers
- introduce a 'clocks' subtree with an 'osc' node for the crystal
or oscillator SoC input (fixed frequency)
- provide default values with 33MHz oscillator frequency in the
common include (the 66MHz IPS bus already was there), add
override values for the ifm AC14xx board which deviates from
the reference design (25MHz xtal, 80MHz IPS bus)
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/ac14xx.dts | 7 +++++++
arch/powerpc/boot/dts/mpc5121.dtsi | 15 ++++++++++++++-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a543c40..a1b8837 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -139,7 +139,14 @@
};
};
+ clocks {
+ osc {
+ clock-frequency = <25000000>;
+ };
+ };
+
soc@80000000 {
+ bus-frequency = <80000000>; /* 80 MHz ips bus */
clock@f00 {
compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index bd14c00..8f4cba0 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -9,6 +9,8 @@
* option) any later version.
*/
+#include <dt-bindings/clock/mpc512x-clock.h>
+
/dts-v1/;
/ {
@@ -73,6 +75,16 @@
ranges = <0x0 0x0 0xfc000000 0x04000000>;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc {
+ compatible = "fsl,mpc512x-osc", "fixed-clock";
+ clock-frequency = <33000000>;
+ };
+ };
+
soc@80000000 {
compatible = "fsl,mpc5121-immr";
#address-cells = <1>;
@@ -118,9 +130,10 @@
};
/* Clock control */
- clock@f00 {
+ clks: clock@f00 {
compatible = "fsl,mpc5121-clock";
reg = <0xf00 0x100>;
+ #clock-cells = <1>;
};
/* Power Management Controller */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 08/24] dts: mpc512x: add clock related device tree specs
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
this addresses the clock driver aka provider's side of clocks
- prepare for future '<&clks ID>' phandle references for device tree
based clock lookup in client drivers
- introduce a 'clocks' subtree with an 'osc' node for the crystal
or oscillator SoC input (fixed frequency)
- provide default values with 33MHz oscillator frequency in the
common include (the 66MHz IPS bus already was there), add
override values for the ifm AC14xx board which deviates from
the reference design (25MHz xtal, 80MHz IPS bus)
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/ac14xx.dts | 7 +++++++
arch/powerpc/boot/dts/mpc5121.dtsi | 15 ++++++++++++++-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a543c40..a1b8837 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -139,7 +139,14 @@
};
};
+ clocks {
+ osc {
+ clock-frequency = <25000000>;
+ };
+ };
+
soc at 80000000 {
+ bus-frequency = <80000000>; /* 80 MHz ips bus */
clock at f00 {
compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index bd14c00..8f4cba0 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -9,6 +9,8 @@
* option) any later version.
*/
+#include <dt-bindings/clock/mpc512x-clock.h>
+
/dts-v1/;
/ {
@@ -73,6 +75,16 @@
ranges = <0x0 0x0 0xfc000000 0x04000000>;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc {
+ compatible = "fsl,mpc512x-osc", "fixed-clock";
+ clock-frequency = <33000000>;
+ };
+ };
+
soc at 80000000 {
compatible = "fsl,mpc5121-immr";
#address-cells = <1>;
@@ -118,9 +130,10 @@
};
/* Clock control */
- clock at f00 {
+ clks: clock at f00 {
compatible = "fsl,mpc5121-clock";
reg = <0xf00 0x100>;
+ #clock-cells = <1>;
};
/* Power Management Controller */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 09/24] clk: mpc512x: introduce COMMON_CLK for MPC512x
2013-07-18 17:00 ` Gerhard Sittig
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this change introduces a clock infrastructure implementation for the
MPC512x PowerPC platform which follows the COMMON_CLK approach and uses
common clock drivers shared with other platforms
this driver implements the publicly announced set of clocks (which can
get referenced by means of symbolic identifiers from the dt-bindings
header file), as well as generates additional 'struct clk' items where
the SoC hardware cannot easily get mapped to the common primitives of
the clock API, or requires "intermediate" clock nodes to represent
clocks that have both gates and dividers
the previous PPC_CLOCK implementation is kept in place and resides in
parallel to the common clock implementation for test and comparison
during migration, a compile time option picks one of the two
alternatives (Kconfig switch, common clock used by default)
since not all drivers for peripherals were adjusted yet to properly
allocate and release their clock items, this platform clock driver
implementation pre-enables some of the clock items to not break
peripheral drivers during migration -- these clock pre-enable
workarounds will get removed as peripheral drivers get adjusted
to provide clock names which the serial communication drivers are using
and where the PSC index number is encoded into, clkdev registration is
done to not break these peripheral drivers -- this workaround will get
removed as these drivers get adjusted after device tree based clock
lookup has become available
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/Kconfig | 14 +-
arch/powerpc/platforms/512x/Makefile | 4 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 778 +++++++++++++++++++++++++
include/linux/clk-provider.h | 16 +
4 files changed, 810 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index fc9c1cb..c5fcdd0 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,9 +1,21 @@
+config MPC512x_COMMON_CLK
+ bool "MPC512x platform uses COMMON_CLK"
+ default y
+ depends on PPC_MPC512x
+ help
+ This option is only here to support tests and comparison
+ during development and migration. This option will get
+ removed after the COMMON_CLK support for MPC512x has become
+ fully operational and all drivers were adjusted to explicitly
+ acquire their required clocks.
+
config PPC_MPC512x
bool "512x-based boards"
depends on 6xx
select FSL_SOC
select IPIC
- select PPC_CLOCK
+ select PPC_CLOCK if !MPC512x_COMMON_CLK
+ select COMMON_CLK if MPC512x_COMMON_CLK
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 72fb934..1e05f9d 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,7 +1,9 @@
#
# Makefile for the Freescale PowerPC 512x linux kernel.
#
-obj-y += clock.o mpc512x_shared.o
+obj-$(CONFIG_PPC_CLOCK) += clock.o
+obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
+obj-y += mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o
obj-$(CONFIG_PDM360NG) += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
new file mode 100644
index 0000000..6627957
--- /dev/null
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -0,0 +1,778 @@
+/*
+ * Copyright (C) 2013 DENX Software Engineering
+ *
+ * Gerhard Sittig, <gsi@denx.de>
+ *
+ * common clock driver support for the MPC512x platform
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <asm/mpc5121.h>
+#include <dt-bindings/clock/mpc512x-clock.h>
+
+#include "mpc512x.h" /* our public mpc5121_clk_init() API */
+
+/* helpers to keep the MCLK intermediates "somewhere" in our table */
+enum {
+ MCLK_IDX_MUX0,
+ MCLK_IDX_EN0,
+ MCLK_IDX_DIV0,
+ MCLK_IDX_MUX1,
+ MCLK_MAX_IDX,
+};
+
+#define NR_PSCS 12
+#define NR_MSCANS 4
+#define NR_SPDIFS 1
+#define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS)
+
+/* extend the public set of clocks by adding internal slots for management */
+enum {
+ /* arrange for adjacent numbers after the public set */
+ MPC512x_CLK_START_PRIVATE = MPC512x_CLK_LAST_PUBLIC,
+ /* clocks which aren't announced to the public */
+ MPC512x_CLK_DDR,
+ MPC512x_CLK_MEM,
+ MPC512x_CLK_IIM,
+ MPC512x_CLK_SDHC_2,
+ /* intermediates in div+gate combos or fractional dividers */
+ MPC512x_CLK_DDR_UG,
+ MPC512x_CLK_SDHC_x4,
+ MPC512x_CLK_SDHC_UG,
+ MPC512x_CLK_DIU_x4,
+ MPC512x_CLK_DIU_UG,
+ MPC512x_CLK_MBX_BUS_UG,
+ MPC512x_CLK_MBX_UG,
+ MPC512x_CLK_MBX_3D_UG,
+ MPC512x_CLK_PCI_UG,
+ MPC512x_CLK_NFC_UG,
+ MPC512x_CLK_LPC_UG,
+ MPC512x_CLK_SPDIF_TX_IN,
+ /* intermediates for the mux+gate+div+mux MCLK generation */
+ MPC512x_CLK_MCLKS_FIRST,
+ MPC512x_CLK_MCLKS_LAST = MPC512x_CLK_MCLKS_FIRST
+ + NR_MCLKS * MCLK_MAX_IDX,
+ /* internal, symbolic spec for the number of slots */
+ MPC512x_CLK_LAST_PRIVATE,
+};
+
+/* data required for the OF clock provider registration */
+static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
+static struct clk_onecell_data clk_data;
+
+/* CCM register access */
+static struct mpc512x_ccm __iomem *clkregs;
+static DEFINE_SPINLOCK(clklock);
+
+/* convenience wrappers around the common clk API */
+static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
+{
+ return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *mpc512x_clk_factor(
+ const char *name, const char *parent_name,
+ int mul, int div)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_fixed_factor(NULL, name, parent_name, clkflags,
+ mul, div);
+}
+
+static inline struct clk *mpc512x_clk_divider(
+ const char *name, const char *parent_name, u8 clkflags,
+ u32 __iomem *reg, u8 pos, u8 len, int divflags)
+{
+ return clk_register_divider(NULL, name, parent_name, clkflags,
+ reg, pos, len, divflags, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_divtable(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos, u8 len,
+ const struct clk_div_table *divtab)
+{
+ u8 divflags;
+
+ divflags = 0;
+ return clk_register_divider_table(NULL, name, parent_name, 0,
+ reg, pos, len, divflags,
+ divtab, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_gated(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_gate(NULL, name, parent_name, clkflags,
+ reg, pos, 0, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_muxed(const char *name,
+ const char **parent_names, int parent_count,
+ u32 __iomem *reg, u8 pos, u8 len)
+{
+ int clkflags;
+ u8 muxflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ muxflags = 0;
+ return clk_register_mux(NULL, name,
+ parent_names, parent_count, clkflags,
+ reg, pos, len, muxflags, &clklock);
+}
+
+/* helper to isolate a bit field from a register */
+static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len)
+{
+ uint32_t val;
+
+ val = in_be32(reg);
+ val >>= pos;
+ val &= (1 << len) - 1;
+ return val;
+}
+
+/* get the SPMF and translate it into the "sys pll" multiplier */
+static int get_spmf_mult(void)
+{
+ static int spmf_to_mult[] = {
+ 68, 1, 12, 16, 20, 24, 28, 32,
+ 36, 40, 44, 48, 52, 56, 60, 64,
+ };
+ int spmf;
+
+ spmf = get_bit_field(&clkregs->spmr, 24, 4);
+ return spmf_to_mult[spmf];
+}
+
+/*
+ * get the SYS_DIV value and translate it into a divide factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * divide ratio is fractional
+ */
+static int get_sys_div_x2(void)
+{
+ static int sysdiv_code_to_x2[] = {
+ 4, 5, 6, 7, 8, 9, 10, 14,
+ 12, 16, 18, 22, 20, 24, 26, 30,
+ 28, 32, 34, 38, 36, 40, 42, 46,
+ 44, 48, 50, 54, 52, 56, 58, 62,
+ 60, 64, 66,
+ };
+ int divcode;
+
+ divcode = get_bit_field(&clkregs->scfr2, 26, 6);
+ return sysdiv_code_to_x2[divcode];
+}
+
+/*
+ * get the CPMF value and translate it into a multiplier factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * multiplier ratio is fractional
+ */
+static int get_cpmf_mult_x2(void)
+{
+ static int cpmf_to_mult[] = {
+ 72, 2, 2, 3, 4, 5, 6, 7,
+ };
+ int cpmf;
+
+ cpmf = get_bit_field(&clkregs->spmr, 16, 4);
+ return cpmf_to_mult[cpmf];
+}
+
+/*
+ * some of the clock dividers do scale in a linear way, yet not all of
+ * their bit combinations are legal; use a divider table to get a
+ * resulting set of applicable divider values
+ */
+
+/* applies to the IPS_DIV, and PCI_DIV values */
+static struct clk_div_table divtab_2346[] = {
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .val = 6, .div = 6, },
+ { .div = 0, },
+};
+
+/* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
+static struct clk_div_table divtab_1234[] = {
+ { .val = 1, .div = 1, },
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .div = 0, },
+};
+
+static int get_freq_from_dt(char *propname)
+{
+ struct device_node *np;
+ const unsigned int *prop;
+ int val;
+
+ val = 0;
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
+ if (np) {
+ prop = of_get_property(np, propname, NULL);
+ if (prop)
+ val = *prop;
+ of_node_put(np);
+ }
+ return val;
+}
+
+static void mpc512x_clk_preset_data(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++)
+ clks[i] = ERR_PTR(-ENODEV);
+}
+
+/*
+ * - receives the "bus frequency" from the caller (that's the IPS clock
+ * rate, the historical source of clock information)
+ * - fetches the system PLL multiplier and divider values as well as the
+ * IPS divider value from hardware
+ * - determines the REF clock rate either from the XTAL/OSC spec (if
+ * there is a device tree node describing the oscillator) or from the
+ * IPS bus clock (supported for backwards compatibility, such that
+ * setups without XTAL/OSC specs keep working)
+ * - creates the "ref" clock item in the clock tree, such that
+ * subsequent code can create the remainder of the hierarchy (REF ->
+ * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
+ * values
+ */
+static void mpc512x_clk_setup_ref_clock(int bus_freq,
+ int *sys_mul, int *sys_div, int *ips_div)
+{
+ struct clk *osc_clk;
+ int calc_freq;
+
+ /* fetch mul/div factors from the hardware */
+ *sys_mul = get_spmf_mult();
+ *sys_mul *= 2; /* compensate for the fractional divider */
+ *sys_div = get_sys_div_x2();
+ *ips_div = get_bit_field(&clkregs->scfr1, 23, 3);
+
+ /* lookup the oscillator node */
+ osc_clk = clk_get(NULL, "osc");
+ if (osc_clk) {
+ /* descend REF directly from OSC, verify the IPS rate */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1);
+ calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]);
+ calc_freq *= *sys_mul;
+ calc_freq /= *sys_div;
+ calc_freq /= 2;
+ calc_freq /= *ips_div;
+ if (bus_freq && calc_freq != bus_freq)
+ pr_warn("calc rate %d != OF spec %d\n",
+ calc_freq, bus_freq);
+ } else {
+ /* calculate OSC rate and create REF from the freq value */
+ calc_freq = bus_freq; /* start with IPS */
+ calc_freq *= *ips_div; /* IPS -> CSB */
+ calc_freq *= 2; /* CSB -> SYS */
+ calc_freq *= *sys_div; /* SYS -> PLL out */
+ calc_freq /= *sys_mul; /* PLL out -> REF == OSC */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq);
+ }
+}
+
+/*
+ * helper code for the MCLK subtree setup
+ *
+ * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
+ * suggests that all instances of the "PSC clock generation" are equal,
+ * and that one might re-use the PSC setup for MSCAN clock generation
+ * (section 5.2.5) as well, at least the logic if not the data for
+ * description
+ *
+ * the details (starting at page 5-20) show differences in the specific
+ * inputs of the first mux stage ("can clk in", "spdif tx"), and the
+ * factual non-availability of the second mux stage (it's present yet
+ * only one input is valid)
+ *
+ * the MSCAN clock related registers (starting at page 5-35) all
+ * reference "spdif clk" at the first mux stage and don't mention any
+ * "can clk" at all, which somehow is unexpected
+ *
+ * TODO re-check the document, and clarify whether the RM is correct in
+ * the overview or in the details, and whether the difference is a
+ * clipboard induced error or results from chip revisions
+ *
+ * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
+ * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
+ * first a doc update is required which better reflects reality in the
+ * SoC before the implementation should follow while no questions remain
+ */
+
+/*
+ * note that this declaration raises a checkpatch warning, but
+ * it's the very data type which <linux/clk-provider.h> expects,
+ * making this declaration pass checkpatch will break compilation
+ */
+static const char *parent_names_mux0[] = {
+ "sys", "ref", "psc-mclk-in", "spdif-tx",
+};
+
+enum mclk_type {
+ MCLK_TYPE_PSC,
+ MCLK_TYPE_MSCAN,
+ MCLK_TYPE_SPDIF,
+};
+
+struct mclk_setup_data {
+ enum mclk_type type;
+ int comp_idx;
+ bool has_mclk1;
+ int bit_sccr1, bit_sccr2;
+ const char *name_mux0;
+ const char *name_en0;
+ const char *name_div0;
+ const char *parent_names_mux1[2];
+ const char *name_mux1;
+ const char *name_mclk;
+};
+
+#define MCLK_SETUP_DATA_PSC(id) { \
+ MCLK_TYPE_PSC, id, \
+ 0, 27 - id, -1, \
+ "psc" #id "-mux0", \
+ "psc" #id "-en0", \
+ "psc" #id "_mclk_div", \
+ { "psc" #id "_mclk_div", "dummy", }, \
+ "psc" #id "_mclk_out", \
+ "psc" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_MSCAN(id) { \
+ MCLK_TYPE_MSCAN, id, \
+ 0, -1, 25, \
+ "mscan" #id "-mux0", \
+ "mscan" #id "-en0", \
+ "mscan" #id "_mclk_div", \
+ { "mscan" #id "_mclk_div", "dummy", }, \
+ "mscan" #id "_mclk_out", \
+ "mscan" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_SPDIF { \
+ MCLK_TYPE_SPDIF, 0, \
+ 1, -1, 23, \
+ "spdif-mux0", \
+ "spdif-en0", \
+ "spdif_mclk_div", \
+ { "spdif_mclk_div", "spdif-rx", }, \
+ "spdif_mclk_out", \
+ "spdif_mclk", \
+}
+
+static struct mclk_setup_data mclk_psc_data[] = {
+ MCLK_SETUP_DATA_PSC(0),
+ MCLK_SETUP_DATA_PSC(1),
+ MCLK_SETUP_DATA_PSC(2),
+ MCLK_SETUP_DATA_PSC(3),
+ MCLK_SETUP_DATA_PSC(4),
+ MCLK_SETUP_DATA_PSC(5),
+ MCLK_SETUP_DATA_PSC(6),
+ MCLK_SETUP_DATA_PSC(7),
+ MCLK_SETUP_DATA_PSC(8),
+ MCLK_SETUP_DATA_PSC(9),
+ MCLK_SETUP_DATA_PSC(10),
+ MCLK_SETUP_DATA_PSC(11),
+};
+
+static struct mclk_setup_data mclk_mscan_data[] = {
+ MCLK_SETUP_DATA_MSCAN(0),
+ MCLK_SETUP_DATA_MSCAN(1),
+ MCLK_SETUP_DATA_MSCAN(2),
+ MCLK_SETUP_DATA_MSCAN(3),
+};
+
+static struct mclk_setup_data mclk_spdif_data[] = {
+ MCLK_SETUP_DATA_SPDIF,
+};
+
+/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
+static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
+{
+ size_t clks_idx_pub, clks_idx_int;
+ u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */
+ u32 __iomem *sccr_reg; /* system clock control register (enable) */
+ int sccr_bit;
+ int div;
+
+ /* derive a few parameters from the component type and index */
+ switch (entry->type) {
+ case MCLK_TYPE_PSC:
+ clks_idx_pub = MPC512x_CLK_PSC0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->psc_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_MSCAN:
+ clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->mscan_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_SPDIF:
+ clks_idx_pub = MPC512x_CLK_SPDIF_MCLK;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->spccr;
+ break;
+ default:
+ return;
+ }
+ if (entry->bit_sccr1 >= 0) {
+ sccr_reg = &clkregs->sccr1;
+ sccr_bit = entry->bit_sccr1;
+ } else if (entry->bit_sccr2 >= 0) {
+ sccr_reg = &clkregs->sccr2;
+ sccr_bit = entry->bit_sccr2;
+ } else {
+ sccr_reg = NULL;
+ }
+
+ /*
+ * this was grabbed from the PPC_CLOCK implementation, which
+ * enforced a specific MCLK divider while the clock was gated
+ * during setup (that's a documented hardware requirement)
+ *
+ * the PPC_CLOCK implementation might even have violated the
+ * "MCLK <= IPS" constraint, the fixed divider value of 1
+ * results in a divider of 2 and thus MCLK = SYS/2 which equals
+ * CSB which is greater than IPS; the serial port setup may have
+ * adjusted the divider which the clock setup might have left in
+ * an undesirable state
+ *
+ * initial setup is:
+ * - MCLK 0 from SYS
+ * - MCLK DIV such to not exceed the IPS clock
+ * - MCLK 0 enabled
+ * - MCLK 1 from MCLK DIV
+ */
+ div = clk_get_rate(clks[MPC512x_CLK_SYS]);
+ div /= clk_get_rate(clks[MPC512x_CLK_IPS]);
+ out_be32(mccr_reg, (0 << 16));
+ out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
+ out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
+
+ /*
+ * create the 'struct clk' items of the MCLK's clock subtree
+ *
+ * note that by design we always create all nodes and won't take
+ * shortcuts here, because
+ * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
+ * selectable inputs to the CFM while those who "actually use"
+ * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
+ * for their bitrate
+ * - in the absence of "aliases" for clocks we need to create
+ * individial 'struct clk' items for whatever might get
+ * referenced or looked up, even if several of those items are
+ * identical from the logical POV (their rate value)
+ * - for easier future maintenance and for better reflection of
+ * the SoC's documentation, it appears appropriate to generate
+ * clock items even for those muxers which actually are NOPs
+ * (those with two inputs of which one is reserved)
+ */
+ clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed(
+ entry->name_mux0,
+ &parent_names_mux0[0], ARRAY_SIZE(parent_names_mux0),
+ mccr_reg, 14, 2);
+ clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated(
+ entry->name_en0, entry->name_mux0,
+ mccr_reg, 16);
+ clks[clks_idx_int + MCLK_IDX_DIV0] = mpc512x_clk_divider(
+ entry->name_div0,
+ entry->name_en0, CLK_SET_RATE_GATE,
+ mccr_reg, 17, 15, 0);
+ if (entry->has_mclk1) {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_muxed(
+ entry->name_mux1,
+ &entry->parent_names_mux1[0],
+ ARRAY_SIZE(entry->parent_names_mux1),
+ mccr_reg, 7, 1);
+ } else {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_factor(
+ entry->name_mux1, entry->parent_names_mux1[0],
+ 1, 1);
+ }
+ if (sccr_reg) {
+ clks[clks_idx_pub] = mpc512x_clk_gated(
+ entry->name_mclk,
+ entry->name_mux1, sccr_reg, sccr_bit);
+ } else {
+ clks[clks_idx_pub] = mpc512x_clk_factor(
+ entry->name_mclk,
+ entry->name_mux1, 1, 1);
+ }
+
+ /*
+ * without this "clock device" registration, "simple" lookups in
+ * the SPI master initialization and serial port setup will fail
+ *
+ * those drivers need to get adjusted to lookup their required
+ * clocks from device tree specs, and device tree nodes need to
+ * provide the clock specs, before this clkdev registration
+ * becomes obsolete
+ */
+ clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
+}
+
+static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
+{
+ while (count-- > 0)
+ mpc512x_clk_setup_mclk(table++);
+}
+
+static void mpc512x_clk_setup_clock_tree(int busfreq)
+{
+ int sys_mul, sys_div, ips_div;
+ int mul, div;
+ int freq;
+
+ /*
+ * TODO
+ * - consider whether to handle clocks which have both gates and
+ * dividers via intermediates or by means of composites
+ * - fractional dividers appear to not map well to composites
+ * since they can be seen as a fixed multiplier and an
+ * adjustable divider, while composites can only combine at
+ * most one of a mux, div, and gate each into one 'struct clk'
+ * item
+ * - PSC/MSCAN/SPDIF clock generation OTOH already is very
+ * specific and cannot get mapped to componsites (at least not
+ * a single one, maybe two of them, but see the comment about
+ * "intermediates are referenced from elsewhere, too")
+ * - trim the list of auto-enabled clocks after drivers acquire
+ * them correctly as needed
+ */
+
+ /* regardless of whether XTAL/OSC exists, have REF created */
+ mpc512x_clk_setup_ref_clock(busfreq, &sys_mul, &sys_div, &ips_div);
+
+ /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
+ clks[MPC512x_CLK_SYS] = mpc512x_clk_factor("sys", "ref",
+ sys_mul, sys_div);
+ clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2);
+ clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb",
+ &clkregs->scfr1, 23, 3,
+ divtab_2346);
+
+ /* now setup anything below SYS and CSB and IPS */
+ clks[MPC512x_CLK_DDR_UG] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2);
+ clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0,
+ &clkregs->scfr2, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+ clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_DIU_UG] = mpc512x_clk_divider("diu-ug", "diu-x4", 0,
+ &clkregs->scfr1, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+
+ /*
+ * the "power architecture PLL" was setup from data which was
+ * sampled from the reset config word, at this point in time the
+ * configuration can be considered fixed and read only (i.e. no
+ * longer adjustable, or no longer in need of adjustment), which
+ * is why we don't register a PLL here but assume fixed factors
+ */
+ mul = get_cpmf_mult_x2();
+ div = 2; /* compensate for the fractional factor */
+ clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div);
+
+ clks[MPC512x_CLK_MBX_BUS_UG] = mpc512x_clk_factor("mbx-bus-ug", "csb",
+ 1, 2);
+ clks[MPC512x_CLK_MBX_UG] = mpc512x_clk_divtable("mbx-ug", "mbx-bus-ug",
+ &clkregs->scfr1, 14, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_MBX_3D_UG] = mpc512x_clk_factor("mbx-3d-ug", "mbx-ug",
+ 1, 1);
+ clks[MPC512x_CLK_PCI_UG] = mpc512x_clk_divtable("pci-ug", "csb",
+ &clkregs->scfr1, 20, 3,
+ divtab_2346);
+ clks[MPC512x_CLK_NFC_UG] = mpc512x_clk_divtable("nfc-ug", "ips",
+ &clkregs->scfr1, 8, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips",
+ &clkregs->scfr1, 11, 3,
+ divtab_1234);
+
+ clks[MPC512x_CLK_LPC] = mpc512x_clk_gated("lpc", "lpc-ug",
+ &clkregs->sccr1, 30);
+ clks[MPC512x_CLK_NFC] = mpc512x_clk_gated("nfc", "nfc-ug",
+ &clkregs->sccr1, 29);
+ clks[MPC512x_CLK_PATA] = mpc512x_clk_gated("pata", "ips",
+ &clkregs->sccr1, 28);
+ mpc512x_clk_setup_mclks(mclk_psc_data, ARRAY_SIZE(mclk_psc_data));
+ clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips",
+ &clkregs->sccr1, 15);
+ clks[MPC512x_CLK_SATA] = mpc512x_clk_gated("sata", "ips",
+ &clkregs->sccr1, 14);
+ clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips",
+ &clkregs->sccr1, 13);
+ clks[MPC512x_CLK_PCI] = mpc512x_clk_gated("pci", "pci-ug",
+ &clkregs->sccr1, 11);
+ clks[MPC512x_CLK_DDR] = mpc512x_clk_gated("ddr", "ddr-ug",
+ &clkregs->sccr1, 10);
+
+ clks[MPC512x_CLK_DIU] = mpc512x_clk_gated("diu", "diu-ug",
+ &clkregs->sccr2, 31);
+ clks[MPC512x_CLK_AXE] = mpc512x_clk_gated("axe", "csb",
+ &clkregs->sccr2, 30);
+ clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips",
+ &clkregs->sccr2, 29);
+ clks[MPC512x_CLK_USB1] = mpc512x_clk_gated("usb1", "csb",
+ &clkregs->sccr2, 28);
+ clks[MPC512x_CLK_USB2] = mpc512x_clk_gated("usb2", "csb",
+ &clkregs->sccr2, 27);
+ clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips",
+ &clkregs->sccr2, 26);
+ mpc512x_clk_setup_mclks(mclk_mscan_data, ARRAY_SIZE(mclk_mscan_data));
+ clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug",
+ &clkregs->sccr2, 24);
+ mpc512x_clk_setup_mclks(mclk_spdif_data, ARRAY_SIZE(mclk_spdif_data));
+ clks[MPC512x_CLK_MBX_BUS] = mpc512x_clk_gated("mbx-bus", "mbx-bus-ug",
+ &clkregs->sccr2, 22);
+ clks[MPC512x_CLK_MBX] = mpc512x_clk_gated("mbx", "mbx-ug",
+ &clkregs->sccr2, 21);
+ clks[MPC512x_CLK_MBX_3D] = mpc512x_clk_gated("mbx-3d", "mbx-3d-ug",
+ &clkregs->sccr2, 20);
+ clks[MPC512x_CLK_IIM] = mpc512x_clk_gated("iim", "csb",
+ &clkregs->sccr2, 19);
+ clks[MPC512x_CLK_VIU] = mpc512x_clk_gated("viu", "csb",
+ &clkregs->sccr2, 18);
+ clks[MPC512x_CLK_SDHC_2] = mpc512x_clk_gated("sdhc-2", "sdhc-ug",
+ &clkregs->sccr2, 17);
+
+ /*
+ * externally provided clocks (when implemented in hardware,
+ * device tree may specify values which otherwise were unknown)
+ */
+ freq = get_freq_from_dt("psc_mclk_in");
+ if (!freq)
+ freq = 25000000;
+ clks[MPC512x_CLK_PSC_MCLK_IN] = mpc512x_clk_fixed("psc_mclk_in", freq);
+ freq = get_freq_from_dt("spdif_tx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_tx_in", freq);
+ freq = get_freq_from_dt("spdif_rx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_rx_in", freq);
+
+ /* fixed frequency for AC97, always 24.567MHz */
+ clks[MPC512x_CLK_AC97] = mpc512x_clk_fixed("ac97", 24567000);
+
+ pr_debug("clock tree setup complete\n");
+ freq = clk_get_rate(clks[MPC512x_CLK_E300]);
+ pr_debug("derived PPC freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_IPS]);
+ pr_debug("derived IPS freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_LPC]);
+ pr_debug("derived LPC freq [%d]\n", freq);
+
+ /* enable some of the clocks here unconditionally because ... */
+ pr_debug("automatically enabling some clocks\n");
+ /* some are essential yet never get claimed by any driver */
+ clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
+ clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */
+ clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
+ clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
+ /* some are required yet no dependencies were declared */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
+ /* some are not yet acquired by their respective drivers */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
+ clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
+ clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
+ clk_prepare_enable(clks[MPC512x_CLK_I2C]);
+ /*
+ * some have their individual clock subtree with separate clock
+ * items and their individual enable counters, yet share a
+ * common gate (refer to the same register location) while the
+ * common clock driver code is not aware of the fact and the
+ * platform's code doesn't provide specific support either
+ *
+ * what might happen is that e.g. enabling two MSCAN clock items
+ * and disabling one of them will disable the common gate and
+ * thus break the other MSCAN clock as well
+ */
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN0_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN1_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN2_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN3_MCLK]);
+}
+
+/*
+ * registers the set of public clocks (those listed in the dt-bindings/
+ * header file) for OF lookups, keeps the intermediates private to us
+ */
+static void mpc5121_clk_register_of_provider(struct device_node *np)
+{
+ clk_data.clks = clks;
+ clk_data.clk_num = MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_SIZE() */
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+int __init mpc5121_clk_init(void)
+{
+ struct device_node *clk_np;
+ int busfreq;
+
+ /* map the clock control registers */
+ clk_np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ if (!clk_np)
+ return -ENODEV;
+ clkregs = of_iomap(clk_np, 0);
+ WARN_ON(!clkregs);
+
+ /* invalidate all not yet registered clock slots */
+ mpc512x_clk_preset_data();
+
+ /*
+ * have the device tree scanned for "fixed-clock" nodes (which
+ * includes the oscillator node if the board's DT provides one)
+ */
+ of_clk_init(NULL);
+
+ /*
+ * add a dummy clock for those situations where a clock spec is
+ * required yet no real clock is involved
+ */
+ clks[MPC512x_CLK_DUMMY] = mpc512x_clk_fixed("dummy", 0);
+
+ /*
+ * have all the real nodes in the clock tree populated from REF
+ * down to all leaves, either starting from the OSC node or from
+ * a REF root that was created from the IPS bus clock input
+ */
+ busfreq = get_freq_from_dt("bus-frequency");
+ mpc512x_clk_setup_clock_tree(busfreq);
+
+ /* register as an OF clock provider */
+ mpc5121_clk_register_of_provider(clk_np);
+
+ return 0;
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c4f7799..7f8fc64 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -497,6 +497,20 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
* for improved portability across platforms
*/
+#if IS_ENABLED(CONFIG_PPC)
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return ioread32be(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ iowrite32be(val, reg);
+}
+
+#else /* platform dependent I/O accessors */
+
static inline u32 clk_readl(u32 __iomem *reg)
{
return readl(reg);
@@ -507,5 +521,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
writel(val, reg);
}
+#endif /* platform dependent I/O accessors */
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 09/24] clk: mpc512x: introduce COMMON_CLK for MPC512x
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
this change introduces a clock infrastructure implementation for the
MPC512x PowerPC platform which follows the COMMON_CLK approach and uses
common clock drivers shared with other platforms
this driver implements the publicly announced set of clocks (which can
get referenced by means of symbolic identifiers from the dt-bindings
header file), as well as generates additional 'struct clk' items where
the SoC hardware cannot easily get mapped to the common primitives of
the clock API, or requires "intermediate" clock nodes to represent
clocks that have both gates and dividers
the previous PPC_CLOCK implementation is kept in place and resides in
parallel to the common clock implementation for test and comparison
during migration, a compile time option picks one of the two
alternatives (Kconfig switch, common clock used by default)
since not all drivers for peripherals were adjusted yet to properly
allocate and release their clock items, this platform clock driver
implementation pre-enables some of the clock items to not break
peripheral drivers during migration -- these clock pre-enable
workarounds will get removed as peripheral drivers get adjusted
to provide clock names which the serial communication drivers are using
and where the PSC index number is encoded into, clkdev registration is
done to not break these peripheral drivers -- this workaround will get
removed as these drivers get adjusted after device tree based clock
lookup has become available
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/Kconfig | 14 +-
arch/powerpc/platforms/512x/Makefile | 4 +-
arch/powerpc/platforms/512x/clock-commonclk.c | 778 +++++++++++++++++++++++++
include/linux/clk-provider.h | 16 +
4 files changed, 810 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/platforms/512x/clock-commonclk.c
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index fc9c1cb..c5fcdd0 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,9 +1,21 @@
+config MPC512x_COMMON_CLK
+ bool "MPC512x platform uses COMMON_CLK"
+ default y
+ depends on PPC_MPC512x
+ help
+ This option is only here to support tests and comparison
+ during development and migration. This option will get
+ removed after the COMMON_CLK support for MPC512x has become
+ fully operational and all drivers were adjusted to explicitly
+ acquire their required clocks.
+
config PPC_MPC512x
bool "512x-based boards"
depends on 6xx
select FSL_SOC
select IPIC
- select PPC_CLOCK
+ select PPC_CLOCK if !MPC512x_COMMON_CLK
+ select COMMON_CLK if MPC512x_COMMON_CLK
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 72fb934..1e05f9d 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,7 +1,9 @@
#
# Makefile for the Freescale PowerPC 512x linux kernel.
#
-obj-y += clock.o mpc512x_shared.o
+obj-$(CONFIG_PPC_CLOCK) += clock.o
+obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
+obj-y += mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o
obj-$(CONFIG_PDM360NG) += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
new file mode 100644
index 0000000..6627957
--- /dev/null
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -0,0 +1,778 @@
+/*
+ * Copyright (C) 2013 DENX Software Engineering
+ *
+ * Gerhard Sittig, <gsi@denx.de>
+ *
+ * common clock driver support for the MPC512x platform
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <asm/mpc5121.h>
+#include <dt-bindings/clock/mpc512x-clock.h>
+
+#include "mpc512x.h" /* our public mpc5121_clk_init() API */
+
+/* helpers to keep the MCLK intermediates "somewhere" in our table */
+enum {
+ MCLK_IDX_MUX0,
+ MCLK_IDX_EN0,
+ MCLK_IDX_DIV0,
+ MCLK_IDX_MUX1,
+ MCLK_MAX_IDX,
+};
+
+#define NR_PSCS 12
+#define NR_MSCANS 4
+#define NR_SPDIFS 1
+#define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS)
+
+/* extend the public set of clocks by adding internal slots for management */
+enum {
+ /* arrange for adjacent numbers after the public set */
+ MPC512x_CLK_START_PRIVATE = MPC512x_CLK_LAST_PUBLIC,
+ /* clocks which aren't announced to the public */
+ MPC512x_CLK_DDR,
+ MPC512x_CLK_MEM,
+ MPC512x_CLK_IIM,
+ MPC512x_CLK_SDHC_2,
+ /* intermediates in div+gate combos or fractional dividers */
+ MPC512x_CLK_DDR_UG,
+ MPC512x_CLK_SDHC_x4,
+ MPC512x_CLK_SDHC_UG,
+ MPC512x_CLK_DIU_x4,
+ MPC512x_CLK_DIU_UG,
+ MPC512x_CLK_MBX_BUS_UG,
+ MPC512x_CLK_MBX_UG,
+ MPC512x_CLK_MBX_3D_UG,
+ MPC512x_CLK_PCI_UG,
+ MPC512x_CLK_NFC_UG,
+ MPC512x_CLK_LPC_UG,
+ MPC512x_CLK_SPDIF_TX_IN,
+ /* intermediates for the mux+gate+div+mux MCLK generation */
+ MPC512x_CLK_MCLKS_FIRST,
+ MPC512x_CLK_MCLKS_LAST = MPC512x_CLK_MCLKS_FIRST
+ + NR_MCLKS * MCLK_MAX_IDX,
+ /* internal, symbolic spec for the number of slots */
+ MPC512x_CLK_LAST_PRIVATE,
+};
+
+/* data required for the OF clock provider registration */
+static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
+static struct clk_onecell_data clk_data;
+
+/* CCM register access */
+static struct mpc512x_ccm __iomem *clkregs;
+static DEFINE_SPINLOCK(clklock);
+
+/* convenience wrappers around the common clk API */
+static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
+{
+ return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *mpc512x_clk_factor(
+ const char *name, const char *parent_name,
+ int mul, int div)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_fixed_factor(NULL, name, parent_name, clkflags,
+ mul, div);
+}
+
+static inline struct clk *mpc512x_clk_divider(
+ const char *name, const char *parent_name, u8 clkflags,
+ u32 __iomem *reg, u8 pos, u8 len, int divflags)
+{
+ return clk_register_divider(NULL, name, parent_name, clkflags,
+ reg, pos, len, divflags, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_divtable(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos, u8 len,
+ const struct clk_div_table *divtab)
+{
+ u8 divflags;
+
+ divflags = 0;
+ return clk_register_divider_table(NULL, name, parent_name, 0,
+ reg, pos, len, divflags,
+ divtab, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_gated(
+ const char *name, const char *parent_name,
+ u32 __iomem *reg, u8 pos)
+{
+ int clkflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ return clk_register_gate(NULL, name, parent_name, clkflags,
+ reg, pos, 0, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_muxed(const char *name,
+ const char **parent_names, int parent_count,
+ u32 __iomem *reg, u8 pos, u8 len)
+{
+ int clkflags;
+ u8 muxflags;
+
+ clkflags = CLK_SET_RATE_PARENT;
+ muxflags = 0;
+ return clk_register_mux(NULL, name,
+ parent_names, parent_count, clkflags,
+ reg, pos, len, muxflags, &clklock);
+}
+
+/* helper to isolate a bit field from a register */
+static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len)
+{
+ uint32_t val;
+
+ val = in_be32(reg);
+ val >>= pos;
+ val &= (1 << len) - 1;
+ return val;
+}
+
+/* get the SPMF and translate it into the "sys pll" multiplier */
+static int get_spmf_mult(void)
+{
+ static int spmf_to_mult[] = {
+ 68, 1, 12, 16, 20, 24, 28, 32,
+ 36, 40, 44, 48, 52, 56, 60, 64,
+ };
+ int spmf;
+
+ spmf = get_bit_field(&clkregs->spmr, 24, 4);
+ return spmf_to_mult[spmf];
+}
+
+/*
+ * get the SYS_DIV value and translate it into a divide factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * divide ratio is fractional
+ */
+static int get_sys_div_x2(void)
+{
+ static int sysdiv_code_to_x2[] = {
+ 4, 5, 6, 7, 8, 9, 10, 14,
+ 12, 16, 18, 22, 20, 24, 26, 30,
+ 28, 32, 34, 38, 36, 40, 42, 46,
+ 44, 48, 50, 54, 52, 56, 58, 62,
+ 60, 64, 66,
+ };
+ int divcode;
+
+ divcode = get_bit_field(&clkregs->scfr2, 26, 6);
+ return sysdiv_code_to_x2[divcode];
+}
+
+/*
+ * get the CPMF value and translate it into a multiplier factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * multiplier ratio is fractional
+ */
+static int get_cpmf_mult_x2(void)
+{
+ static int cpmf_to_mult[] = {
+ 72, 2, 2, 3, 4, 5, 6, 7,
+ };
+ int cpmf;
+
+ cpmf = get_bit_field(&clkregs->spmr, 16, 4);
+ return cpmf_to_mult[cpmf];
+}
+
+/*
+ * some of the clock dividers do scale in a linear way, yet not all of
+ * their bit combinations are legal; use a divider table to get a
+ * resulting set of applicable divider values
+ */
+
+/* applies to the IPS_DIV, and PCI_DIV values */
+static struct clk_div_table divtab_2346[] = {
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .val = 6, .div = 6, },
+ { .div = 0, },
+};
+
+/* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
+static struct clk_div_table divtab_1234[] = {
+ { .val = 1, .div = 1, },
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 3, },
+ { .val = 4, .div = 4, },
+ { .div = 0, },
+};
+
+static int get_freq_from_dt(char *propname)
+{
+ struct device_node *np;
+ const unsigned int *prop;
+ int val;
+
+ val = 0;
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
+ if (np) {
+ prop = of_get_property(np, propname, NULL);
+ if (prop)
+ val = *prop;
+ of_node_put(np);
+ }
+ return val;
+}
+
+static void mpc512x_clk_preset_data(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++)
+ clks[i] = ERR_PTR(-ENODEV);
+}
+
+/*
+ * - receives the "bus frequency" from the caller (that's the IPS clock
+ * rate, the historical source of clock information)
+ * - fetches the system PLL multiplier and divider values as well as the
+ * IPS divider value from hardware
+ * - determines the REF clock rate either from the XTAL/OSC spec (if
+ * there is a device tree node describing the oscillator) or from the
+ * IPS bus clock (supported for backwards compatibility, such that
+ * setups without XTAL/OSC specs keep working)
+ * - creates the "ref" clock item in the clock tree, such that
+ * subsequent code can create the remainder of the hierarchy (REF ->
+ * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
+ * values
+ */
+static void mpc512x_clk_setup_ref_clock(int bus_freq,
+ int *sys_mul, int *sys_div, int *ips_div)
+{
+ struct clk *osc_clk;
+ int calc_freq;
+
+ /* fetch mul/div factors from the hardware */
+ *sys_mul = get_spmf_mult();
+ *sys_mul *= 2; /* compensate for the fractional divider */
+ *sys_div = get_sys_div_x2();
+ *ips_div = get_bit_field(&clkregs->scfr1, 23, 3);
+
+ /* lookup the oscillator node */
+ osc_clk = clk_get(NULL, "osc");
+ if (osc_clk) {
+ /* descend REF directly from OSC, verify the IPS rate */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1);
+ calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]);
+ calc_freq *= *sys_mul;
+ calc_freq /= *sys_div;
+ calc_freq /= 2;
+ calc_freq /= *ips_div;
+ if (bus_freq && calc_freq != bus_freq)
+ pr_warn("calc rate %d != OF spec %d\n",
+ calc_freq, bus_freq);
+ } else {
+ /* calculate OSC rate and create REF from the freq value */
+ calc_freq = bus_freq; /* start with IPS */
+ calc_freq *= *ips_div; /* IPS -> CSB */
+ calc_freq *= 2; /* CSB -> SYS */
+ calc_freq *= *sys_div; /* SYS -> PLL out */
+ calc_freq /= *sys_mul; /* PLL out -> REF == OSC */
+ clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq);
+ }
+}
+
+/*
+ * helper code for the MCLK subtree setup
+ *
+ * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
+ * suggests that all instances of the "PSC clock generation" are equal,
+ * and that one might re-use the PSC setup for MSCAN clock generation
+ * (section 5.2.5) as well, at least the logic if not the data for
+ * description
+ *
+ * the details (starting at page 5-20) show differences in the specific
+ * inputs of the first mux stage ("can clk in", "spdif tx"), and the
+ * factual non-availability of the second mux stage (it's present yet
+ * only one input is valid)
+ *
+ * the MSCAN clock related registers (starting at page 5-35) all
+ * reference "spdif clk" at the first mux stage and don't mention any
+ * "can clk" at all, which somehow is unexpected
+ *
+ * TODO re-check the document, and clarify whether the RM is correct in
+ * the overview or in the details, and whether the difference is a
+ * clipboard induced error or results from chip revisions
+ *
+ * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
+ * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
+ * first a doc update is required which better reflects reality in the
+ * SoC before the implementation should follow while no questions remain
+ */
+
+/*
+ * note that this declaration raises a checkpatch warning, but
+ * it's the very data type which <linux/clk-provider.h> expects,
+ * making this declaration pass checkpatch will break compilation
+ */
+static const char *parent_names_mux0[] = {
+ "sys", "ref", "psc-mclk-in", "spdif-tx",
+};
+
+enum mclk_type {
+ MCLK_TYPE_PSC,
+ MCLK_TYPE_MSCAN,
+ MCLK_TYPE_SPDIF,
+};
+
+struct mclk_setup_data {
+ enum mclk_type type;
+ int comp_idx;
+ bool has_mclk1;
+ int bit_sccr1, bit_sccr2;
+ const char *name_mux0;
+ const char *name_en0;
+ const char *name_div0;
+ const char *parent_names_mux1[2];
+ const char *name_mux1;
+ const char *name_mclk;
+};
+
+#define MCLK_SETUP_DATA_PSC(id) { \
+ MCLK_TYPE_PSC, id, \
+ 0, 27 - id, -1, \
+ "psc" #id "-mux0", \
+ "psc" #id "-en0", \
+ "psc" #id "_mclk_div", \
+ { "psc" #id "_mclk_div", "dummy", }, \
+ "psc" #id "_mclk_out", \
+ "psc" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_MSCAN(id) { \
+ MCLK_TYPE_MSCAN, id, \
+ 0, -1, 25, \
+ "mscan" #id "-mux0", \
+ "mscan" #id "-en0", \
+ "mscan" #id "_mclk_div", \
+ { "mscan" #id "_mclk_div", "dummy", }, \
+ "mscan" #id "_mclk_out", \
+ "mscan" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_SPDIF { \
+ MCLK_TYPE_SPDIF, 0, \
+ 1, -1, 23, \
+ "spdif-mux0", \
+ "spdif-en0", \
+ "spdif_mclk_div", \
+ { "spdif_mclk_div", "spdif-rx", }, \
+ "spdif_mclk_out", \
+ "spdif_mclk", \
+}
+
+static struct mclk_setup_data mclk_psc_data[] = {
+ MCLK_SETUP_DATA_PSC(0),
+ MCLK_SETUP_DATA_PSC(1),
+ MCLK_SETUP_DATA_PSC(2),
+ MCLK_SETUP_DATA_PSC(3),
+ MCLK_SETUP_DATA_PSC(4),
+ MCLK_SETUP_DATA_PSC(5),
+ MCLK_SETUP_DATA_PSC(6),
+ MCLK_SETUP_DATA_PSC(7),
+ MCLK_SETUP_DATA_PSC(8),
+ MCLK_SETUP_DATA_PSC(9),
+ MCLK_SETUP_DATA_PSC(10),
+ MCLK_SETUP_DATA_PSC(11),
+};
+
+static struct mclk_setup_data mclk_mscan_data[] = {
+ MCLK_SETUP_DATA_MSCAN(0),
+ MCLK_SETUP_DATA_MSCAN(1),
+ MCLK_SETUP_DATA_MSCAN(2),
+ MCLK_SETUP_DATA_MSCAN(3),
+};
+
+static struct mclk_setup_data mclk_spdif_data[] = {
+ MCLK_SETUP_DATA_SPDIF,
+};
+
+/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
+static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
+{
+ size_t clks_idx_pub, clks_idx_int;
+ u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */
+ u32 __iomem *sccr_reg; /* system clock control register (enable) */
+ int sccr_bit;
+ int div;
+
+ /* derive a few parameters from the component type and index */
+ switch (entry->type) {
+ case MCLK_TYPE_PSC:
+ clks_idx_pub = MPC512x_CLK_PSC0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->psc_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_MSCAN:
+ clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + entry->comp_idx;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + entry->comp_idx) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->mscan_ccr[entry->comp_idx];
+ break;
+ case MCLK_TYPE_SPDIF:
+ clks_idx_pub = MPC512x_CLK_SPDIF_MCLK;
+ clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+ + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
+ mccr_reg = &clkregs->spccr;
+ break;
+ default:
+ return;
+ }
+ if (entry->bit_sccr1 >= 0) {
+ sccr_reg = &clkregs->sccr1;
+ sccr_bit = entry->bit_sccr1;
+ } else if (entry->bit_sccr2 >= 0) {
+ sccr_reg = &clkregs->sccr2;
+ sccr_bit = entry->bit_sccr2;
+ } else {
+ sccr_reg = NULL;
+ }
+
+ /*
+ * this was grabbed from the PPC_CLOCK implementation, which
+ * enforced a specific MCLK divider while the clock was gated
+ * during setup (that's a documented hardware requirement)
+ *
+ * the PPC_CLOCK implementation might even have violated the
+ * "MCLK <= IPS" constraint, the fixed divider value of 1
+ * results in a divider of 2 and thus MCLK = SYS/2 which equals
+ * CSB which is greater than IPS; the serial port setup may have
+ * adjusted the divider which the clock setup might have left in
+ * an undesirable state
+ *
+ * initial setup is:
+ * - MCLK 0 from SYS
+ * - MCLK DIV such to not exceed the IPS clock
+ * - MCLK 0 enabled
+ * - MCLK 1 from MCLK DIV
+ */
+ div = clk_get_rate(clks[MPC512x_CLK_SYS]);
+ div /= clk_get_rate(clks[MPC512x_CLK_IPS]);
+ out_be32(mccr_reg, (0 << 16));
+ out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
+ out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
+
+ /*
+ * create the 'struct clk' items of the MCLK's clock subtree
+ *
+ * note that by design we always create all nodes and won't take
+ * shortcuts here, because
+ * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
+ * selectable inputs to the CFM while those who "actually use"
+ * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
+ * for their bitrate
+ * - in the absence of "aliases" for clocks we need to create
+ * individial 'struct clk' items for whatever might get
+ * referenced or looked up, even if several of those items are
+ * identical from the logical POV (their rate value)
+ * - for easier future maintenance and for better reflection of
+ * the SoC's documentation, it appears appropriate to generate
+ * clock items even for those muxers which actually are NOPs
+ * (those with two inputs of which one is reserved)
+ */
+ clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed(
+ entry->name_mux0,
+ &parent_names_mux0[0], ARRAY_SIZE(parent_names_mux0),
+ mccr_reg, 14, 2);
+ clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated(
+ entry->name_en0, entry->name_mux0,
+ mccr_reg, 16);
+ clks[clks_idx_int + MCLK_IDX_DIV0] = mpc512x_clk_divider(
+ entry->name_div0,
+ entry->name_en0, CLK_SET_RATE_GATE,
+ mccr_reg, 17, 15, 0);
+ if (entry->has_mclk1) {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_muxed(
+ entry->name_mux1,
+ &entry->parent_names_mux1[0],
+ ARRAY_SIZE(entry->parent_names_mux1),
+ mccr_reg, 7, 1);
+ } else {
+ clks[clks_idx_int + MCLK_IDX_MUX1] = mpc512x_clk_factor(
+ entry->name_mux1, entry->parent_names_mux1[0],
+ 1, 1);
+ }
+ if (sccr_reg) {
+ clks[clks_idx_pub] = mpc512x_clk_gated(
+ entry->name_mclk,
+ entry->name_mux1, sccr_reg, sccr_bit);
+ } else {
+ clks[clks_idx_pub] = mpc512x_clk_factor(
+ entry->name_mclk,
+ entry->name_mux1, 1, 1);
+ }
+
+ /*
+ * without this "clock device" registration, "simple" lookups in
+ * the SPI master initialization and serial port setup will fail
+ *
+ * those drivers need to get adjusted to lookup their required
+ * clocks from device tree specs, and device tree nodes need to
+ * provide the clock specs, before this clkdev registration
+ * becomes obsolete
+ */
+ clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
+}
+
+static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
+{
+ while (count-- > 0)
+ mpc512x_clk_setup_mclk(table++);
+}
+
+static void mpc512x_clk_setup_clock_tree(int busfreq)
+{
+ int sys_mul, sys_div, ips_div;
+ int mul, div;
+ int freq;
+
+ /*
+ * TODO
+ * - consider whether to handle clocks which have both gates and
+ * dividers via intermediates or by means of composites
+ * - fractional dividers appear to not map well to composites
+ * since they can be seen as a fixed multiplier and an
+ * adjustable divider, while composites can only combine at
+ * most one of a mux, div, and gate each into one 'struct clk'
+ * item
+ * - PSC/MSCAN/SPDIF clock generation OTOH already is very
+ * specific and cannot get mapped to componsites (at least not
+ * a single one, maybe two of them, but see the comment about
+ * "intermediates are referenced from elsewhere, too")
+ * - trim the list of auto-enabled clocks after drivers acquire
+ * them correctly as needed
+ */
+
+ /* regardless of whether XTAL/OSC exists, have REF created */
+ mpc512x_clk_setup_ref_clock(busfreq, &sys_mul, &sys_div, &ips_div);
+
+ /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
+ clks[MPC512x_CLK_SYS] = mpc512x_clk_factor("sys", "ref",
+ sys_mul, sys_div);
+ clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2);
+ clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb",
+ &clkregs->scfr1, 23, 3,
+ divtab_2346);
+
+ /* now setup anything below SYS and CSB and IPS */
+ clks[MPC512x_CLK_DDR_UG] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2);
+ clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0,
+ &clkregs->scfr2, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+ clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1);
+ clks[MPC512x_CLK_DIU_UG] = mpc512x_clk_divider("diu-ug", "diu-x4", 0,
+ &clkregs->scfr1, 0, 8,
+ CLK_DIVIDER_ONE_BASED);
+
+ /*
+ * the "power architecture PLL" was setup from data which was
+ * sampled from the reset config word, at this point in time the
+ * configuration can be considered fixed and read only (i.e. no
+ * longer adjustable, or no longer in need of adjustment), which
+ * is why we don't register a PLL here but assume fixed factors
+ */
+ mul = get_cpmf_mult_x2();
+ div = 2; /* compensate for the fractional factor */
+ clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div);
+
+ clks[MPC512x_CLK_MBX_BUS_UG] = mpc512x_clk_factor("mbx-bus-ug", "csb",
+ 1, 2);
+ clks[MPC512x_CLK_MBX_UG] = mpc512x_clk_divtable("mbx-ug", "mbx-bus-ug",
+ &clkregs->scfr1, 14, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_MBX_3D_UG] = mpc512x_clk_factor("mbx-3d-ug", "mbx-ug",
+ 1, 1);
+ clks[MPC512x_CLK_PCI_UG] = mpc512x_clk_divtable("pci-ug", "csb",
+ &clkregs->scfr1, 20, 3,
+ divtab_2346);
+ clks[MPC512x_CLK_NFC_UG] = mpc512x_clk_divtable("nfc-ug", "ips",
+ &clkregs->scfr1, 8, 3,
+ divtab_1234);
+ clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips",
+ &clkregs->scfr1, 11, 3,
+ divtab_1234);
+
+ clks[MPC512x_CLK_LPC] = mpc512x_clk_gated("lpc", "lpc-ug",
+ &clkregs->sccr1, 30);
+ clks[MPC512x_CLK_NFC] = mpc512x_clk_gated("nfc", "nfc-ug",
+ &clkregs->sccr1, 29);
+ clks[MPC512x_CLK_PATA] = mpc512x_clk_gated("pata", "ips",
+ &clkregs->sccr1, 28);
+ mpc512x_clk_setup_mclks(mclk_psc_data, ARRAY_SIZE(mclk_psc_data));
+ clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips",
+ &clkregs->sccr1, 15);
+ clks[MPC512x_CLK_SATA] = mpc512x_clk_gated("sata", "ips",
+ &clkregs->sccr1, 14);
+ clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips",
+ &clkregs->sccr1, 13);
+ clks[MPC512x_CLK_PCI] = mpc512x_clk_gated("pci", "pci-ug",
+ &clkregs->sccr1, 11);
+ clks[MPC512x_CLK_DDR] = mpc512x_clk_gated("ddr", "ddr-ug",
+ &clkregs->sccr1, 10);
+
+ clks[MPC512x_CLK_DIU] = mpc512x_clk_gated("diu", "diu-ug",
+ &clkregs->sccr2, 31);
+ clks[MPC512x_CLK_AXE] = mpc512x_clk_gated("axe", "csb",
+ &clkregs->sccr2, 30);
+ clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips",
+ &clkregs->sccr2, 29);
+ clks[MPC512x_CLK_USB1] = mpc512x_clk_gated("usb1", "csb",
+ &clkregs->sccr2, 28);
+ clks[MPC512x_CLK_USB2] = mpc512x_clk_gated("usb2", "csb",
+ &clkregs->sccr2, 27);
+ clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips",
+ &clkregs->sccr2, 26);
+ mpc512x_clk_setup_mclks(mclk_mscan_data, ARRAY_SIZE(mclk_mscan_data));
+ clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug",
+ &clkregs->sccr2, 24);
+ mpc512x_clk_setup_mclks(mclk_spdif_data, ARRAY_SIZE(mclk_spdif_data));
+ clks[MPC512x_CLK_MBX_BUS] = mpc512x_clk_gated("mbx-bus", "mbx-bus-ug",
+ &clkregs->sccr2, 22);
+ clks[MPC512x_CLK_MBX] = mpc512x_clk_gated("mbx", "mbx-ug",
+ &clkregs->sccr2, 21);
+ clks[MPC512x_CLK_MBX_3D] = mpc512x_clk_gated("mbx-3d", "mbx-3d-ug",
+ &clkregs->sccr2, 20);
+ clks[MPC512x_CLK_IIM] = mpc512x_clk_gated("iim", "csb",
+ &clkregs->sccr2, 19);
+ clks[MPC512x_CLK_VIU] = mpc512x_clk_gated("viu", "csb",
+ &clkregs->sccr2, 18);
+ clks[MPC512x_CLK_SDHC_2] = mpc512x_clk_gated("sdhc-2", "sdhc-ug",
+ &clkregs->sccr2, 17);
+
+ /*
+ * externally provided clocks (when implemented in hardware,
+ * device tree may specify values which otherwise were unknown)
+ */
+ freq = get_freq_from_dt("psc_mclk_in");
+ if (!freq)
+ freq = 25000000;
+ clks[MPC512x_CLK_PSC_MCLK_IN] = mpc512x_clk_fixed("psc_mclk_in", freq);
+ freq = get_freq_from_dt("spdif_tx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_tx_in", freq);
+ freq = get_freq_from_dt("spdif_rx_in");
+ clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed("spdif_rx_in", freq);
+
+ /* fixed frequency for AC97, always 24.567MHz */
+ clks[MPC512x_CLK_AC97] = mpc512x_clk_fixed("ac97", 24567000);
+
+ pr_debug("clock tree setup complete\n");
+ freq = clk_get_rate(clks[MPC512x_CLK_E300]);
+ pr_debug("derived PPC freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_IPS]);
+ pr_debug("derived IPS freq [%d]\n", freq);
+ freq = clk_get_rate(clks[MPC512x_CLK_LPC]);
+ pr_debug("derived LPC freq [%d]\n", freq);
+
+ /* enable some of the clocks here unconditionally because ... */
+ pr_debug("automatically enabling some clocks\n");
+ /* some are essential yet never get claimed by any driver */
+ clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
+ clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */
+ clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
+ clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
+ clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
+ /* some are required yet no dependencies were declared */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
+ /* some are not yet acquired by their respective drivers */
+ clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
+ clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
+ clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
+ clk_prepare_enable(clks[MPC512x_CLK_I2C]);
+ /*
+ * some have their individual clock subtree with separate clock
+ * items and their individual enable counters, yet share a
+ * common gate (refer to the same register location) while the
+ * common clock driver code is not aware of the fact and the
+ * platform's code doesn't provide specific support either
+ *
+ * what might happen is that e.g. enabling two MSCAN clock items
+ * and disabling one of them will disable the common gate and
+ * thus break the other MSCAN clock as well
+ */
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN0_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN1_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN2_MCLK]);
+ clk_prepare_enable(clks[MPC512x_CLK_MSCAN3_MCLK]);
+}
+
+/*
+ * registers the set of public clocks (those listed in the dt-bindings/
+ * header file) for OF lookups, keeps the intermediates private to us
+ */
+static void mpc5121_clk_register_of_provider(struct device_node *np)
+{
+ clk_data.clks = clks;
+ clk_data.clk_num = MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_SIZE() */
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+int __init mpc5121_clk_init(void)
+{
+ struct device_node *clk_np;
+ int busfreq;
+
+ /* map the clock control registers */
+ clk_np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ if (!clk_np)
+ return -ENODEV;
+ clkregs = of_iomap(clk_np, 0);
+ WARN_ON(!clkregs);
+
+ /* invalidate all not yet registered clock slots */
+ mpc512x_clk_preset_data();
+
+ /*
+ * have the device tree scanned for "fixed-clock" nodes (which
+ * includes the oscillator node if the board's DT provides one)
+ */
+ of_clk_init(NULL);
+
+ /*
+ * add a dummy clock for those situations where a clock spec is
+ * required yet no real clock is involved
+ */
+ clks[MPC512x_CLK_DUMMY] = mpc512x_clk_fixed("dummy", 0);
+
+ /*
+ * have all the real nodes in the clock tree populated from REF
+ * down to all leaves, either starting from the OSC node or from
+ * a REF root that was created from the IPS bus clock input
+ */
+ busfreq = get_freq_from_dt("bus-frequency");
+ mpc512x_clk_setup_clock_tree(busfreq);
+
+ /* register as an OF clock provider */
+ mpc5121_clk_register_of_provider(clk_np);
+
+ return 0;
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c4f7799..7f8fc64 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -497,6 +497,20 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
* for improved portability across platforms
*/
+#if IS_ENABLED(CONFIG_PPC)
+
+static inline u32 clk_readl(u32 __iomem *reg)
+{
+ return ioread32be(reg);
+}
+
+static inline void clk_writel(u32 val, u32 __iomem *reg)
+{
+ iowrite32be(val, reg);
+}
+
+#else /* platform dependent I/O accessors */
+
static inline u32 clk_readl(u32 __iomem *reg)
{
return readl(reg);
@@ -507,5 +521,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
writel(val, reg);
}
+#endif /* platform dependent I/O accessors */
+
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 10/24] dts: mpc512x: add clock specs for client lookups
2013-07-18 17:00 ` Gerhard Sittig
(?)
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
this addresses the client side of device tree based clock lookups:
add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu,
viu, mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the
shared mpc5121.dtsi include
these specs map 'clock-names' encoded in drivers to their respective
'struct clk' items in the platform's clock driver; some drivers
still need to learn how to lookup OF clocks, other drivers will
transparently probe successfully on MPC512x as well (sdhc)
few 'clock-names' (nfc, viu) use strings that are encoded in their
respective drivers to keep up compatibility, an alternative approach
would be to register clkdev items in the platform's clock driver for
the migration period
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 8f4cba0..983da9c 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -51,6 +51,10 @@
compatible = "fsl,mpc5121-mbx";
reg = <0x20000000 0x4000>;
interrupts = <66 0x8>;
+ clocks = <&clks MPC512x_CLK_MBX_BUS>,
+ <&clks MPC512x_CLK_MBX_3D>,
+ <&clks MPC512x_CLK_MBX>;
+ clock-names = "mbx-bus", "mbx-3d", "mbx";
};
sram@30000000 {
@@ -64,6 +68,8 @@
interrupts = <6 8>;
#address-cells = <1>;
#size-cells = <1>;
+ clocks = <&clks MPC512x_CLK_NFC>;
+ clock-names = "nfc_clk"; /* backwards compat */
};
localbus@80000020 {
@@ -153,12 +159,22 @@
compatible = "fsl,mpc5121-mscan";
reg = <0x1300 0x80>;
interrupts = <12 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN0_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can@1380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x1380 0x80>;
interrupts = <13 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN1_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
sdhc@1500 {
@@ -167,6 +183,9 @@
interrupts = <8 0x8>;
dmas = <&dma0 30>;
dma-names = "rx-tx";
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SDHC>;
+ clock-names = "ipg", "per";
};
i2c@1700 {
@@ -175,6 +194,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c@1720 {
@@ -183,6 +204,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c@1740 {
@@ -191,6 +214,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2ccontrol@1760 {
@@ -202,30 +227,46 @@
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
+ clocks = <&clks MPC512x_CLK_AXE>;
+ clock-names = "per";
};
display@2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
+ clocks = <&clks MPC512x_CLK_DIU>;
+ clock-names = "per";
};
can@2300 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2300 0x80>;
interrupts = <90 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN2_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can@2380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2380 0x80>;
interrupts = <91 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN3_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
viu@2400 {
compatible = "fsl,mpc5121-viu";
reg = <0x2400 0x400>;
interrupts = <67 0x8>;
+ clocks = <&clks MPC512x_CLK_VIU>;
+ clock-names = "viu_clk"; /* backwards compat */
};
mdio@2800 {
@@ -233,6 +274,8 @@
reg = <0x2800 0x800>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
eth0: ethernet@2800 {
@@ -241,6 +284,8 @@
reg = <0x2800 0x800>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
/* USB1 using external ULPI PHY */
@@ -252,6 +297,8 @@
interrupts = <43 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
+ clocks = <&clks MPC512x_CLK_USB1>;
+ clock-names = "per";
};
/* USB0 using internal UTMI PHY */
@@ -263,6 +310,8 @@
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
+ clocks = <&clks MPC512x_CLK_USB2>;
+ clock-names = "per";
};
/* IO control */
@@ -281,6 +330,8 @@
compatible = "fsl,mpc5121-pata";
reg = <0x10200 0x100>;
interrupts = <5 0x8>;
+ clocks = <&clks MPC512x_CLK_PATA>;
+ clock-names = "per";
};
/* 512x PSCs are not 52xx PSC compatible */
@@ -292,6 +343,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC0_MCLK>;
+ clock-names = "mclk";
};
/* PSC1 */
@@ -301,6 +354,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC1_MCLK>;
+ clock-names = "mclk";
};
/* PSC2 */
@@ -310,6 +365,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC2_MCLK>;
+ clock-names = "mclk";
};
/* PSC3 */
@@ -319,6 +376,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC3_MCLK>;
+ clock-names = "mclk";
};
/* PSC4 */
@@ -328,6 +387,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC4_MCLK>;
+ clock-names = "mclk";
};
/* PSC5 */
@@ -337,6 +398,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC5_MCLK>;
+ clock-names = "mclk";
};
/* PSC6 */
@@ -346,6 +409,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC6_MCLK>;
+ clock-names = "mclk";
};
/* PSC7 */
@@ -355,6 +420,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC7_MCLK>;
+ clock-names = "mclk";
};
/* PSC8 */
@@ -364,6 +431,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC8_MCLK>;
+ clock-names = "mclk";
};
/* PSC9 */
@@ -373,6 +442,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC9_MCLK>;
+ clock-names = "mclk";
};
/* PSC10 */
@@ -382,6 +453,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC10_MCLK>;
+ clock-names = "mclk";
};
/* PSC11 */
@@ -391,12 +464,16 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC11_MCLK>;
+ clock-names = "mclk";
};
pscfifo@11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
+ clocks = <&clks MPC512x_CLK_PSC_FIFO>;
+ clock-names = "per";
};
dma0: dma@14000 {
@@ -414,6 +491,8 @@
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
+ clocks = <&clks MPC512x_CLK_PCI>;
+ clock-names = "per";
reg = <0x80008500 0x100 /* internal registers */
0x80008300 0x8>; /* config space access registers */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 10/24] dts: mpc512x: add clock specs for client lookups
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
this addresses the client side of device tree based clock lookups:
add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu,
viu, mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the
shared mpc5121.dtsi include
these specs map 'clock-names' encoded in drivers to their respective
'struct clk' items in the platform's clock driver; some drivers
still need to learn how to lookup OF clocks, other drivers will
transparently probe successfully on MPC512x as well (sdhc)
few 'clock-names' (nfc, viu) use strings that are encoded in their
respective drivers to keep up compatibility, an alternative approach
would be to register clkdev items in the platform's clock driver for
the migration period
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 8f4cba0..983da9c 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -51,6 +51,10 @@
compatible = "fsl,mpc5121-mbx";
reg = <0x20000000 0x4000>;
interrupts = <66 0x8>;
+ clocks = <&clks MPC512x_CLK_MBX_BUS>,
+ <&clks MPC512x_CLK_MBX_3D>,
+ <&clks MPC512x_CLK_MBX>;
+ clock-names = "mbx-bus", "mbx-3d", "mbx";
};
sram@30000000 {
@@ -64,6 +68,8 @@
interrupts = <6 8>;
#address-cells = <1>;
#size-cells = <1>;
+ clocks = <&clks MPC512x_CLK_NFC>;
+ clock-names = "nfc_clk"; /* backwards compat */
};
localbus@80000020 {
@@ -153,12 +159,22 @@
compatible = "fsl,mpc5121-mscan";
reg = <0x1300 0x80>;
interrupts = <12 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN0_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can@1380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x1380 0x80>;
interrupts = <13 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN1_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
sdhc@1500 {
@@ -167,6 +183,9 @@
interrupts = <8 0x8>;
dmas = <&dma0 30>;
dma-names = "rx-tx";
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SDHC>;
+ clock-names = "ipg", "per";
};
i2c@1700 {
@@ -175,6 +194,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c@1720 {
@@ -183,6 +204,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c@1740 {
@@ -191,6 +214,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2ccontrol@1760 {
@@ -202,30 +227,46 @@
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
+ clocks = <&clks MPC512x_CLK_AXE>;
+ clock-names = "per";
};
display@2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
+ clocks = <&clks MPC512x_CLK_DIU>;
+ clock-names = "per";
};
can@2300 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2300 0x80>;
interrupts = <90 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN2_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can@2380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2380 0x80>;
interrupts = <91 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN3_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
viu@2400 {
compatible = "fsl,mpc5121-viu";
reg = <0x2400 0x400>;
interrupts = <67 0x8>;
+ clocks = <&clks MPC512x_CLK_VIU>;
+ clock-names = "viu_clk"; /* backwards compat */
};
mdio@2800 {
@@ -233,6 +274,8 @@
reg = <0x2800 0x800>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
eth0: ethernet@2800 {
@@ -241,6 +284,8 @@
reg = <0x2800 0x800>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
/* USB1 using external ULPI PHY */
@@ -252,6 +297,8 @@
interrupts = <43 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
+ clocks = <&clks MPC512x_CLK_USB1>;
+ clock-names = "per";
};
/* USB0 using internal UTMI PHY */
@@ -263,6 +310,8 @@
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
+ clocks = <&clks MPC512x_CLK_USB2>;
+ clock-names = "per";
};
/* IO control */
@@ -281,6 +330,8 @@
compatible = "fsl,mpc5121-pata";
reg = <0x10200 0x100>;
interrupts = <5 0x8>;
+ clocks = <&clks MPC512x_CLK_PATA>;
+ clock-names = "per";
};
/* 512x PSCs are not 52xx PSC compatible */
@@ -292,6 +343,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC0_MCLK>;
+ clock-names = "mclk";
};
/* PSC1 */
@@ -301,6 +354,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC1_MCLK>;
+ clock-names = "mclk";
};
/* PSC2 */
@@ -310,6 +365,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC2_MCLK>;
+ clock-names = "mclk";
};
/* PSC3 */
@@ -319,6 +376,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC3_MCLK>;
+ clock-names = "mclk";
};
/* PSC4 */
@@ -328,6 +387,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC4_MCLK>;
+ clock-names = "mclk";
};
/* PSC5 */
@@ -337,6 +398,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC5_MCLK>;
+ clock-names = "mclk";
};
/* PSC6 */
@@ -346,6 +409,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC6_MCLK>;
+ clock-names = "mclk";
};
/* PSC7 */
@@ -355,6 +420,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC7_MCLK>;
+ clock-names = "mclk";
};
/* PSC8 */
@@ -364,6 +431,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC8_MCLK>;
+ clock-names = "mclk";
};
/* PSC9 */
@@ -373,6 +442,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC9_MCLK>;
+ clock-names = "mclk";
};
/* PSC10 */
@@ -382,6 +453,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC10_MCLK>;
+ clock-names = "mclk";
};
/* PSC11 */
@@ -391,12 +464,16 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC11_MCLK>;
+ clock-names = "mclk";
};
pscfifo@11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
+ clocks = <&clks MPC512x_CLK_PSC_FIFO>;
+ clock-names = "per";
};
dma0: dma@14000 {
@@ -414,6 +491,8 @@
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
+ clocks = <&clks MPC512x_CLK_PCI>;
+ clock-names = "per";
reg = <0x80008500 0x100 /* internal registers */
0x80008300 0x8>; /* config space access registers */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 10/24] dts: mpc512x: add clock specs for client lookups
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
this addresses the client side of device tree based clock lookups:
add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu,
viu, mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the
shared mpc5121.dtsi include
these specs map 'clock-names' encoded in drivers to their respective
'struct clk' items in the platform's clock driver; some drivers
still need to learn how to lookup OF clocks, other drivers will
transparently probe successfully on MPC512x as well (sdhc)
few 'clock-names' (nfc, viu) use strings that are encoded in their
respective drivers to keep up compatibility, an alternative approach
would be to register clkdev items in the platform's clock driver for
the migration period
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 8f4cba0..983da9c 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -51,6 +51,10 @@
compatible = "fsl,mpc5121-mbx";
reg = <0x20000000 0x4000>;
interrupts = <66 0x8>;
+ clocks = <&clks MPC512x_CLK_MBX_BUS>,
+ <&clks MPC512x_CLK_MBX_3D>,
+ <&clks MPC512x_CLK_MBX>;
+ clock-names = "mbx-bus", "mbx-3d", "mbx";
};
sram at 30000000 {
@@ -64,6 +68,8 @@
interrupts = <6 8>;
#address-cells = <1>;
#size-cells = <1>;
+ clocks = <&clks MPC512x_CLK_NFC>;
+ clock-names = "nfc_clk"; /* backwards compat */
};
localbus at 80000020 {
@@ -153,12 +159,22 @@
compatible = "fsl,mpc5121-mscan";
reg = <0x1300 0x80>;
interrupts = <12 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN0_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can at 1380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x1380 0x80>;
interrupts = <13 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN1_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
sdhc at 1500 {
@@ -167,6 +183,9 @@
interrupts = <8 0x8>;
dmas = <&dma0 30>;
dma-names = "rx-tx";
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SDHC>;
+ clock-names = "ipg", "per";
};
i2c at 1700 {
@@ -175,6 +194,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c at 1720 {
@@ -183,6 +204,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2c at 1740 {
@@ -191,6 +214,8 @@
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
+ clocks = <&clks MPC512x_CLK_I2C>;
+ clock-names = "per";
};
i2ccontrol at 1760 {
@@ -202,30 +227,46 @@
compatible = "fsl,mpc5121-axe";
reg = <0x2000 0x100>;
interrupts = <42 0x8>;
+ clocks = <&clks MPC512x_CLK_AXE>;
+ clock-names = "per";
};
display at 2100 {
compatible = "fsl,mpc5121-diu";
reg = <0x2100 0x100>;
interrupts = <64 0x8>;
+ clocks = <&clks MPC512x_CLK_DIU>;
+ clock-names = "per";
};
can at 2300 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2300 0x80>;
interrupts = <90 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN2_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
can at 2380 {
compatible = "fsl,mpc5121-mscan";
reg = <0x2380 0x80>;
interrupts = <91 0x8>;
+ clocks = <&clks MPC512x_CLK_IPS>,
+ <&clks MPC512x_CLK_SYS>,
+ <&clks MPC512x_CLK_REF>,
+ <&clks MPC512x_CLK_MSCAN3_MCLK>;
+ clock-names = "ips", "sys", "ref", "mclk";
};
viu at 2400 {
compatible = "fsl,mpc5121-viu";
reg = <0x2400 0x400>;
interrupts = <67 0x8>;
+ clocks = <&clks MPC512x_CLK_VIU>;
+ clock-names = "viu_clk"; /* backwards compat */
};
mdio at 2800 {
@@ -233,6 +274,8 @@
reg = <0x2800 0x800>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
eth0: ethernet at 2800 {
@@ -241,6 +284,8 @@
reg = <0x2800 0x800>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <4 0x8>;
+ clocks = <&clks MPC512x_CLK_FEC>;
+ clock-names = "per";
};
/* USB1 using external ULPI PHY */
@@ -252,6 +297,8 @@
interrupts = <43 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
+ clocks = <&clks MPC512x_CLK_USB1>;
+ clock-names = "per";
};
/* USB0 using internal UTMI PHY */
@@ -263,6 +310,8 @@
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
+ clocks = <&clks MPC512x_CLK_USB2>;
+ clock-names = "per";
};
/* IO control */
@@ -281,6 +330,8 @@
compatible = "fsl,mpc5121-pata";
reg = <0x10200 0x100>;
interrupts = <5 0x8>;
+ clocks = <&clks MPC512x_CLK_PATA>;
+ clock-names = "per";
};
/* 512x PSCs are not 52xx PSC compatible */
@@ -292,6 +343,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC0_MCLK>;
+ clock-names = "mclk";
};
/* PSC1 */
@@ -301,6 +354,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC1_MCLK>;
+ clock-names = "mclk";
};
/* PSC2 */
@@ -310,6 +365,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC2_MCLK>;
+ clock-names = "mclk";
};
/* PSC3 */
@@ -319,6 +376,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC3_MCLK>;
+ clock-names = "mclk";
};
/* PSC4 */
@@ -328,6 +387,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC4_MCLK>;
+ clock-names = "mclk";
};
/* PSC5 */
@@ -337,6 +398,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC5_MCLK>;
+ clock-names = "mclk";
};
/* PSC6 */
@@ -346,6 +409,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC6_MCLK>;
+ clock-names = "mclk";
};
/* PSC7 */
@@ -355,6 +420,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC7_MCLK>;
+ clock-names = "mclk";
};
/* PSC8 */
@@ -364,6 +431,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC8_MCLK>;
+ clock-names = "mclk";
};
/* PSC9 */
@@ -373,6 +442,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC9_MCLK>;
+ clock-names = "mclk";
};
/* PSC10 */
@@ -382,6 +453,8 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC10_MCLK>;
+ clock-names = "mclk";
};
/* PSC11 */
@@ -391,12 +464,16 @@
interrupts = <40 0x8>;
fsl,rx-fifo-size = <16>;
fsl,tx-fifo-size = <16>;
+ clocks = <&clks MPC512x_CLK_PSC11_MCLK>;
+ clock-names = "mclk";
};
pscfifo at 11f00 {
compatible = "fsl,mpc5121-psc-fifo";
reg = <0x11f00 0x100>;
interrupts = <40 0x8>;
+ clocks = <&clks MPC512x_CLK_PSC_FIFO>;
+ clock-names = "per";
};
dma0: dma at 14000 {
@@ -414,6 +491,8 @@
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
+ clocks = <&clks MPC512x_CLK_PCI>;
+ clock-names = "per";
reg = <0x80008500 0x100 /* internal registers */
0x80008300 0x8>; /* config space access registers */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 11/24] spi: mpc512x: remove now obsolete clock lookup name
2013-07-18 17:00 ` Gerhard Sittig
(?)
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
after device tree based clock lookup became available, the peripheral
driver need no longer construct clock names which include the PSC index,
remove the "psc%d_mclk" template and unconditionally use "mclk"
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/spi/spi-mpc512x-psc.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 7a32373..b04f094 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -474,8 +474,6 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
struct spi_master *master;
int ret;
void *tempp;
- int psc_num;
- char clk_name[16];
master = spi_alloc_master(dev, sizeof *mps);
if (master == NULL)
@@ -518,9 +516,7 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
goto free_master;
init_completion(&mps->txisrdone);
- psc_num = master->bus_num;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- mps->clk_mclk = clk_get(dev, clk_name);
+ mps->clk_mclk = clk_get(dev, "mclk");
if (IS_ERR(mps->clk_mclk))
goto free_irq;
ret = clk_prepare_enable(mps->clk_mclk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 11/24] spi: mpc512x: remove now obsolete clock lookup name
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
after device tree based clock lookup became available, the peripheral
driver need no longer construct clock names which include the PSC index,
remove the "psc%d_mclk" template and unconditionally use "mclk"
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/spi/spi-mpc512x-psc.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 7a32373..b04f094 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -474,8 +474,6 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
struct spi_master *master;
int ret;
void *tempp;
- int psc_num;
- char clk_name[16];
master = spi_alloc_master(dev, sizeof *mps);
if (master == NULL)
@@ -518,9 +516,7 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
goto free_master;
init_completion(&mps->txisrdone);
- psc_num = master->bus_num;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- mps->clk_mclk = clk_get(dev, clk_name);
+ mps->clk_mclk = clk_get(dev, "mclk");
if (IS_ERR(mps->clk_mclk))
goto free_irq;
ret = clk_prepare_enable(mps->clk_mclk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 11/24] spi: mpc512x: remove now obsolete clock lookup name
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
after device tree based clock lookup became available, the peripheral
driver need no longer construct clock names which include the PSC index,
remove the "psc%d_mclk" template and unconditionally use "mclk"
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/spi/spi-mpc512x-psc.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 7a32373..b04f094 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -474,8 +474,6 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
struct spi_master *master;
int ret;
void *tempp;
- int psc_num;
- char clk_name[16];
master = spi_alloc_master(dev, sizeof *mps);
if (master == NULL)
@@ -518,9 +516,7 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
goto free_master;
init_completion(&mps->txisrdone);
- psc_num = master->bus_num;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- mps->clk_mclk = clk_get(dev, clk_name);
+ mps->clk_mclk = clk_get(dev, "mclk");
if (IS_ERR(mps->clk_mclk))
goto free_irq;
ret = clk_prepare_enable(mps->clk_mclk);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 12/24] serial: mpc512x: remove now obsolete clock lookup name
2013-07-18 17:00 ` Gerhard Sittig
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
after device tree based clock lookup became available, the peripheral
driver need no longer construct clock names which include the PSC index,
remove the "psc%d_mclk" template and unconditionally use "mclk"
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/tty/serial/mpc52xx_uart.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index 98a1f43..8643dcf 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -623,14 +623,11 @@ static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
/* called from within the .request_port() callback (allocation) */
static int mpc512x_psc_alloc_clock(struct uart_port *port)
{
- int psc_num;
- char clk_name[16];
struct clk *clk;
int err;
+ int psc_num;
- psc_num = (port->mapbase & 0xf00) >> 8;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- clk = clk_get(port->dev, clk_name);
+ clk = clk_get(port->dev, "mclk");
if (IS_ERR(clk)) {
dev_err(port->dev, "Failed to get MCLK!\n");
return PTR_ERR(clk);
@@ -641,6 +638,7 @@ static int mpc512x_psc_alloc_clock(struct uart_port *port)
clk_put(clk);
return err;
}
+ psc_num = (port->mapbase & 0xf00) >> 8;
psc_mclk_clk[psc_num] = clk;
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 12/24] serial: mpc512x: remove now obsolete clock lookup name
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
after device tree based clock lookup became available, the peripheral
driver need no longer construct clock names which include the PSC index,
remove the "psc%d_mclk" template and unconditionally use "mclk"
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/tty/serial/mpc52xx_uart.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index 98a1f43..8643dcf 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -623,14 +623,11 @@ static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
/* called from within the .request_port() callback (allocation) */
static int mpc512x_psc_alloc_clock(struct uart_port *port)
{
- int psc_num;
- char clk_name[16];
struct clk *clk;
int err;
+ int psc_num;
- psc_num = (port->mapbase & 0xf00) >> 8;
- snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
- clk = clk_get(port->dev, clk_name);
+ clk = clk_get(port->dev, "mclk");
if (IS_ERR(clk)) {
dev_err(port->dev, "Failed to get MCLK!\n");
return PTR_ERR(clk);
@@ -641,6 +638,7 @@ static int mpc512x_psc_alloc_clock(struct uart_port *port)
clk_put(clk);
return err;
}
+ psc_num = (port->mapbase & 0xf00) >> 8;
psc_mclk_clk[psc_num] = clk;
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 13/24] clk: mpc512x: remove now obsolete clkdev registration
2013-07-18 17:00 ` Gerhard Sittig
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
after the peripheral drivers for UART and SPI mode (both using the PSC
controller) got converted to device tree based clock lookups, the
platform clock driver need no longer provide the "psc%d_mclk" name which
depends on the PSC index number -- remove the clk_register_clkdev() call
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 6627957..b822469 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -12,7 +12,6 @@
*/
#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/io.h>
@@ -529,17 +528,6 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
entry->name_mclk,
entry->name_mux1, 1, 1);
}
-
- /*
- * without this "clock device" registration, "simple" lookups in
- * the SPI master initialization and serial port setup will fail
- *
- * those drivers need to get adjusted to lookup their required
- * clocks from device tree specs, and device tree nodes need to
- * provide the clock specs, before this clkdev registration
- * becomes obsolete
- */
- clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
}
static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 13/24] clk: mpc512x: remove now obsolete clkdev registration
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
after the peripheral drivers for UART and SPI mode (both using the PSC
controller) got converted to device tree based clock lookups, the
platform clock driver need no longer provide the "psc%d_mclk" name which
depends on the PSC index number -- remove the clk_register_clkdev() call
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 6627957..b822469 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -12,7 +12,6 @@
*/
#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/io.h>
@@ -529,17 +528,6 @@ static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry)
entry->name_mclk,
entry->name_mux1, 1, 1);
}
-
- /*
- * without this "clock device" registration, "simple" lookups in
- * the SPI master initialization and serial port setup will fail
- *
- * those drivers need to get adjusted to lookup their required
- * clocks from device tree specs, and device tree nodes need to
- * provide the clock specs, before this clkdev registration
- * becomes obsolete
- */
- clk_register_clkdev(clks[clks_idx_pub], entry->name_mclk, NULL);
}
static void mpc512x_clk_setup_mclks(struct mclk_setup_data *table, size_t count)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 14/24] serial: mpc512x: setup the PSC FIFO clock as well
2013-07-18 17:00 ` Gerhard Sittig
@ 2013-07-18 17:00 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
prepare and enable the FIFO clock upon PSC FIFO initialization,
disable and unprepare the FIFO clock upon PSC FIFO uninitialization,
remove the pre-enable workaround from the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 2 --
drivers/tty/serial/mpc52xx_uart.c | 39 +++++++++++++++++++++----
2 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index b822469..99d197d 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -689,8 +689,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
- /* some are required yet no dependencies were declared */
- clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index 8643dcf..3fdadf9 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -421,6 +421,7 @@ struct psc_fifoc {
static struct psc_fifoc __iomem *psc_fifoc;
static unsigned int psc_fifoc_irq;
+static struct clk *psc_fifoc_clk;
static void mpc512x_psc_fifo_init(struct uart_port *port)
{
@@ -574,30 +575,56 @@ static int __init mpc512x_psc_fifoc_init(void)
"fsl,mpc5121-psc-fifo");
if (!np) {
pr_err("%s: Can't find FIFOC node\n", __func__);
- return -ENODEV;
+ goto out_err;
+ }
+
+ psc_fifoc_clk = of_clk_get_by_name(np, "per");
+ if (IS_ERR(psc_fifoc_clk)) {
+ pr_err("%s: Can't lookup FIFO clock\n", __func__);
+ goto out_ofnode_put;
+ }
+ if (clk_prepare_enable(psc_fifoc_clk)) {
+ pr_err("%s: Can't enable FIFO clock\n", __func__);
+ goto out_clk_put;
}
psc_fifoc = of_iomap(np, 0);
if (!psc_fifoc) {
pr_err("%s: Can't map FIFOC\n", __func__);
- of_node_put(np);
- return -ENODEV;
+ goto out_clk_disable;
}
psc_fifoc_irq = irq_of_parse_and_map(np, 0);
- of_node_put(np);
if (psc_fifoc_irq == 0) {
pr_err("%s: Can't get FIFOC irq\n", __func__);
- iounmap(psc_fifoc);
- return -ENODEV;
+ goto out_unmap;
}
+ of_node_put(np);
return 0;
+
+out_unmap:
+ iounmap(psc_fifoc);
+out_clk_disable:
+ clk_disable_unprepare(psc_fifoc_clk);
+out_clk_put:
+ clk_put(psc_fifoc_clk);
+out_ofnode_put:
+ of_node_put(np);
+out_err:
+ return -ENODEV;
}
static void __exit mpc512x_psc_fifoc_uninit(void)
{
iounmap(psc_fifoc);
+
+ /* disable the clock, errors are not fatal */
+ if (psc_fifoc_clk && !IS_ERR(psc_fifoc_clk)) {
+ clk_disable_unprepare(psc_fifoc_clk);
+ clk_put(psc_fifoc_clk);
+ psc_fifoc_clk = NULL;
+ }
}
/* 512x specific interrupt handler. The caller holds the port lock */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 14/24] serial: mpc512x: setup the PSC FIFO clock as well
@ 2013-07-18 17:00 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 17:00 UTC (permalink / raw)
To: linux-arm-kernel
prepare and enable the FIFO clock upon PSC FIFO initialization,
disable and unprepare the FIFO clock upon PSC FIFO uninitialization,
remove the pre-enable workaround from the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 2 --
drivers/tty/serial/mpc52xx_uart.c | 39 +++++++++++++++++++++----
2 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index b822469..99d197d 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -689,8 +689,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
- /* some are required yet no dependencies were declared */
- clk_prepare_enable(clks[MPC512x_CLK_PSC_FIFO]);
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index 8643dcf..3fdadf9 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -421,6 +421,7 @@ struct psc_fifoc {
static struct psc_fifoc __iomem *psc_fifoc;
static unsigned int psc_fifoc_irq;
+static struct clk *psc_fifoc_clk;
static void mpc512x_psc_fifo_init(struct uart_port *port)
{
@@ -574,30 +575,56 @@ static int __init mpc512x_psc_fifoc_init(void)
"fsl,mpc5121-psc-fifo");
if (!np) {
pr_err("%s: Can't find FIFOC node\n", __func__);
- return -ENODEV;
+ goto out_err;
+ }
+
+ psc_fifoc_clk = of_clk_get_by_name(np, "per");
+ if (IS_ERR(psc_fifoc_clk)) {
+ pr_err("%s: Can't lookup FIFO clock\n", __func__);
+ goto out_ofnode_put;
+ }
+ if (clk_prepare_enable(psc_fifoc_clk)) {
+ pr_err("%s: Can't enable FIFO clock\n", __func__);
+ goto out_clk_put;
}
psc_fifoc = of_iomap(np, 0);
if (!psc_fifoc) {
pr_err("%s: Can't map FIFOC\n", __func__);
- of_node_put(np);
- return -ENODEV;
+ goto out_clk_disable;
}
psc_fifoc_irq = irq_of_parse_and_map(np, 0);
- of_node_put(np);
if (psc_fifoc_irq == 0) {
pr_err("%s: Can't get FIFOC irq\n", __func__);
- iounmap(psc_fifoc);
- return -ENODEV;
+ goto out_unmap;
}
+ of_node_put(np);
return 0;
+
+out_unmap:
+ iounmap(psc_fifoc);
+out_clk_disable:
+ clk_disable_unprepare(psc_fifoc_clk);
+out_clk_put:
+ clk_put(psc_fifoc_clk);
+out_ofnode_put:
+ of_node_put(np);
+out_err:
+ return -ENODEV;
}
static void __exit mpc512x_psc_fifoc_uninit(void)
{
iounmap(psc_fifoc);
+
+ /* disable the clock, errors are not fatal */
+ if (psc_fifoc_clk && !IS_ERR(psc_fifoc_clk)) {
+ clk_disable_unprepare(psc_fifoc_clk);
+ clk_put(psc_fifoc_clk);
+ psc_fifoc_clk = NULL;
+ }
}
/* 512x specific interrupt handler. The caller holds the port lock */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* Re: [PATCH v1 05/24] clk: wrap I/O access for improved portability
2013-07-18 9:17 ` Russell King - ARM Linux
@ 2013-07-18 17:47 ` Nicolas Pitre
-1 siblings, 0 replies; 432+ messages in thread
From: Nicolas Pitre @ 2013-07-18 17:47 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Mike Turquette, Detlev Zundel, Wolfram Sang, devicetree-discuss,
Greg Kroah-Hartman, Gerhard Sittig, linuxppc-dev, Rob Herring,
Mark Brown, Marc Kleine-Budde, Wolfgang Grandegger,
David Woodhouse, Sascha Hauer, linux-arm-kernel,
Mauro Carvalho Chehab
On Thu, 18 Jul 2013, Russell King - ARM Linux wrote:
> 1. clk_get() and clk_put() are NOT part of the common clock API.
> They're separate - they're part of the clk API, and the infrastructure
> behind that is clkdev, which is a separately owned thing (by me.)
>
> 2. The "contract" of the clk API is defined by the clk API, not by some
> random implementation like the common clock API. The clk API is
> maintained by myself, and is described in include/linux/clk.h
>
> 3. clk_prepare() and clk_unprepare() are functions MUST only be called
> from contexts where sleeping is permitted. These functions MAY sleep
> for whatever reason they require to, and as long as they require to.
> (This is the whole reason these two functions were created in the
> first place.)
>
> 4. clk_enable() and clk_disable() MAY be called from any context, but
> MUST never sleep. If you need to talk over a non-atomic bus for these,
> then these functions should be no-ops, and the code which does that
> must be executed from the clk_prepare()/clk_unprepare() operations.
Could the above be included in some form in Documentation/clk.txt (this
is likely one of the first location people look for information) and
elsewhere if appropriate please?
A *lot* of people are confused by the prepare-enable-disable-unprepare
sequence and when I try to find some rational for the prepare/enable
split I can only direct them to mail archive posts since this is nowhere
to be found in the kernel.
The comments in include/linux/clk.h, while correct, are very terse and
don't provide any insight to the reason why there is a split in the API.
The content of Documentation/clk.txt does refer to prepare and enable
(and their counterparts) but again doesn't provide any clue about the
reason for their existence.
Since there've been several good posts with usage example now buried
into list archives, I think this would go a long way helping people get
it right if those were part of the kernel documentation as well.
Nicolas
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v1 05/24] clk: wrap I/O access for improved portability
@ 2013-07-18 17:47 ` Nicolas Pitre
0 siblings, 0 replies; 432+ messages in thread
From: Nicolas Pitre @ 2013-07-18 17:47 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 18 Jul 2013, Russell King - ARM Linux wrote:
> 1. clk_get() and clk_put() are NOT part of the common clock API.
> They're separate - they're part of the clk API, and the infrastructure
> behind that is clkdev, which is a separately owned thing (by me.)
>
> 2. The "contract" of the clk API is defined by the clk API, not by some
> random implementation like the common clock API. The clk API is
> maintained by myself, and is described in include/linux/clk.h
>
> 3. clk_prepare() and clk_unprepare() are functions MUST only be called
> from contexts where sleeping is permitted. These functions MAY sleep
> for whatever reason they require to, and as long as they require to.
> (This is the whole reason these two functions were created in the
> first place.)
>
> 4. clk_enable() and clk_disable() MAY be called from any context, but
> MUST never sleep. If you need to talk over a non-atomic bus for these,
> then these functions should be no-ops, and the code which does that
> must be executed from the clk_prepare()/clk_unprepare() operations.
Could the above be included in some form in Documentation/clk.txt (this
is likely one of the first location people look for information) and
elsewhere if appropriate please?
A *lot* of people are confused by the prepare-enable-disable-unprepare
sequence and when I try to find some rational for the prepare/enable
split I can only direct them to mail archive posts since this is nowhere
to be found in the kernel.
The comments in include/linux/clk.h, while correct, are very terse and
don't provide any insight to the reason why there is a split in the API.
The content of Documentation/clk.txt does refer to prepare and enable
(and their counterparts) but again doesn't provide any clue about the
reason for their existence.
Since there've been several good posts with usage example now buried
into list archives, I think this would go a long way helping people get
it right if those were part of the kernel documentation as well.
Nicolas
^ permalink raw reply [flat|nested] 432+ messages in thread
* [PATCH v2 15/24] net: can: mscan: add a comment on reg to idx mapping
2013-07-18 17:00 ` Gerhard Sittig
(?)
@ 2013-07-18 20:20 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
add a comment about the magic of deriving an MSCAN component index
from the peripheral's physical address / register offset
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index 5b0ee8e..bc422ba 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -148,7 +148,10 @@ static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
goto exit_put;
}
- /* Determine the MSCAN device index from the physical address */
+ /* Determine the MSCAN device index from the peripheral's
+ * physical address. Register address offsets against the
+ * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
+ */
pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
BUG_ON(!pval || plen < sizeof(*pval));
clockidx = (*pval & 0x80) ? 1 : 0;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 15/24] net: can: mscan: add a comment on reg to idx mapping
@ 2013-07-18 20:20 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
add a comment about the magic of deriving an MSCAN component index
from the peripheral's physical address / register offset
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index 5b0ee8e..bc422ba 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -148,7 +148,10 @@ static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
goto exit_put;
}
- /* Determine the MSCAN device index from the physical address */
+ /* Determine the MSCAN device index from the peripheral's
+ * physical address. Register address offsets against the
+ * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
+ */
pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
BUG_ON(!pval || plen < sizeof(*pval));
clockidx = (*pval & 0x80) ? 1 : 0;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 15/24] net: can: mscan: add a comment on reg to idx mapping
@ 2013-07-18 20:20 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linux-arm-kernel
add a comment about the magic of deriving an MSCAN component index
from the peripheral's physical address / register offset
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index 5b0ee8e..bc422ba 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -148,7 +148,10 @@ static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
goto exit_put;
}
- /* Determine the MSCAN device index from the physical address */
+ /* Determine the MSCAN device index from the peripheral's
+ * physical address. Register address offsets against the
+ * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
+ */
pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
BUG_ON(!pval || plen < sizeof(*pval));
clockidx = (*pval & 0x80) ? 1 : 0;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 16/24] net: can: mscan: make mpc512x code use common clock
2013-07-18 17:00 ` Gerhard Sittig
(?)
@ 2013-07-18 20:20 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
extend the mscan(4) driver with alternative support for the COMMON_CLK
approach which is an option in the MPC512x platform, keep the existing
clock support implementation in place since the driver is shared with
other MPC5xxx SoCs which don't have common clock support
one byproduct of this change is that the CAN driver no longer needs to
access the SoC's clock control registers, which shall be the domain of
the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
drivers/net/can/mscan/mpc5xxx_can.c | 139 +++++++++++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index bc422ba..dd26ab6 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -108,6 +108,143 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
#endif /* CONFIG_PPC_MPC52xx */
#ifdef CONFIG_PPC_MPC512x
+
+#if IS_ENABLED(CONFIG_COMMON_CLK)
+
+static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
+ const char *clock_source, int *mscan_clksrc)
+{
+ struct device_node *np;
+ u32 clockdiv;
+ enum {
+ CLK_FROM_AUTO,
+ CLK_FROM_IPS,
+ CLK_FROM_SYS,
+ CLK_FROM_REF,
+ } clk_from;
+ struct clk *clk_in, *clk_can;
+ unsigned long freq_calc;
+
+ /* the caller passed in the clock source spec that was read from
+ * the device tree, get the optional clock divider as well
+ */
+ np = ofdev->dev.of_node;
+ clockdiv = 1;
+ of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
+ dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
+ clock_source ? clock_source : "<NULL>", clockdiv);
+
+ /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
+ * get set, and the 'ips' clock is the input to the MSCAN
+ * component
+ *
+ * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
+ * bit needs to get cleared, an optional clock-divider may have
+ * been specified (the default value is 1), the appropriate
+ * MSCAN related MCLK is the input to the MSCAN component
+ *
+ * in the absence of a clock-source spec, first an optimal clock
+ * gets determined based on the 'sys' clock, if that fails the
+ * 'ref' clock is used
+ */
+ clk_from = CLK_FROM_AUTO;
+ if (clock_source) {
+ /* interpret the device tree's spec for the clock source */
+ if (!strcmp(clock_source, "ip"))
+ clk_from = CLK_FROM_IPS;
+ else if (!strcmp(clock_source, "sys"))
+ clk_from = CLK_FROM_SYS;
+ else if (!strcmp(clock_source, "ref"))
+ clk_from = CLK_FROM_REF;
+ else
+ goto err_invalid;
+ dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, try the 'sys' clock; round to the
+ * next MHz and see if we can get a multiple of 16MHz
+ */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc += 499999;
+ freq_calc /= 1000000;
+ freq_calc *= 1000000;
+ if ((freq_calc % 16000000) == 0) {
+ clk_from = CLK_FROM_SYS;
+ clockdiv = freq_calc / 16000000;
+ dev_dbg(&ofdev->dev,
+ "clk fit, sys[%lu] div[%d] freq[%lu]\n",
+ freq_calc, clockdiv, freq_calc / clockdiv);
+ }
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, use the 'ref' clock */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_from = CLK_FROM_REF;
+ freq_calc = clk_get_rate(clk_in);
+ dev_dbg(&ofdev->dev,
+ "clk fit, ref[%lu] (no div) freq[%lu]\n",
+ freq_calc, freq_calc);
+ }
+
+ /* select IPS or MCLK as the MSCAN input (returned to the caller),
+ * setup the MCLK mux source and rate if applicable, apply the
+ * optionally specified or derived above divider, and determine
+ * the actual resulting clock rate to return to the caller
+ */
+ switch (clk_from) {
+ case CLK_FROM_IPS:
+ clk_can = clk_get(&ofdev->dev, "ips");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_IPS;
+ dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ case CLK_FROM_SYS:
+ case CLK_FROM_REF:
+ clk_can = clk_get(&ofdev->dev, "mclk");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ if (clk_from == CLK_FROM_SYS)
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (clk_from == CLK_FROM_REF)
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_set_parent(clk_can, clk_in);
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc /= clockdiv;
+ clk_set_rate(clk_can, freq_calc);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_BUS;
+ dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ default:
+ goto err_invalid;
+ }
+
+ return freq_calc;
+
+err_invalid:
+ dev_err(&ofdev->dev, "invalid clock source specification\n");
+ return 0;
+
+err_notavail:
+ dev_err(&ofdev->dev, "cannot acquire or setup clock source\n");
+ return 0;
+}
+#else /* COMMON_CLK */
struct mpc512x_clockctl {
u32 spmr; /* System PLL Mode Reg */
u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
@@ -238,6 +375,8 @@ exit_put:
of_node_put(np_clock);
return freq;
}
+#endif /* COMMON_CLK */
+
#else /* !CONFIG_PPC_MPC512x */
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_name, int *mscan_clksrc)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 16/24] net: can: mscan: make mpc512x code use common clock
@ 2013-07-18 20:20 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
extend the mscan(4) driver with alternative support for the COMMON_CLK
approach which is an option in the MPC512x platform, keep the existing
clock support implementation in place since the driver is shared with
other MPC5xxx SoCs which don't have common clock support
one byproduct of this change is that the CAN driver no longer needs to
access the SoC's clock control registers, which shall be the domain of
the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 139 +++++++++++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index bc422ba..dd26ab6 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -108,6 +108,143 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
#endif /* CONFIG_PPC_MPC52xx */
#ifdef CONFIG_PPC_MPC512x
+
+#if IS_ENABLED(CONFIG_COMMON_CLK)
+
+static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
+ const char *clock_source, int *mscan_clksrc)
+{
+ struct device_node *np;
+ u32 clockdiv;
+ enum {
+ CLK_FROM_AUTO,
+ CLK_FROM_IPS,
+ CLK_FROM_SYS,
+ CLK_FROM_REF,
+ } clk_from;
+ struct clk *clk_in, *clk_can;
+ unsigned long freq_calc;
+
+ /* the caller passed in the clock source spec that was read from
+ * the device tree, get the optional clock divider as well
+ */
+ np = ofdev->dev.of_node;
+ clockdiv = 1;
+ of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
+ dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
+ clock_source ? clock_source : "<NULL>", clockdiv);
+
+ /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
+ * get set, and the 'ips' clock is the input to the MSCAN
+ * component
+ *
+ * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
+ * bit needs to get cleared, an optional clock-divider may have
+ * been specified (the default value is 1), the appropriate
+ * MSCAN related MCLK is the input to the MSCAN component
+ *
+ * in the absence of a clock-source spec, first an optimal clock
+ * gets determined based on the 'sys' clock, if that fails the
+ * 'ref' clock is used
+ */
+ clk_from = CLK_FROM_AUTO;
+ if (clock_source) {
+ /* interpret the device tree's spec for the clock source */
+ if (!strcmp(clock_source, "ip"))
+ clk_from = CLK_FROM_IPS;
+ else if (!strcmp(clock_source, "sys"))
+ clk_from = CLK_FROM_SYS;
+ else if (!strcmp(clock_source, "ref"))
+ clk_from = CLK_FROM_REF;
+ else
+ goto err_invalid;
+ dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, try the 'sys' clock; round to the
+ * next MHz and see if we can get a multiple of 16MHz
+ */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc += 499999;
+ freq_calc /= 1000000;
+ freq_calc *= 1000000;
+ if ((freq_calc % 16000000) == 0) {
+ clk_from = CLK_FROM_SYS;
+ clockdiv = freq_calc / 16000000;
+ dev_dbg(&ofdev->dev,
+ "clk fit, sys[%lu] div[%d] freq[%lu]\n",
+ freq_calc, clockdiv, freq_calc / clockdiv);
+ }
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, use the 'ref' clock */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_from = CLK_FROM_REF;
+ freq_calc = clk_get_rate(clk_in);
+ dev_dbg(&ofdev->dev,
+ "clk fit, ref[%lu] (no div) freq[%lu]\n",
+ freq_calc, freq_calc);
+ }
+
+ /* select IPS or MCLK as the MSCAN input (returned to the caller),
+ * setup the MCLK mux source and rate if applicable, apply the
+ * optionally specified or derived above divider, and determine
+ * the actual resulting clock rate to return to the caller
+ */
+ switch (clk_from) {
+ case CLK_FROM_IPS:
+ clk_can = clk_get(&ofdev->dev, "ips");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_IPS;
+ dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ case CLK_FROM_SYS:
+ case CLK_FROM_REF:
+ clk_can = clk_get(&ofdev->dev, "mclk");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ if (clk_from == CLK_FROM_SYS)
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (clk_from == CLK_FROM_REF)
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_set_parent(clk_can, clk_in);
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc /= clockdiv;
+ clk_set_rate(clk_can, freq_calc);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_BUS;
+ dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ default:
+ goto err_invalid;
+ }
+
+ return freq_calc;
+
+err_invalid:
+ dev_err(&ofdev->dev, "invalid clock source specification\n");
+ return 0;
+
+err_notavail:
+ dev_err(&ofdev->dev, "cannot acquire or setup clock source\n");
+ return 0;
+}
+#else /* COMMON_CLK */
struct mpc512x_clockctl {
u32 spmr; /* System PLL Mode Reg */
u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
@@ -238,6 +375,8 @@ exit_put:
of_node_put(np_clock);
return freq;
}
+#endif /* COMMON_CLK */
+
#else /* !CONFIG_PPC_MPC512x */
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_name, int *mscan_clksrc)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 16/24] net: can: mscan: make mpc512x code use common clock
@ 2013-07-18 20:20 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linux-arm-kernel
extend the mscan(4) driver with alternative support for the COMMON_CLK
approach which is an option in the MPC512x platform, keep the existing
clock support implementation in place since the driver is shared with
other MPC5xxx SoCs which don't have common clock support
one byproduct of this change is that the CAN driver no longer needs to
access the SoC's clock control registers, which shall be the domain of
the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
drivers/net/can/mscan/mpc5xxx_can.c | 139 +++++++++++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index bc422ba..dd26ab6 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -108,6 +108,143 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
#endif /* CONFIG_PPC_MPC52xx */
#ifdef CONFIG_PPC_MPC512x
+
+#if IS_ENABLED(CONFIG_COMMON_CLK)
+
+static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
+ const char *clock_source, int *mscan_clksrc)
+{
+ struct device_node *np;
+ u32 clockdiv;
+ enum {
+ CLK_FROM_AUTO,
+ CLK_FROM_IPS,
+ CLK_FROM_SYS,
+ CLK_FROM_REF,
+ } clk_from;
+ struct clk *clk_in, *clk_can;
+ unsigned long freq_calc;
+
+ /* the caller passed in the clock source spec that was read from
+ * the device tree, get the optional clock divider as well
+ */
+ np = ofdev->dev.of_node;
+ clockdiv = 1;
+ of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
+ dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
+ clock_source ? clock_source : "<NULL>", clockdiv);
+
+ /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
+ * get set, and the 'ips' clock is the input to the MSCAN
+ * component
+ *
+ * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
+ * bit needs to get cleared, an optional clock-divider may have
+ * been specified (the default value is 1), the appropriate
+ * MSCAN related MCLK is the input to the MSCAN component
+ *
+ * in the absence of a clock-source spec, first an optimal clock
+ * gets determined based on the 'sys' clock, if that fails the
+ * 'ref' clock is used
+ */
+ clk_from = CLK_FROM_AUTO;
+ if (clock_source) {
+ /* interpret the device tree's spec for the clock source */
+ if (!strcmp(clock_source, "ip"))
+ clk_from = CLK_FROM_IPS;
+ else if (!strcmp(clock_source, "sys"))
+ clk_from = CLK_FROM_SYS;
+ else if (!strcmp(clock_source, "ref"))
+ clk_from = CLK_FROM_REF;
+ else
+ goto err_invalid;
+ dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, try the 'sys' clock; round to the
+ * next MHz and see if we can get a multiple of 16MHz
+ */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc += 499999;
+ freq_calc /= 1000000;
+ freq_calc *= 1000000;
+ if ((freq_calc % 16000000) == 0) {
+ clk_from = CLK_FROM_SYS;
+ clockdiv = freq_calc / 16000000;
+ dev_dbg(&ofdev->dev,
+ "clk fit, sys[%lu] div[%d] freq[%lu]\n",
+ freq_calc, clockdiv, freq_calc / clockdiv);
+ }
+ }
+ if (clk_from == CLK_FROM_AUTO) {
+ /* no spec so far, use the 'ref' clock */
+ dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_from = CLK_FROM_REF;
+ freq_calc = clk_get_rate(clk_in);
+ dev_dbg(&ofdev->dev,
+ "clk fit, ref[%lu] (no div) freq[%lu]\n",
+ freq_calc, freq_calc);
+ }
+
+ /* select IPS or MCLK as the MSCAN input (returned to the caller),
+ * setup the MCLK mux source and rate if applicable, apply the
+ * optionally specified or derived above divider, and determine
+ * the actual resulting clock rate to return to the caller
+ */
+ switch (clk_from) {
+ case CLK_FROM_IPS:
+ clk_can = clk_get(&ofdev->dev, "ips");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_IPS;
+ dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ case CLK_FROM_SYS:
+ case CLK_FROM_REF:
+ clk_can = clk_get(&ofdev->dev, "mclk");
+ if (IS_ERR(clk_can))
+ goto err_notavail;
+ clk_prepare_enable(clk_can);
+ if (clk_from == CLK_FROM_SYS)
+ clk_in = clk_get(&ofdev->dev, "sys");
+ if (clk_from == CLK_FROM_REF)
+ clk_in = clk_get(&ofdev->dev, "ref");
+ if (IS_ERR(clk_in))
+ goto err_notavail;
+ clk_set_parent(clk_can, clk_in);
+ freq_calc = clk_get_rate(clk_in);
+ freq_calc /= clockdiv;
+ clk_set_rate(clk_can, freq_calc);
+ freq_calc = clk_get_rate(clk_can);
+ *mscan_clksrc = MSCAN_CLKSRC_BUS;
+ dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
+ *mscan_clksrc, freq_calc);
+ break;
+ default:
+ goto err_invalid;
+ }
+
+ return freq_calc;
+
+err_invalid:
+ dev_err(&ofdev->dev, "invalid clock source specification\n");
+ return 0;
+
+err_notavail:
+ dev_err(&ofdev->dev, "cannot acquire or setup clock source\n");
+ return 0;
+}
+#else /* COMMON_CLK */
struct mpc512x_clockctl {
u32 spmr; /* System PLL Mode Reg */
u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
@@ -238,6 +375,8 @@ exit_put:
of_node_put(np_clock);
return freq;
}
+#endif /* COMMON_CLK */
+
#else /* !CONFIG_PPC_MPC512x */
static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
const char *clock_name, int *mscan_clksrc)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 17/24] powerpc/mpc512x: improve DIU related clock setup
2013-07-18 17:00 ` Gerhard Sittig
(?)
@ 2013-07-18 20:20 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Anatolij Gustschin,
Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Rob Herring,
Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
adapt the DIU clock initialization to the COMMON_CLK approach: device
tree based clock lookup, prepare and unprepare for clocks, work with
frequencies not dividers, call the appropriate clk_*() routines and
don't access CCM registers, remove the pre-enable workaround in the
platform's clock driver
the "best clock" determination now completely relies on the platform's
clock driver to pick a frequency close to what the caller requests, and
merely checks whether the desired frequency was met (is acceptable since
it meets the tolerance of the monitor) -- this approach shall succeed
upon first try in the usual case, will test a few less desirable yet
acceptable frequencies in edge cases, and will fallback to "best effort"
if none of the previously tried frequencies pass the test
Signed-off-by: Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++++++++++++------------
2 files changed, 88 insertions(+), 78 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 99d197d..b8963b7 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -692,7 +692,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index a82a41b..3381eea 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -12,6 +12,7 @@
* (at your option) any later version.
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/irq.h>
@@ -70,98 +71,108 @@ struct fsl_diu_shared_fb {
bool in_use;
};
-#define DIU_DIV_MASK 0x000000ff
+/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
void mpc512x_set_pixel_clock(unsigned int pixclock)
{
- unsigned long bestval, bestfreq, speed, busfreq;
- unsigned long minpixclock, maxpixclock, pixval;
- struct mpc512x_ccm __iomem *ccm;
struct device_node *np;
- u32 temp;
- long err;
- int i;
+ struct clk *clk_diu;
+ unsigned long epsilon, minpixclock, maxpixclock;
+ unsigned long offset, want, got, delta;
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ /* lookup and enable the DIU clock */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
if (!np) {
- pr_err("Can't find clock control module.\n");
+ pr_err("Could not find DIU device tree node.\n");
return;
}
-
- ccm = of_iomap(np, 0);
+ clk_diu = of_clk_get_by_name(np, "per");
of_node_put(np);
- if (!ccm) {
- pr_err("Can't map clock control module reg.\n");
+ if (IS_ERR(clk_diu)) {
+ pr_err("Could not lookup DIU clock.\n");
return;
}
-
- np = of_find_node_by_type(NULL, "cpu");
- if (np) {
- const unsigned int *prop =
- of_get_property(np, "bus-frequency", NULL);
-
- of_node_put(np);
- if (prop) {
- busfreq = *prop;
- } else {
- pr_err("Can't get bus-frequency property\n");
- return;
- }
- } else {
- pr_err("Can't find 'cpu' node.\n");
+ if (clk_prepare_enable(clk_diu)) {
+ pr_err("Could not enable DIU clock.\n");
return;
}
- /* Pixel Clock configuration */
- pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
- speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
-
- /* Calculate the pixel clock with the smallest error */
- /* calculate the following in steps to avoid overflow */
- pr_debug("DIU pixclock in ps - %d\n", pixclock);
- temp = (1000000000 / pixclock) * 1000;
- pixclock = temp;
- pr_debug("DIU pixclock freq - %u\n", pixclock);
-
- temp = temp / 20; /* pixclock * 0.05 */
- pr_debug("deviation = %d\n", temp);
- minpixclock = pixclock - temp;
- maxpixclock = pixclock + temp;
- pr_debug("DIU minpixclock - %lu\n", minpixclock);
- pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
- pixval = speed/pixclock;
- pr_debug("DIU pixval = %lu\n", pixval);
-
- err = LONG_MAX;
- bestval = pixval;
- pr_debug("DIU bestval = %lu\n", bestval);
-
- bestfreq = 0;
- for (i = -1; i <= 1; i++) {
- temp = speed / (pixval+i);
- pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
- i, pixval, temp);
- if ((temp < minpixclock) || (temp > maxpixclock))
- pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
- minpixclock, maxpixclock);
- else if (abs(temp - pixclock) < err) {
- pr_debug("Entered the else if block %d\n", i);
- err = abs(temp - pixclock);
- bestval = pixval + i;
- bestfreq = temp;
- }
+ /*
+ * convert the picoseconds spec into the desired clock rate,
+ * determine the acceptable clock range for the monitor (+/- 5%),
+ * do the calculation in steps to avoid integer overflow
+ */
+ pr_debug("DIU pixclock in ps - %u\n", pixclock);
+ pixclock = (1000000000 / pixclock) * 1000;
+ pr_debug("DIU pixclock freq - %u\n", pixclock);
+ epsilon = pixclock / 20; /* pixclock * 0.05 */
+ pr_debug("DIU deviation - %lu\n", epsilon);
+ minpixclock = pixclock - epsilon;
+ maxpixclock = pixclock + epsilon;
+ pr_debug("DIU minpixclock - %lu\n", minpixclock);
+ pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+
+ /*
+ * check whether the DIU supports the desired pixel clock
+ *
+ * - simply request the desired clock and see what the
+ * platform's clock driver will make of it, assuming that it
+ * will setup the best approximation of the requested value
+ * - try other candidate frequencies in the order of decreasing
+ * preference (i.e. with increasing distance from the desired
+ * pixel clock, and checking the lower frequency before the
+ * higher frequency to not overload the hardware) until the
+ * first match is found -- any potential subsequent match
+ * would only be as good as the former match or typically
+ * would be less preferrable
+ *
+ * the offset increment of pixelclock divided by 64 is an
+ * arbitrary choice -- it's simple to calculate, in the typical
+ * case we expect the first check to succeed already, in the
+ * worst case seven frequencies get tested (the exact center and
+ * three more values each to the left and to the right) before
+ * the 5% tolerance window is exceeded, resulting in fast enough
+ * execution yet high enough probability of finding a suitable
+ * value, while the error rate will be in the order of single
+ * percents
+ */
+ for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
+ want = pixclock - offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
+ if (!offset)
+ continue;
+ want = pixclock + offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
}
+ if (offset <= epsilon) {
+ pr_debug("DIU clock accepted - %lu\n", want);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
+ return;
+ }
+ pr_warn("DIU pixclock auto search unsuccessful\n");
- pr_debug("DIU chose = %lx\n", bestval);
- pr_debug("DIU error = %ld\n NomPixClk ", err);
- pr_debug("DIU: Best Freq = %lx\n", bestfreq);
- /* Modify DIU_DIV in CCM SCFR1 */
- temp = in_be32(&ccm->scfr1);
- pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
- temp &= ~DIU_DIV_MASK;
- temp |= (bestval & DIU_DIV_MASK);
- out_be32(&ccm->scfr1, temp);
- pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
- iounmap(ccm);
+ /*
+ * what is the most appropriate action to take when the search
+ * for an available pixel clock which is acceptable to the
+ * monitor has failed? disable the DIU (clock) or just provide
+ * a "best effort"? we go with the latter
+ */
+ pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
+ clk_set_rate(clk_diu, pixclock);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
}
enum fsl_diu_monitor_port
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 17/24] powerpc/mpc512x: improve DIU related clock setup
@ 2013-07-18 20:20 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
adapt the DIU clock initialization to the COMMON_CLK approach: device
tree based clock lookup, prepare and unprepare for clocks, work with
frequencies not dividers, call the appropriate clk_*() routines and
don't access CCM registers, remove the pre-enable workaround in the
platform's clock driver
the "best clock" determination now completely relies on the platform's
clock driver to pick a frequency close to what the caller requests, and
merely checks whether the desired frequency was met (is acceptable since
it meets the tolerance of the monitor) -- this approach shall succeed
upon first try in the usual case, will test a few less desirable yet
acceptable frequencies in edge cases, and will fallback to "best effort"
if none of the previously tried frequencies pass the test
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++++++++++++------------
2 files changed, 88 insertions(+), 78 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 99d197d..b8963b7 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -692,7 +692,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index a82a41b..3381eea 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -12,6 +12,7 @@
* (at your option) any later version.
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/irq.h>
@@ -70,98 +71,108 @@ struct fsl_diu_shared_fb {
bool in_use;
};
-#define DIU_DIV_MASK 0x000000ff
+/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
void mpc512x_set_pixel_clock(unsigned int pixclock)
{
- unsigned long bestval, bestfreq, speed, busfreq;
- unsigned long minpixclock, maxpixclock, pixval;
- struct mpc512x_ccm __iomem *ccm;
struct device_node *np;
- u32 temp;
- long err;
- int i;
+ struct clk *clk_diu;
+ unsigned long epsilon, minpixclock, maxpixclock;
+ unsigned long offset, want, got, delta;
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ /* lookup and enable the DIU clock */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
if (!np) {
- pr_err("Can't find clock control module.\n");
+ pr_err("Could not find DIU device tree node.\n");
return;
}
-
- ccm = of_iomap(np, 0);
+ clk_diu = of_clk_get_by_name(np, "per");
of_node_put(np);
- if (!ccm) {
- pr_err("Can't map clock control module reg.\n");
+ if (IS_ERR(clk_diu)) {
+ pr_err("Could not lookup DIU clock.\n");
return;
}
-
- np = of_find_node_by_type(NULL, "cpu");
- if (np) {
- const unsigned int *prop =
- of_get_property(np, "bus-frequency", NULL);
-
- of_node_put(np);
- if (prop) {
- busfreq = *prop;
- } else {
- pr_err("Can't get bus-frequency property\n");
- return;
- }
- } else {
- pr_err("Can't find 'cpu' node.\n");
+ if (clk_prepare_enable(clk_diu)) {
+ pr_err("Could not enable DIU clock.\n");
return;
}
- /* Pixel Clock configuration */
- pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
- speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
-
- /* Calculate the pixel clock with the smallest error */
- /* calculate the following in steps to avoid overflow */
- pr_debug("DIU pixclock in ps - %d\n", pixclock);
- temp = (1000000000 / pixclock) * 1000;
- pixclock = temp;
- pr_debug("DIU pixclock freq - %u\n", pixclock);
-
- temp = temp / 20; /* pixclock * 0.05 */
- pr_debug("deviation = %d\n", temp);
- minpixclock = pixclock - temp;
- maxpixclock = pixclock + temp;
- pr_debug("DIU minpixclock - %lu\n", minpixclock);
- pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
- pixval = speed/pixclock;
- pr_debug("DIU pixval = %lu\n", pixval);
-
- err = LONG_MAX;
- bestval = pixval;
- pr_debug("DIU bestval = %lu\n", bestval);
-
- bestfreq = 0;
- for (i = -1; i <= 1; i++) {
- temp = speed / (pixval+i);
- pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
- i, pixval, temp);
- if ((temp < minpixclock) || (temp > maxpixclock))
- pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
- minpixclock, maxpixclock);
- else if (abs(temp - pixclock) < err) {
- pr_debug("Entered the else if block %d\n", i);
- err = abs(temp - pixclock);
- bestval = pixval + i;
- bestfreq = temp;
- }
+ /*
+ * convert the picoseconds spec into the desired clock rate,
+ * determine the acceptable clock range for the monitor (+/- 5%),
+ * do the calculation in steps to avoid integer overflow
+ */
+ pr_debug("DIU pixclock in ps - %u\n", pixclock);
+ pixclock = (1000000000 / pixclock) * 1000;
+ pr_debug("DIU pixclock freq - %u\n", pixclock);
+ epsilon = pixclock / 20; /* pixclock * 0.05 */
+ pr_debug("DIU deviation - %lu\n", epsilon);
+ minpixclock = pixclock - epsilon;
+ maxpixclock = pixclock + epsilon;
+ pr_debug("DIU minpixclock - %lu\n", minpixclock);
+ pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+
+ /*
+ * check whether the DIU supports the desired pixel clock
+ *
+ * - simply request the desired clock and see what the
+ * platform's clock driver will make of it, assuming that it
+ * will setup the best approximation of the requested value
+ * - try other candidate frequencies in the order of decreasing
+ * preference (i.e. with increasing distance from the desired
+ * pixel clock, and checking the lower frequency before the
+ * higher frequency to not overload the hardware) until the
+ * first match is found -- any potential subsequent match
+ * would only be as good as the former match or typically
+ * would be less preferrable
+ *
+ * the offset increment of pixelclock divided by 64 is an
+ * arbitrary choice -- it's simple to calculate, in the typical
+ * case we expect the first check to succeed already, in the
+ * worst case seven frequencies get tested (the exact center and
+ * three more values each to the left and to the right) before
+ * the 5% tolerance window is exceeded, resulting in fast enough
+ * execution yet high enough probability of finding a suitable
+ * value, while the error rate will be in the order of single
+ * percents
+ */
+ for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
+ want = pixclock - offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
+ if (!offset)
+ continue;
+ want = pixclock + offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
}
+ if (offset <= epsilon) {
+ pr_debug("DIU clock accepted - %lu\n", want);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
+ return;
+ }
+ pr_warn("DIU pixclock auto search unsuccessful\n");
- pr_debug("DIU chose = %lx\n", bestval);
- pr_debug("DIU error = %ld\n NomPixClk ", err);
- pr_debug("DIU: Best Freq = %lx\n", bestfreq);
- /* Modify DIU_DIV in CCM SCFR1 */
- temp = in_be32(&ccm->scfr1);
- pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
- temp &= ~DIU_DIV_MASK;
- temp |= (bestval & DIU_DIV_MASK);
- out_be32(&ccm->scfr1, temp);
- pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
- iounmap(ccm);
+ /*
+ * what is the most appropriate action to take when the search
+ * for an available pixel clock which is acceptable to the
+ * monitor has failed? disable the DIU (clock) or just provide
+ * a "best effort"? we go with the latter
+ */
+ pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
+ clk_set_rate(clk_diu, pixclock);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
}
enum fsl_diu_monitor_port
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 17/24] powerpc/mpc512x: improve DIU related clock setup
@ 2013-07-18 20:20 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linux-arm-kernel
adapt the DIU clock initialization to the COMMON_CLK approach: device
tree based clock lookup, prepare and unprepare for clocks, work with
frequencies not dividers, call the appropriate clk_*() routines and
don't access CCM registers, remove the pre-enable workaround in the
platform's clock driver
the "best clock" determination now completely relies on the platform's
clock driver to pick a frequency close to what the caller requests, and
merely checks whether the desired frequency was met (is acceptable since
it meets the tolerance of the monitor) -- this approach shall succeed
upon first try in the usual case, will test a few less desirable yet
acceptable frequencies in edge cases, and will fallback to "best effort"
if none of the previously tried frequencies pass the test
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
arch/powerpc/platforms/512x/mpc512x_shared.c | 165 +++++++++++++------------
2 files changed, 88 insertions(+), 78 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 99d197d..b8963b7 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -692,7 +692,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_DIU]); /* display */
clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index a82a41b..3381eea 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -12,6 +12,7 @@
* (at your option) any later version.
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/irq.h>
@@ -70,98 +71,108 @@ struct fsl_diu_shared_fb {
bool in_use;
};
-#define DIU_DIV_MASK 0x000000ff
+/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
void mpc512x_set_pixel_clock(unsigned int pixclock)
{
- unsigned long bestval, bestfreq, speed, busfreq;
- unsigned long minpixclock, maxpixclock, pixval;
- struct mpc512x_ccm __iomem *ccm;
struct device_node *np;
- u32 temp;
- long err;
- int i;
+ struct clk *clk_diu;
+ unsigned long epsilon, minpixclock, maxpixclock;
+ unsigned long offset, want, got, delta;
- np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+ /* lookup and enable the DIU clock */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
if (!np) {
- pr_err("Can't find clock control module.\n");
+ pr_err("Could not find DIU device tree node.\n");
return;
}
-
- ccm = of_iomap(np, 0);
+ clk_diu = of_clk_get_by_name(np, "per");
of_node_put(np);
- if (!ccm) {
- pr_err("Can't map clock control module reg.\n");
+ if (IS_ERR(clk_diu)) {
+ pr_err("Could not lookup DIU clock.\n");
return;
}
-
- np = of_find_node_by_type(NULL, "cpu");
- if (np) {
- const unsigned int *prop =
- of_get_property(np, "bus-frequency", NULL);
-
- of_node_put(np);
- if (prop) {
- busfreq = *prop;
- } else {
- pr_err("Can't get bus-frequency property\n");
- return;
- }
- } else {
- pr_err("Can't find 'cpu' node.\n");
+ if (clk_prepare_enable(clk_diu)) {
+ pr_err("Could not enable DIU clock.\n");
return;
}
- /* Pixel Clock configuration */
- pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
- speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
-
- /* Calculate the pixel clock with the smallest error */
- /* calculate the following in steps to avoid overflow */
- pr_debug("DIU pixclock in ps - %d\n", pixclock);
- temp = (1000000000 / pixclock) * 1000;
- pixclock = temp;
- pr_debug("DIU pixclock freq - %u\n", pixclock);
-
- temp = temp / 20; /* pixclock * 0.05 */
- pr_debug("deviation = %d\n", temp);
- minpixclock = pixclock - temp;
- maxpixclock = pixclock + temp;
- pr_debug("DIU minpixclock - %lu\n", minpixclock);
- pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
- pixval = speed/pixclock;
- pr_debug("DIU pixval = %lu\n", pixval);
-
- err = LONG_MAX;
- bestval = pixval;
- pr_debug("DIU bestval = %lu\n", bestval);
-
- bestfreq = 0;
- for (i = -1; i <= 1; i++) {
- temp = speed / (pixval+i);
- pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
- i, pixval, temp);
- if ((temp < minpixclock) || (temp > maxpixclock))
- pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
- minpixclock, maxpixclock);
- else if (abs(temp - pixclock) < err) {
- pr_debug("Entered the else if block %d\n", i);
- err = abs(temp - pixclock);
- bestval = pixval + i;
- bestfreq = temp;
- }
+ /*
+ * convert the picoseconds spec into the desired clock rate,
+ * determine the acceptable clock range for the monitor (+/- 5%),
+ * do the calculation in steps to avoid integer overflow
+ */
+ pr_debug("DIU pixclock in ps - %u\n", pixclock);
+ pixclock = (1000000000 / pixclock) * 1000;
+ pr_debug("DIU pixclock freq - %u\n", pixclock);
+ epsilon = pixclock / 20; /* pixclock * 0.05 */
+ pr_debug("DIU deviation - %lu\n", epsilon);
+ minpixclock = pixclock - epsilon;
+ maxpixclock = pixclock + epsilon;
+ pr_debug("DIU minpixclock - %lu\n", minpixclock);
+ pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+
+ /*
+ * check whether the DIU supports the desired pixel clock
+ *
+ * - simply request the desired clock and see what the
+ * platform's clock driver will make of it, assuming that it
+ * will setup the best approximation of the requested value
+ * - try other candidate frequencies in the order of decreasing
+ * preference (i.e. with increasing distance from the desired
+ * pixel clock, and checking the lower frequency before the
+ * higher frequency to not overload the hardware) until the
+ * first match is found -- any potential subsequent match
+ * would only be as good as the former match or typically
+ * would be less preferrable
+ *
+ * the offset increment of pixelclock divided by 64 is an
+ * arbitrary choice -- it's simple to calculate, in the typical
+ * case we expect the first check to succeed already, in the
+ * worst case seven frequencies get tested (the exact center and
+ * three more values each to the left and to the right) before
+ * the 5% tolerance window is exceeded, resulting in fast enough
+ * execution yet high enough probability of finding a suitable
+ * value, while the error rate will be in the order of single
+ * percents
+ */
+ for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
+ want = pixclock - offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
+ if (!offset)
+ continue;
+ want = pixclock + offset;
+ pr_debug("DIU checking clock - %lu\n", want);
+ clk_set_rate(clk_diu, want);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ if (delta < epsilon)
+ break;
}
+ if (offset <= epsilon) {
+ pr_debug("DIU clock accepted - %lu\n", want);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
+ return;
+ }
+ pr_warn("DIU pixclock auto search unsuccessful\n");
- pr_debug("DIU chose = %lx\n", bestval);
- pr_debug("DIU error = %ld\n NomPixClk ", err);
- pr_debug("DIU: Best Freq = %lx\n", bestfreq);
- /* Modify DIU_DIV in CCM SCFR1 */
- temp = in_be32(&ccm->scfr1);
- pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
- temp &= ~DIU_DIV_MASK;
- temp |= (bestval & DIU_DIV_MASK);
- out_be32(&ccm->scfr1, temp);
- pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
- iounmap(ccm);
+ /*
+ * what is the most appropriate action to take when the search
+ * for an available pixel clock which is acceptable to the
+ * monitor has failed? disable the DIU (clock) or just provide
+ * a "best effort"? we go with the latter
+ */
+ pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
+ clk_set_rate(clk_diu, pixclock);
+ got = clk_get_rate(clk_diu);
+ delta = abs(pixclock - got);
+ pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+ pixclock, got, delta, epsilon);
}
enum fsl_diu_monitor_port
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 18/24] i2c: mpc: OF clock lookup for MPC512x
2013-07-18 17:00 ` Gerhard Sittig
(?)
@ 2013-07-18 20:20 ` Gerhard Sittig
-1 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, Pantelis Antoniou,
David Woodhouse, Wolfgang Grandegger, Mauro Carvalho Chehab
make the MPC I2C driver prepare and enable the peripheral clock
('per' for register access) in the MPC512x setup routine,
make this clock setup non-fatal to allow for a migration period,
remove the pre-enabling hack in the platform's clock driver
Signed-off-by: Gerhard Sittig <gsi@denx.de>
---
arch/powerpc/platforms/512x/clock-commonclk.c | 1 -
drivers/i2c/busses/i2c-mpc.c | 9 +++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index b8963b7..49c52bc 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -692,7 +692,6 @@ static void mpc512x_clk_setup_clock_tree(int busfreq)
/* some are not yet acquired by their respective drivers */
clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
clk_prepare_enable(clks[MPC512x_CLK_FEC]); /* network, NFS */
- clk_prepare_enable(clks[MPC512x_CLK_I2C]);
/*
* some have their individual clock subtree with separate clock
* items and their individual enable counters, yet share a
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 7607dc0..13d6822 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -21,6 +21,7 @@
#include <linux/of_i2c.h>
#include <linux/slab.h>
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/i2c.h>
@@ -264,11 +265,19 @@ static void mpc_i2c_setup_512x(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler)
{
+ struct clk *clk;
struct device_node *node_ctrl;
void __iomem *ctrl;
const u32 *pval;
u32 idx;
+ /* enable clock for the I2C peripheral (non fatal) */
+ clk = of_clk_get_by_name(node, "per");
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
+
/* Enable I2C interrupts for mpc5121 */
node_ctrl = of_find_compatible_node(NULL, NULL,
"fsl,mpc5121-i2c-ctrl");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 432+ messages in thread
* [PATCH v2 18/24] i2c: mpc: OF clock lookup for MPC512x
@ 2013-07-18 20:20 ` Gerhard Sittig
0 siblings, 0 replies; 432+ messages in thread
From: Gerhard Sittig @ 2013-07-18 20:20 UTC (permalink / raw)
To: linuxppc-dev, Anatolij Gustschin, Mike Turquette,
linux-arm-kernel, devicetree-discuss
Cc: Detlev Zundel, Wolfram Sang, Greg Kroah-Hartman, Gerhard Sittig,
Rob Herring, Mark Brown, Marc Kleine-Budde, David Woodhouse,
Wolfgang Grandegger, Mauro Carvalho Chehab
make the MPC I2C driver prepare and enable the peripheral clock
('per' for register access) in the MPC512x setup routine,
make this clock setup non-fatal to allow for a migration period,
remove the pre-enabling hack in the platform's clock drive