On Thu, Jul 25, 2013 at 05:32:12PM +0800, Barry Song wrote:
> 2013/7/20 Mark Brown <broonie@kernel.org>:

> > Also what exactly is the rate being set - can the driver just figure
> > this out automatically from the sample rate?

> here it is generating the right pcm clock by an internal DIVISOR in USP module.

> For USP_MODE2:
> 30:21 (R/W) USP_CLK_DIVISOR 10’h0 USP serial clock divider

> For USP_TX_FRAME_CTRL:
> 31:30 (R/W) USP_CLK_DIVISOR 2’h0 This is the two bit [11:10] of
> USP_CLK_DIVISOR in USP_MODE2

> for figuring this out automatically from the sample rate, do you mean
> a lookup table for common sample rate?

That or just calculating it - if you know the input rate and know the
output rate you need then for a simple divisor it should be possible to
calculate the required value.