From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755568Ab3HLWNH (ORCPT ); Mon, 12 Aug 2013 18:13:07 -0400 Received: from caramon.arm.linux.org.uk ([78.32.30.218]:41278 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751797Ab3HLWNE (ORCPT ); Mon, 12 Aug 2013 18:13:04 -0400 Date: Mon, 12 Aug 2013 23:12:50 +0100 From: Russell King - ARM Linux To: Peter Maydell Cc: Guenter Roeck , Paul Gortmaker , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , qemu-devel@nongnu.org, Arnd Bergmann Subject: Re: [Qemu-devel] SCSI bus failures with qemu-arm in kernel 3.8+ Message-ID: <20130812221250.GI23006@n2100.arm.linux.org.uk> References: <5207B3C3.9080508@roeck-us.net> <20130811220450.GY23006@n2100.arm.linux.org.uk> <52082EF8.10005@roeck-us.net> <20130812164548.GE23006@n2100.arm.linux.org.uk> <20130812200628.GG23006@n2100.arm.linux.org.uk> <20130812212149.GH23006@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 12, 2013 at 10:36:17PM +0100, Peter Maydell wrote: > On this point, yes. Equivalent bit from the PB926 TRM: > http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Cacdijji.html > > (There are differences between the PCI controllers on > the different boards. Differences I know of are: > * size of the three memory mapped regions > * whether the top bits of the PCI address come from the top > or bottom of the IMAP* registers > I believe (based on some experimentation and an educated guess) > that these both changed at the same point, but some of the board > TRMs claim to be part one way part the other, presumably due to > copy and paste error. In particular PB1176's TRM has a mangled > description of the IMAP* registers which didn't match what the > h/w actually did in my testing.) Bah, updated TRMs since my version. Right, so if I've traced everything correctly, this should work: /* * Slot INTA INTB INTC INTD * 31 PCI1 PCI2 PCI3 PCI0 * 30 PCI0 PCI1 PCI2 PCI3 * 29 PCI3 PCI0 PCI1 PCI2 */ return IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3); From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41455) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V90Mw-0004PZ-Re for qemu-devel@nongnu.org; Mon, 12 Aug 2013 18:13:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V90Ms-0005FT-JT for qemu-devel@nongnu.org; Mon, 12 Aug 2013 18:13:42 -0400 Received: from caramon.arm.linux.org.uk ([2002:4e20:1eda::1]:46947) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V90Ms-0005FH-6I for qemu-devel@nongnu.org; Mon, 12 Aug 2013 18:13:38 -0400 Date: Mon, 12 Aug 2013 23:12:50 +0100 From: Russell King - ARM Linux Message-ID: <20130812221250.GI23006@n2100.arm.linux.org.uk> References: <5207B3C3.9080508@roeck-us.net> <20130811220450.GY23006@n2100.arm.linux.org.uk> <52082EF8.10005@roeck-us.net> <20130812164548.GE23006@n2100.arm.linux.org.uk> <20130812200628.GG23006@n2100.arm.linux.org.uk> <20130812212149.GH23006@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: Russell King - ARM Linux Subject: Re: [Qemu-devel] SCSI bus failures with qemu-arm in kernel 3.8+ List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "linux-kernel@vger.kernel.org" , qemu-devel@nongnu.org, Paul Gortmaker , Guenter Roeck , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" On Mon, Aug 12, 2013 at 10:36:17PM +0100, Peter Maydell wrote: > On this point, yes. Equivalent bit from the PB926 TRM: > http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Cacdijji.html > > (There are differences between the PCI controllers on > the different boards. Differences I know of are: > * size of the three memory mapped regions > * whether the top bits of the PCI address come from the top > or bottom of the IMAP* registers > I believe (based on some experimentation and an educated guess) > that these both changed at the same point, but some of the board > TRMs claim to be part one way part the other, presumably due to > copy and paste error. In particular PB1176's TRM has a mangled > description of the IMAP* registers which didn't match what the > h/w actually did in my testing.) Bah, updated TRMs since my version. Right, so if I've traced everything correctly, this should work: /* * Slot INTA INTB INTC INTD * 31 PCI1 PCI2 PCI3 PCI0 * 30 PCI0 PCI1 PCI2 PCI3 * 29 PCI3 PCI0 PCI1 PCI2 */ return IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3); From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Mon, 12 Aug 2013 23:12:50 +0100 Subject: [Qemu-devel] SCSI bus failures with qemu-arm in kernel 3.8+ In-Reply-To: References: <5207B3C3.9080508@roeck-us.net> <20130811220450.GY23006@n2100.arm.linux.org.uk> <52082EF8.10005@roeck-us.net> <20130812164548.GE23006@n2100.arm.linux.org.uk> <20130812200628.GG23006@n2100.arm.linux.org.uk> <20130812212149.GH23006@n2100.arm.linux.org.uk> Message-ID: <20130812221250.GI23006@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Aug 12, 2013 at 10:36:17PM +0100, Peter Maydell wrote: > On this point, yes. Equivalent bit from the PB926 TRM: > http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Cacdijji.html > > (There are differences between the PCI controllers on > the different boards. Differences I know of are: > * size of the three memory mapped regions > * whether the top bits of the PCI address come from the top > or bottom of the IMAP* registers > I believe (based on some experimentation and an educated guess) > that these both changed at the same point, but some of the board > TRMs claim to be part one way part the other, presumably due to > copy and paste error. In particular PB1176's TRM has a mangled > description of the IMAP* registers which didn't match what the > h/w actually did in my testing.) Bah, updated TRMs since my version. Right, so if I've traced everything correctly, this should work: /* * Slot INTA INTB INTC INTD * 31 PCI1 PCI2 PCI3 PCI0 * 30 PCI0 PCI1 PCI2 PCI3 * 29 PCI3 PCI0 PCI1 PCI2 */ return IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3);