From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 6/9] drm/i915: don't disable/reenable IVB error interrupts when not needed Date: Tue, 20 Aug 2013 16:21:34 +0200 Message-ID: <20130820142134.GT776@phenom.ffwll.local> References: <1375826239-3060-1-git-send-email-przanoni@gmail.com> <1375826239-3060-7-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f176.google.com (mail-ea0-f176.google.com [209.85.215.176]) by gabe.freedesktop.org (Postfix) with ESMTP id DC426E70F2 for ; Tue, 20 Aug 2013 07:21:23 -0700 (PDT) Received: by mail-ea0-f176.google.com with SMTP id q16so253539ead.35 for ; Tue, 20 Aug 2013 07:21:23 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1375826239-3060-7-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Tue, Aug 06, 2013 at 06:57:16PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > If the error interrupts are already disabled, don't disable and > reenable them. This is going to be needed when we're in PC8+, where > all the interrupts are disabled so we won't risk re-enabling > DE_ERR_INT_IVB. > > v2: Use dev_priv->irq_mask (Chris) > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_irq.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index d96bd1b..5e7e6f6 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1373,6 +1373,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) > drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; > u32 de_iir, gt_iir, de_ier, sde_ier = 0; > irqreturn_t ret = IRQ_NONE; > + bool err_int_reenable = false; > > atomic_inc(&dev_priv->irq_received); > > @@ -1401,7 +1402,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) > * handler. */ > if (IS_HASWELL(dev)) { > spin_lock(&dev_priv->irq_lock); > - ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); > + err_int_reenable = ~dev_priv->irq_mask & DE_ERR_INT_IVB; > + if (err_int_reenable) > + ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); Hm, that reminds me that this entire logic here is racy wrt concurrent interrupt enabling on a different cpu core (e.g. due to a modeset now again allowing display error interrupts). Do we still need this or could we just ditch this entire complexity? Maybe I'm just engaging in wishful thinking here a bit ;-) Patch applied. -Daniel > spin_unlock(&dev_priv->irq_lock); > } > > @@ -1437,7 +1440,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) > } > } > > - if (IS_HASWELL(dev)) { > + if (err_int_reenable) { > spin_lock(&dev_priv->irq_lock); > if (ivb_can_enable_err_int(dev)) > ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); > -- > 1.8.1.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch