From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34069) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeBWe-0004oK-Dw for qemu-devel@nongnu.org; Wed, 06 Nov 2013 17:24:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeBWY-0001vA-ES for qemu-devel@nongnu.org; Wed, 06 Nov 2013 17:24:36 -0500 Received: from mx1.redhat.com ([209.132.183.28]:49891) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeBWY-0001v6-6H for qemu-devel@nongnu.org; Wed, 06 Nov 2013 17:24:30 -0500 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id rA6MOT4S019548 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Wed, 6 Nov 2013 17:24:29 -0500 Date: Wed, 6 Nov 2013 20:24:15 -0200 From: Marcelo Tosatti Message-ID: <20131106222415.GA18205@amt.cnet> References: <20131024211158.064049176@amt.cnet> <20131024211249.723543071@amt.cnet> <20131106014930.GA20468@amt.cnet> <20131106015543.GA20766@amt.cnet> <20131106213119.GA15543@amt.cnet> <20131106214034.GB22469@redhat.com> <20131106215351.GB15707@amt.cnet> <20131106221559.GA22730@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20131106221559.GA22730@redhat.com> Subject: Re: [Qemu-devel] i386: pc: align gpa<->hpa on 1GB boundary (v4) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: aarcange@redhat.com, gleb@redhat.com, qemu-devel@nongnu.org, Gerd Hoffmann , Igor Mammedov , pbonzini@redhat.com On Thu, Nov 07, 2013 at 12:15:59AM +0200, Michael S. Tsirkin wrote: > On Wed, Nov 06, 2013 at 07:53:51PM -0200, Marcelo Tosatti wrote: > > On Wed, Nov 06, 2013 at 11:40:34PM +0200, Michael S. Tsirkin wrote: > > > On Wed, Nov 06, 2013 at 07:31:19PM -0200, Marcelo Tosatti wrote: > > > > > > > > v2: condition enablement of new mapping to new machine types (Paolo) > > > > v3: fix changelog > > > > v4: rebase > > > > > > > > ----- > > > > > > > > > > > > Align guest physical address and host physical address > > > > beyond guest 4GB on a 1GB boundary. > > > > > > > > Otherwise 1GB TLBs cannot be cached for the range. > > > > > > > > Signed-off-by: Marcelo Tosatti > > > > > > Um. This will conflict with: > > > pc: map PCI address space as catchall region for not mapped addresses > > > > > > I think we really should stop using the hacked hole thing > > > and just use priorities like that patch does. > > > > Sorry hacked in what way? > > This patch is necessary to enable 1GB hugepages beyond 4GB of RAM on the > > current machine types. > > > Sorry if I wasn't clear. when I said "hacked" I was talking about the > pci hole concept generally in upstream qemu, not about your patch. > > Its hacked because there's no "pci hole" on PIIX. > pci hole is where pci was hiding some ram behind it > on some systems. AFAIK this is not what is happens on piix though. > What happens really is that everything not covered by RAM memory is PCI. > > We implemented this using two aliases of RAM but > the natural thing is really just making PCI lower > priority than RAM and let it overlap. > > > > Do you agree? If yes I'm afraid your patch will have to be > > > rebased on top of that yet again, sorry to give you a > > > run-around like that :( > > > > I don't see what exactly is the suggestion (or why the proposed > > patch should conflict with "pc: map PCI address space as catchall region > > for not mapped addresses"). > > It seemed to me that they will conflict but it's after midnight > so maybe I'm confused. > You are saying you apply yours on top and there's no conflict? > In that case I'll recheck, sorry. No conflict between "pc: map PCI address space as catchall region" and the proposed patch. > > > Also - do you think this is 1.7 material? > > > > No. Paolo mentioned you have a tree with 1.8 material, correct? > > Yes > > git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git pci