From mboxrd@z Thu Jan  1 00:00:00 1970
From: Alban Bedel <alban.bedel@avionic-design.de>
Date: Mon, 20 Jan 2014 11:24:37 +0100
Subject: [U-Boot] [PATCH] ARM: tegra20: Add a missing entry in the
	pullid enum
In-Reply-To: <52D6D513.7030506@wwwdotorg.org>
References: <1389797710-14396-1-git-send-email-alban.bedel@avionic-design.de>
	<52D6D513.7030506@wwwdotorg.org>
Message-ID: <20140120112437.67f99faa@avionic-0020>
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On Wed, 15 Jan 2014 11:36:03 -0700
Stephen Warren <swarren@wwwdotorg.org> wrote:

> On 01/15/2014 07:55 AM, Alban Bedel wrote:
> > It seems two entries were merged in one when this file has been
> > created. The GPSLXAU entries is obviously a mix of GPU and SLXA which
> > are next to each other according to the datasheet. Moreover it can be
> > noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have
> > 15 entries instead of 16.
> > 
> > Also fix the pin group descriptions that were using these buggy
> > entries. In particular SLXA that needed to used CRTP to actually
> > write the SLXA register.
> 
> This does appear to match the kernel's pinctrl driver, so,
> Acked-by: Stephen Warren <swarren@nvidia.com>
> 
> I wonder how many more similar issues there are. Did you check the whole
> file for this kind of issue, or just debug a problem with one particular
> pin/group?

I found this while trying to get the internal pull up enabled on UARTD.
Afterwards I checked the whole enum and the table but everything else
seems to be correct.

Alban