From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 4/9] drm/i915/bdw: Use centralized rc6 info print Date: Tue, 11 Feb 2014 17:12:17 +0100 Message-ID: <20140211161217.GN17001@phenom.ffwll.local> References: <1390969547-1018-1-git-send-email-benjamin.widawsky@intel.com> <1390969547-1018-5-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-la0-f54.google.com (mail-la0-f54.google.com [209.85.215.54]) by gabe.freedesktop.org (Postfix) with ESMTP id 1168DFA330 for ; Tue, 11 Feb 2014 08:12:23 -0800 (PST) Received: by mail-la0-f54.google.com with SMTP id y1so5985811lam.41 for ; Tue, 11 Feb 2014 08:12:23 -0800 (PST) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@freedesktop.org, Intel GFX , Ben Widawsky , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Thu, Feb 06, 2014 at 11:42:39AM -0200, Rodrigo Vivi wrote: > Reviewed-by: Rodrigo Vivi > > On Wed, Jan 29, 2014 at 2:25 AM, Ben Widawsky > wrote: > > Signed-off-by: Ben Widawsky > > --- > > drivers/gpu/drm/i915/intel_pm.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 944b99c..6acb429 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3215,10 +3215,10 @@ static void gen8_enable_rps(struct drm_device *dev) > > /* 3: Enable RC6 */ > > if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) > > rc6_mask = GEN6_RC_CTL_RC6_ENABLE; > > - DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); > > + intel_print_rc6_info(dev, rc6_mask); > > I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | > > - GEN6_RC_CTL_EI_MODE(1) | > > - rc6_mask); > > + GEN6_RC_CTL_EI_MODE(1) | > > + rc6_mask); > > > > /* 4 Program defaults and thresholds for RPS*/ > > I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */ > > -- > > 1.8.5.3 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx Merged up to this patch, but after that it gets confusing: - I have two patches 5/9. - 6/9 lacks review ... Mailing-list grues ate something? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch