* [Qemu-devel] [PATCH v2] q35: Correct typo BRDIGE -> BRIDGE
@ 2014-02-28 10:28 BALATON Zoltan
2014-03-10 18:38 ` BALATON Zoltan
2014-03-10 19:05 ` [Qemu-devel] " Michael S. Tsirkin
0 siblings, 2 replies; 5+ messages in thread
From: BALATON Zoltan @ 2014-02-28 10:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori, Michael S. Tsirkin
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
v2: Sorry, I was too fast to send it. Found two more places to change.
hw/pci-host/q35.c | 10 +++++-----
include/hw/i386/ich9.h | 2 +-
include/hw/pci-host/q35.h | 24 ++++++++++++------------
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 4bc2e01..8b8cc4e 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -272,7 +272,7 @@ static void mch_update_smram(MCHPCIState *mch)
PCIDevice *pd = PCI_DEVICE(mch);
memory_region_transaction_begin();
- smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
+ smram_update(&mch->smram_region, pd->config[MCH_HOST_BRIDGE_SMRAM],
mch->smm_enabled);
memory_region_transaction_commit();
}
@@ -283,7 +283,7 @@ static void mch_set_smm(int smm, void *arg)
PCIDevice *pd = PCI_DEVICE(mch);
memory_region_transaction_begin();
- smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
+ smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRIDGE_SMRAM],
&mch->smram_region);
memory_region_transaction_commit();
}
@@ -306,8 +306,8 @@ static void mch_write_config(PCIDevice *d,
mch_update_pciexbar(mch);
}
- if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
- MCH_HOST_BRDIGE_SMRAM_SIZE)) {
+ if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
+ MCH_HOST_BRIDGE_SMRAM_SIZE)) {
mch_update_smram(mch);
}
}
@@ -347,7 +347,7 @@ static void mch_reset(DeviceState *qdev)
pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
- d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
+ d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
mch_update(mch);
}
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 9e4a0e4..e191435 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -102,7 +102,7 @@ Object *ich9_lpc_find(void);
#define ICH9_USB_UHCI1_DEV 29
#define ICH9_USB_UHCI1_FUNC 0
-/* D30:F0 DMI-to-PCI brdige */
+/* D30:F0 DMI-to-PCI bridge */
#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index d0355b7..d9ee978 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -125,8 +125,8 @@ typedef struct Q35PCIHost {
#define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
#define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
-#define MCH_HOST_BRDIGE_SMRAM 0x9d
-#define MCH_HOST_BRDIGE_SMRAM_SIZE 1
+#define MCH_HOST_BRIDGE_SMRAM 0x9d
+#define MCH_HOST_BRIDGE_SMRAM_SIZE 1
#define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
#define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
#define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
@@ -140,16 +140,16 @@ typedef struct Q35PCIHost {
#define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
#define MCH_HOST_BRIDGE_ESMRAMC 0x9e
-#define MCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
-#define MCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
-#define MCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
-#define MCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
-#define MCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
-#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
-#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
-#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
-#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
-#define MCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
+#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
+#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
+#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
+#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
+#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
+#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
+#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
+#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
+#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
+#define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
/* D1:F0 PCIE* port*/
#define MCH_PCIE_DEV 1
--
1.8.1.5
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH v2] q35: Correct typo BRDIGE -> BRIDGE
2014-02-28 10:28 [Qemu-devel] [PATCH v2] q35: Correct typo BRDIGE -> BRIDGE BALATON Zoltan
@ 2014-03-10 18:38 ` BALATON Zoltan
2014-03-14 15:56 ` [Qemu-devel] [Qemu-trivial] " Michael Tokarev
2014-03-10 19:05 ` [Qemu-devel] " Michael S. Tsirkin
1 sibling, 1 reply; 5+ messages in thread
From: BALATON Zoltan @ 2014-03-10 18:38 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-trivial, Anthony Liguori, Michael S. Tsirkin
Ping!
Also here: http://patchwork.ozlabs.org/patch/325129/
On Fri, 28 Feb 2014, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
>
> v2: Sorry, I was too fast to send it. Found two more places to change.
>
> hw/pci-host/q35.c | 10 +++++-----
> include/hw/i386/ich9.h | 2 +-
> include/hw/pci-host/q35.h | 24 ++++++++++++------------
> 3 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index 4bc2e01..8b8cc4e 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -272,7 +272,7 @@ static void mch_update_smram(MCHPCIState *mch)
> PCIDevice *pd = PCI_DEVICE(mch);
>
> memory_region_transaction_begin();
> - smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
> + smram_update(&mch->smram_region, pd->config[MCH_HOST_BRIDGE_SMRAM],
> mch->smm_enabled);
> memory_region_transaction_commit();
> }
> @@ -283,7 +283,7 @@ static void mch_set_smm(int smm, void *arg)
> PCIDevice *pd = PCI_DEVICE(mch);
>
> memory_region_transaction_begin();
> - smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
> + smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRIDGE_SMRAM],
> &mch->smram_region);
> memory_region_transaction_commit();
> }
> @@ -306,8 +306,8 @@ static void mch_write_config(PCIDevice *d,
> mch_update_pciexbar(mch);
> }
>
> - if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
> - MCH_HOST_BRDIGE_SMRAM_SIZE)) {
> + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
> + MCH_HOST_BRIDGE_SMRAM_SIZE)) {
> mch_update_smram(mch);
> }
> }
> @@ -347,7 +347,7 @@ static void mch_reset(DeviceState *qdev)
> pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
> MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
>
> - d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
> + d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
>
> mch_update(mch);
> }
> diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
> index 9e4a0e4..e191435 100644
> --- a/include/hw/i386/ich9.h
> +++ b/include/hw/i386/ich9.h
> @@ -102,7 +102,7 @@ Object *ich9_lpc_find(void);
> #define ICH9_USB_UHCI1_DEV 29
> #define ICH9_USB_UHCI1_FUNC 0
>
> -/* D30:F0 DMI-to-PCI brdige */
> +/* D30:F0 DMI-to-PCI bridge */
> #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
> #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
>
> diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
> index d0355b7..d9ee978 100644
> --- a/include/hw/pci-host/q35.h
> +++ b/include/hw/pci-host/q35.h
> @@ -125,8 +125,8 @@ typedef struct Q35PCIHost {
> #define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
> #define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
>
> -#define MCH_HOST_BRDIGE_SMRAM 0x9d
> -#define MCH_HOST_BRDIGE_SMRAM_SIZE 1
> +#define MCH_HOST_BRIDGE_SMRAM 0x9d
> +#define MCH_HOST_BRIDGE_SMRAM_SIZE 1
> #define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
> #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
> #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
> @@ -140,16 +140,16 @@ typedef struct Q35PCIHost {
> #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
>
> #define MCH_HOST_BRIDGE_ESMRAMC 0x9e
> -#define MCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
> -#define MCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
> -#define MCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
> -#define MCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
> -#define MCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
> -#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
> -#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
> -#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
> -#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
> -#define MCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
> +#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
> +#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
> +#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
> +#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
> +#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
> +#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
> +#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
> +#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
> +#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
> +#define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
>
> /* D1:F0 PCIE* port*/
> #define MCH_PCIE_DEV 1
> --
> 1.8.1.5
>
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH v2] q35: Correct typo BRDIGE -> BRIDGE
2014-02-28 10:28 [Qemu-devel] [PATCH v2] q35: Correct typo BRDIGE -> BRIDGE BALATON Zoltan
2014-03-10 18:38 ` BALATON Zoltan
@ 2014-03-10 19:05 ` Michael S. Tsirkin
1 sibling, 0 replies; 5+ messages in thread
From: Michael S. Tsirkin @ 2014-03-10 19:05 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: qemu-devel, Anthony Liguori
On Fri, Feb 28, 2014 at 11:28:03AM +0100, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Applied, thanks!
> ---
>
> v2: Sorry, I was too fast to send it. Found two more places to change.
>
> hw/pci-host/q35.c | 10 +++++-----
> include/hw/i386/ich9.h | 2 +-
> include/hw/pci-host/q35.h | 24 ++++++++++++------------
> 3 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index 4bc2e01..8b8cc4e 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -272,7 +272,7 @@ static void mch_update_smram(MCHPCIState *mch)
> PCIDevice *pd = PCI_DEVICE(mch);
>
> memory_region_transaction_begin();
> - smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
> + smram_update(&mch->smram_region, pd->config[MCH_HOST_BRIDGE_SMRAM],
> mch->smm_enabled);
> memory_region_transaction_commit();
> }
> @@ -283,7 +283,7 @@ static void mch_set_smm(int smm, void *arg)
> PCIDevice *pd = PCI_DEVICE(mch);
>
> memory_region_transaction_begin();
> - smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
> + smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRIDGE_SMRAM],
> &mch->smram_region);
> memory_region_transaction_commit();
> }
> @@ -306,8 +306,8 @@ static void mch_write_config(PCIDevice *d,
> mch_update_pciexbar(mch);
> }
>
> - if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
> - MCH_HOST_BRDIGE_SMRAM_SIZE)) {
> + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
> + MCH_HOST_BRIDGE_SMRAM_SIZE)) {
> mch_update_smram(mch);
> }
> }
> @@ -347,7 +347,7 @@ static void mch_reset(DeviceState *qdev)
> pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
> MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
>
> - d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
> + d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
>
> mch_update(mch);
> }
> diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
> index 9e4a0e4..e191435 100644
> --- a/include/hw/i386/ich9.h
> +++ b/include/hw/i386/ich9.h
> @@ -102,7 +102,7 @@ Object *ich9_lpc_find(void);
> #define ICH9_USB_UHCI1_DEV 29
> #define ICH9_USB_UHCI1_FUNC 0
>
> -/* D30:F0 DMI-to-PCI brdige */
> +/* D30:F0 DMI-to-PCI bridge */
> #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
> #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
>
> diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
> index d0355b7..d9ee978 100644
> --- a/include/hw/pci-host/q35.h
> +++ b/include/hw/pci-host/q35.h
> @@ -125,8 +125,8 @@ typedef struct Q35PCIHost {
> #define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
> #define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
>
> -#define MCH_HOST_BRDIGE_SMRAM 0x9d
> -#define MCH_HOST_BRDIGE_SMRAM_SIZE 1
> +#define MCH_HOST_BRIDGE_SMRAM 0x9d
> +#define MCH_HOST_BRIDGE_SMRAM_SIZE 1
> #define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
> #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
> #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
> @@ -140,16 +140,16 @@ typedef struct Q35PCIHost {
> #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
>
> #define MCH_HOST_BRIDGE_ESMRAMC 0x9e
> -#define MCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
> -#define MCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
> -#define MCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
> -#define MCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
> -#define MCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
> -#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
> -#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
> -#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
> -#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
> -#define MCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
> +#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
> +#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
> +#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
> +#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
> +#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
> +#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
> +#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
> +#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
> +#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
> +#define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
>
> /* D1:F0 PCIE* port*/
> #define MCH_PCIE_DEV 1
> --
> 1.8.1.5
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [Qemu-trivial] [PATCH v2] q35: Correct typo BRDIGE -> BRIDGE
2014-03-10 18:38 ` BALATON Zoltan
@ 2014-03-14 15:56 ` Michael Tokarev
2014-03-14 17:52 ` BALATON Zoltan
0 siblings, 1 reply; 5+ messages in thread
From: Michael Tokarev @ 2014-03-14 15:56 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: qemu-trivial, qemu-devel, Michael S. Tsirkin
10.03.2014 22:38, BALATON Zoltan wrote:
> Ping!
> Also here: http://patchwork.ozlabs.org/patch/325129/
Hm? I thought mst applied it to his tree, no?
Applied to -trivial now, should not conflict if it'll
end up in another tree.
Thanks!
/mjt
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [Qemu-trivial] [PATCH v2] q35: Correct typo BRDIGE -> BRIDGE
2014-03-14 15:56 ` [Qemu-devel] [Qemu-trivial] " Michael Tokarev
@ 2014-03-14 17:52 ` BALATON Zoltan
0 siblings, 0 replies; 5+ messages in thread
From: BALATON Zoltan @ 2014-03-14 17:52 UTC (permalink / raw)
To: Michael Tokarev; +Cc: qemu-trivial, qemu-devel, Michael S. Tsirkin
On Fri, 14 Mar 2014, Michael Tokarev wrote:
> 10.03.2014 22:38, BALATON Zoltan wrote:
>> Ping!
>> Also here: http://patchwork.ozlabs.org/patch/325129/
>
> Hm? I thought mst applied it to his tree, no?
Yes he did and it's already merged.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-03-14 17:52 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-02-28 10:28 [Qemu-devel] [PATCH v2] q35: Correct typo BRDIGE -> BRIDGE BALATON Zoltan
2014-03-10 18:38 ` BALATON Zoltan
2014-03-14 15:56 ` [Qemu-devel] [Qemu-trivial] " Michael Tokarev
2014-03-14 17:52 ` BALATON Zoltan
2014-03-10 19:05 ` [Qemu-devel] " Michael S. Tsirkin
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all data and code used by this external index.