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diff for duplicates of <20140314132805.GD813@S2101-09.ap.freescale.net>

diff --git a/a/1.txt b/N1/1.txt
index 3857a63..2e20c98 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -9,7 +9,7 @@ On Thu, Mar 13, 2014 at 02:44:24PM -0700, Tim Harvey wrote:
 This line shouldn't be necessarily in the commit log.
 
 > 
-> Signed-off-by: Tim Harvey <tharvey-UMMOYl/HMS+akBO8gow8eQ@public.gmane.org>
+> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
 > ---
 >  arch/arm/boot/dts/imx6q-gw5400-a.dts  | 40 +++++++++++++++++++++++++++++++----
 >  arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 39 ++++++++++++++++++++++++++++++----
@@ -45,13 +45,13 @@ No need to add a new line.
 >  	reset-gpio = <&gpio1 29 0>;
 >  	status = "okay";
 >  
-> -	eth1: sky2@8 { /* MAC/PHY on bus 8 */
+> -	eth1: sky2 at 8 { /* MAC/PHY on bus 8 */
 > -		compatible = "marvell,sky2";
 
 So this was just a placeholder and did not actually work in any way,
 right?
 
-> +	pcie@0,0 {
+> +	pcie at 0,0 {
 
 Is this whole bridge/switch hierarchy binding documented somewhere or is
 this just something that work for you?
@@ -66,14 +66,14 @@ this just something that work for you?
 > +		 * GigE PCI dev node needs to be defined so that enet driver
 > +		 * can use it to obtain its boot-loader specified MAC
 > +		 */
-> +		pcie@0,0 {
+> +		pcie at 0,0 {
 > +			/* 01:00.0 PCIe switch */
 > +			#address-cells = <3>;
 > +			#size-cells = <2>;
 > +			device_type = "pci";
 > +			reg = <0x0 0 0 0 0>;
 > +
-> +			pcie@8,0 {
+> +			pcie at 8,0 {
 
 What's the naming schema for all these pcie nodes?  Generally, we should
 have the numbers encoded in the node name coming from the address cells
@@ -86,7 +86,7 @@ Shawn
 > +				#size-cells = <2>;
 > +				device_type = "pci";
 > +				reg = <0x4000 0 0 0 0>;
-> +				eth1: pcie@0,0 {
+> +				eth1: pcie at 0,0 {
 > +					/* 08:00.0 GigE */
 > +					#address-cells = <3>;
 > +					#size-cells = <2>;
@@ -124,33 +124,33 @@ Shawn
 >  	reset-gpio = <&gpio1 29 0>;
 >  	status = "okay";
 >  
-> -	eth1: sky2@8 { /* MAC/PHY on bus 8 */
+> -	eth1: sky2 at 8 { /* MAC/PHY on bus 8 */
 > -		compatible = "marvell,sky2";
 > +	/*
 > +	 * GigE PCI dev node needs to be defined so that enet driver
 > +	 * can use it to obtain its boot-loader specified MAC
 > +	 */
-> +	pcie@0,0 {
+> +	pcie at 0,0 {
 > +		/* 00:00.0 root host-bridge */
 > +		#address-cells = <3>;
 > +		#size-cells = <2>;
 > +		device_type = "pci";
 > +		reg = <0x0 0 0 0 0>;
 > +
-> +		pcie@0,0 {
+> +		pcie at 0,0 {
 > +			/* 01:00.0 PCIe switch */
 > +			#address-cells = <3>;
 > +			#size-cells = <2>;
 > +			device_type = "pci";
 > +			reg = <0x0 0 0 0 0>;
 > +
-> +			pcie@4,0 {
+> +			pcie at 4,0 {
 > +				/* 02:04.0 PCIe switch port */
 > +				#address-cells = <3>;
 > +				#size-cells = <2>;
 > +				device_type = "pci";
 > +				reg = <0x2000 0 0 0 0>;
-> +				eth1: pcie@0,0 {
+> +				eth1: pcie at 0,0 {
 > +					/* 04:00.0 GigE */
 > +					#address-cells = <3>;
 > +					#size-cells = <2>;
@@ -188,33 +188,33 @@ Shawn
 >  	reset-gpio = <&gpio1 29 0>;
 >  	status = "okay";
 >  
-> -	eth1: sky2@8 { /* MAC/PHY on bus 8 */
+> -	eth1: sky2 at 8 { /* MAC/PHY on bus 8 */
 > -		compatible = "marvell,sky2";
 > +	/*
 > +	 * GigE PCI dev node needs to be defined so that enet driver
 > +	 * can use it to obtain its boot-loader specified MAC
 > +	 */
-> +	pcie@0,0 {
+> +	pcie at 0,0 {
 > +		/* 00:00.0 root host-bridge */
 > +		#address-cells = <3>;
 > +		#size-cells = <2>;
 > +		device_type = "pci";
 > +		reg = <0x0 0 0 0 0>;
 > +
-> +		pcie@0,0 {
+> +		pcie at 0,0 {
 > +			/* 01:00.0 PCIe switch */
 > +			#address-cells = <3>;
 > +			#size-cells = <2>;
 > +			device_type = "pci";
 > +			reg = <0x0 0 0 0 0>;
 > +
-> +			pcie@8,0 {
+> +			pcie at 8,0 {
 > +				/* 02:08.0 PCIe switch port */
 > +				#address-cells = <3>;
 > +				#size-cells = <2>;
 > +				device_type = "pci";
 > +				reg = <0x4000 0 0 0 0>;
-> +				eth1: pcie@0,0 {
+> +				eth1: pcie at 0,0 {
 > +					/* 08:00.0 GigE */
 > +					#address-cells = <3>;
 > +					#size-cells = <2>;
@@ -233,12 +233,7 @@ Shawn
 > 
 > _______________________________________________
 > linux-arm-kernel mailing list
-> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
+> linux-arm-kernel at lists.infradead.org
 > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 > 
-> 
-
---
-To unsubscribe from this list: send the line "unsubscribe devicetree" in
-the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
-More majordomo info at  http://vger.kernel.org/majordomo-info.html
\ No newline at end of file
+>
\ No newline at end of file
diff --git a/a/content_digest b/N1/content_digest
index 2d162dc..ae4741b 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,24 +2,16 @@
   "ref\0001394747064-4106-1-git-send-email-tharvey\@gateworks.com\0"
 ]
 [
-  "ref\0001394747064-4106-1-git-send-email-tharvey-UMMOYl/HMS+akBO8gow8eQ\@public.gmane.org\0"
+  "From\0shawn.guo\@freescale.com (Shawn Guo)\0"
 ]
 [
-  "From\0Shawn Guo <shawn.guo-KZfg59tc24xl57MIdRCFDg\@public.gmane.org>\0"
-]
-[
-  "Subject\0Re: [PATCH] ARM: dts: ventana: fix eth1 pci dev node\0"
+  "Subject\0[PATCH] ARM: dts: ventana: fix eth1 pci dev node\0"
 ]
 [
   "Date\0Fri, 14 Mar 2014 21:28:06 +0800\0"
 ]
 [
-  "To\0Tim Harvey <tharvey-UMMOYl/HMS+akBO8gow8eQ\@public.gmane.org>\0"
-]
-[
-  "Cc\0devicetree-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
-  " Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>",
-  " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org\0"
+  "To\0linux-arm-kernel\@lists.infradead.org\0"
 ]
 [
   "\0000:1\0"
@@ -39,7 +31,7 @@
   "This line shouldn't be necessarily in the commit log.\n",
   "\n",
   "> \n",
-  "> Signed-off-by: Tim Harvey <tharvey-UMMOYl/HMS+akBO8gow8eQ\@public.gmane.org>\n",
+  "> Signed-off-by: Tim Harvey <tharvey\@gateworks.com>\n",
   "> ---\n",
   ">  arch/arm/boot/dts/imx6q-gw5400-a.dts  | 40 +++++++++++++++++++++++++++++++----\n",
   ">  arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 39 ++++++++++++++++++++++++++++++----\n",
@@ -75,13 +67,13 @@
   ">  \treset-gpio = <&gpio1 29 0>;\n",
   ">  \tstatus = \"okay\";\n",
   ">  \n",
-  "> -\teth1: sky2\@8 { /* MAC/PHY on bus 8 */\n",
+  "> -\teth1: sky2 at 8 { /* MAC/PHY on bus 8 */\n",
   "> -\t\tcompatible = \"marvell,sky2\";\n",
   "\n",
   "So this was just a placeholder and did not actually work in any way,\n",
   "right?\n",
   "\n",
-  "> +\tpcie\@0,0 {\n",
+  "> +\tpcie at 0,0 {\n",
   "\n",
   "Is this whole bridge/switch hierarchy binding documented somewhere or is\n",
   "this just something that work for you?\n",
@@ -96,14 +88,14 @@
   "> +\t\t * GigE PCI dev node needs to be defined so that enet driver\n",
   "> +\t\t * can use it to obtain its boot-loader specified MAC\n",
   "> +\t\t */\n",
-  "> +\t\tpcie\@0,0 {\n",
+  "> +\t\tpcie at 0,0 {\n",
   "> +\t\t\t/* 01:00.0 PCIe switch */\n",
   "> +\t\t\t#address-cells = <3>;\n",
   "> +\t\t\t#size-cells = <2>;\n",
   "> +\t\t\tdevice_type = \"pci\";\n",
   "> +\t\t\treg = <0x0 0 0 0 0>;\n",
   "> +\n",
-  "> +\t\t\tpcie\@8,0 {\n",
+  "> +\t\t\tpcie at 8,0 {\n",
   "\n",
   "What's the naming schema for all these pcie nodes?  Generally, we should\n",
   "have the numbers encoded in the node name coming from the address cells\n",
@@ -116,7 +108,7 @@
   "> +\t\t\t\t#size-cells = <2>;\n",
   "> +\t\t\t\tdevice_type = \"pci\";\n",
   "> +\t\t\t\treg = <0x4000 0 0 0 0>;\n",
-  "> +\t\t\t\teth1: pcie\@0,0 {\n",
+  "> +\t\t\t\teth1: pcie at 0,0 {\n",
   "> +\t\t\t\t\t/* 08:00.0 GigE */\n",
   "> +\t\t\t\t\t#address-cells = <3>;\n",
   "> +\t\t\t\t\t#size-cells = <2>;\n",
@@ -154,33 +146,33 @@
   ">  \treset-gpio = <&gpio1 29 0>;\n",
   ">  \tstatus = \"okay\";\n",
   ">  \n",
-  "> -\teth1: sky2\@8 { /* MAC/PHY on bus 8 */\n",
+  "> -\teth1: sky2 at 8 { /* MAC/PHY on bus 8 */\n",
   "> -\t\tcompatible = \"marvell,sky2\";\n",
   "> +\t/*\n",
   "> +\t * GigE PCI dev node needs to be defined so that enet driver\n",
   "> +\t * can use it to obtain its boot-loader specified MAC\n",
   "> +\t */\n",
-  "> +\tpcie\@0,0 {\n",
+  "> +\tpcie at 0,0 {\n",
   "> +\t\t/* 00:00.0 root host-bridge */\n",
   "> +\t\t#address-cells = <3>;\n",
   "> +\t\t#size-cells = <2>;\n",
   "> +\t\tdevice_type = \"pci\";\n",
   "> +\t\treg = <0x0 0 0 0 0>;\n",
   "> +\n",
-  "> +\t\tpcie\@0,0 {\n",
+  "> +\t\tpcie at 0,0 {\n",
   "> +\t\t\t/* 01:00.0 PCIe switch */\n",
   "> +\t\t\t#address-cells = <3>;\n",
   "> +\t\t\t#size-cells = <2>;\n",
   "> +\t\t\tdevice_type = \"pci\";\n",
   "> +\t\t\treg = <0x0 0 0 0 0>;\n",
   "> +\n",
-  "> +\t\t\tpcie\@4,0 {\n",
+  "> +\t\t\tpcie at 4,0 {\n",
   "> +\t\t\t\t/* 02:04.0 PCIe switch port */\n",
   "> +\t\t\t\t#address-cells = <3>;\n",
   "> +\t\t\t\t#size-cells = <2>;\n",
   "> +\t\t\t\tdevice_type = \"pci\";\n",
   "> +\t\t\t\treg = <0x2000 0 0 0 0>;\n",
-  "> +\t\t\t\teth1: pcie\@0,0 {\n",
+  "> +\t\t\t\teth1: pcie at 0,0 {\n",
   "> +\t\t\t\t\t/* 04:00.0 GigE */\n",
   "> +\t\t\t\t\t#address-cells = <3>;\n",
   "> +\t\t\t\t\t#size-cells = <2>;\n",
@@ -218,33 +210,33 @@
   ">  \treset-gpio = <&gpio1 29 0>;\n",
   ">  \tstatus = \"okay\";\n",
   ">  \n",
-  "> -\teth1: sky2\@8 { /* MAC/PHY on bus 8 */\n",
+  "> -\teth1: sky2 at 8 { /* MAC/PHY on bus 8 */\n",
   "> -\t\tcompatible = \"marvell,sky2\";\n",
   "> +\t/*\n",
   "> +\t * GigE PCI dev node needs to be defined so that enet driver\n",
   "> +\t * can use it to obtain its boot-loader specified MAC\n",
   "> +\t */\n",
-  "> +\tpcie\@0,0 {\n",
+  "> +\tpcie at 0,0 {\n",
   "> +\t\t/* 00:00.0 root host-bridge */\n",
   "> +\t\t#address-cells = <3>;\n",
   "> +\t\t#size-cells = <2>;\n",
   "> +\t\tdevice_type = \"pci\";\n",
   "> +\t\treg = <0x0 0 0 0 0>;\n",
   "> +\n",
-  "> +\t\tpcie\@0,0 {\n",
+  "> +\t\tpcie at 0,0 {\n",
   "> +\t\t\t/* 01:00.0 PCIe switch */\n",
   "> +\t\t\t#address-cells = <3>;\n",
   "> +\t\t\t#size-cells = <2>;\n",
   "> +\t\t\tdevice_type = \"pci\";\n",
   "> +\t\t\treg = <0x0 0 0 0 0>;\n",
   "> +\n",
-  "> +\t\t\tpcie\@8,0 {\n",
+  "> +\t\t\tpcie at 8,0 {\n",
   "> +\t\t\t\t/* 02:08.0 PCIe switch port */\n",
   "> +\t\t\t\t#address-cells = <3>;\n",
   "> +\t\t\t\t#size-cells = <2>;\n",
   "> +\t\t\t\tdevice_type = \"pci\";\n",
   "> +\t\t\t\treg = <0x4000 0 0 0 0>;\n",
-  "> +\t\t\t\teth1: pcie\@0,0 {\n",
+  "> +\t\t\t\teth1: pcie at 0,0 {\n",
   "> +\t\t\t\t\t/* 08:00.0 GigE */\n",
   "> +\t\t\t\t\t#address-cells = <3>;\n",
   "> +\t\t\t\t\t#size-cells = <2>;\n",
@@ -263,15 +255,10 @@
   "> \n",
   "> _______________________________________________\n",
   "> linux-arm-kernel mailing list\n",
-  "> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org\n",
+  "> linux-arm-kernel at lists.infradead.org\n",
   "> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel\n",
   "> \n",
-  "> \n",
-  "\n",
-  "--\n",
-  "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n",
-  "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org\n",
-  "More majordomo info at  http://vger.kernel.org/majordomo-info.html"
+  ">"
 ]
 
-c9118c0a840f9ef02072cce257fd46d6457e13b1ffd31f30a14bd537f1b8b6ec
+272012bc1e982d1182a91d176b28ae8a229fe3a1ba145bca7da860d1eb06d61d

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