From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 07/12] drm/i915/bdw: Set initial rps freq to RP0 Date: Thu, 20 Mar 2014 07:24:38 +0000 Message-ID: <20140320072438.GE4890@nuc-i3427.alporthouse.com> References: <1392692512-2268-1-git-send-email-benjamin.widawsky@intel.com> <1395279079-12704-1-git-send-email-benjamin.widawsky@intel.com> <1395279079-12704-8-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (mail.fireflyinternet.com [87.106.93.118]) by gabe.freedesktop.org (Postfix) with ESMTP id CDB87891FB for ; Thu, 20 Mar 2014 00:24:41 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1395279079-12704-8-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: Intel GFX List-Id: intel-gfx@lists.freedesktop.org On Wed, Mar 19, 2014 at 06:31:14PM -0700, Ben Widawsky wrote: > Programming it outside of the rp0-rp1 range is considered a programming > error. Since we do not know that the previous value would actually be in > the range, program something we've read from the hardware, and therefore > know will work. > > This is potentially an issue for platforms whose ranges are outside the > norms given in the programming guide (ie. early silicon) > > v2: Use RP1 instead of RPn > > Signed-off-by: Ben Widawsky Do you have a reference for GEN6_RC_VIDEO_FREQ? I still have no idea what that controls, nor its valid range. -Chris -- Chris Wilson, Intel Open Source Technology Centre