From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' Date: Mon, 24 Mar 2014 09:39:11 +0000 Message-ID: <20140324093911.GN4366@nuc-i3427.alporthouse.com> References: <1395643764-24353-1-git-send-email-sourab.gupta@intel.com> <1395643764-24353-3-git-send-email-sourab.gupta@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (mail.fireflyinternet.com [87.106.93.118]) by gabe.freedesktop.org (Postfix) with ESMTP id 418926E92B for ; Mon, 24 Mar 2014 02:39:23 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1395643764-24353-3-git-send-email-sourab.gupta@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: sourab.gupta@intel.com Cc: Akash Goel , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Mar 24, 2014 at 12:19:20PM +0530, sourab.gupta@intel.com wrote: > From: Akash Goel > > This workaround is needed on VLV for the HW context feature. > It is used after adding the mi_set_context command in ring buffer > for Hw context switch. As per the spec > "The software must send a pipe_control with a CS stall and a post sync > operation and then a dummy DRAW after every MI_SET_CONTEXT and after any > PIPELINE_SELECT that is enabling 3D mode". > > Signed-off-by: Akash Goel > Signed-off-by: Sourab Gupta > --- > drivers/gpu/drm/i915/i915_gem_context.c | 65 ++++++++++++++++++++++++++++++++- > drivers/gpu/drm/i915/i915_reg.h | 3 ++ > drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++ > drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + > 4 files changed, 76 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c > index 6043062..544fc2d 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > @@ -584,6 +584,58 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) > return ctx; > } > > +static inline void > +mi_set_context_dummy3d_prim_wa(struct intel_ring_buffer *ring) > +{ > + u32 scratch_addr; > + u32 flags = 0; > + > + /* > + * Check if we have the scratch page allocated needed > + * for the Pipe Control command, otherwise don't apply > + * the dummmy 3d primitive workaround & add NOOPs instead > + */ > + if (get_pipe_control_scratch_addr(ring)) { 0 is a valid address. Plus using an unprefixed global static inline is frown upon. Also we cannot get here without allocating a scratch_obj, so we can forgo the test completely (and then kill the get_pipe_control_scratch_addr). > + /* Actual scratch location is at 128 bytes offset */ > + scratch_addr = get_pipe_control_scratch_addr(ring) + 128; > + > + /* > + * WaSendDummy3dPrimitveAfterSetContext:vlv > + * Software must send a pipe_control with a CS stall > + * and a post sync operation and then a dummy DRAW after > + * every MI_SET_CONTEXT and after any PIPELINE_SELECT that > + * is enabling 3D mode. A dummy draw is a 3DPRIMITIVE command > + * with Indirect Parameter Enable set to 0, UAV Coherency > + * Required set to 0, Predicate Enable set to 0, > + * End Offset Enable set to 0, and Vertex Count Per Instance > + * set to 0, All other parameters are a don't care. > + */ > + > + /* > + * Add a pipe control with CS Stall and postsync op > + * before dummy 3D_PRIMITIVE > + */ > + flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; > + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); > + intel_ring_emit(ring, flags); > + intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); > + intel_ring_emit(ring, 0); > + > + /* Add a dummy 3D_PRIMITVE */ > + intel_ring_emit(ring, GFX_OP_3DPRIMITIVE()); GFX_OP_3DPRIMITIVE emulates a function, why? I thought it was a constant. > + intel_ring_emit(ring, 4); /* PrimTopoType*/ > + intel_ring_emit(ring, 0); /* VertexCountPerInstance */ > + intel_ring_emit(ring, 0); /* StartVertexLocation */ > + intel_ring_emit(ring, 0); /* InstanceCount */ > + intel_ring_emit(ring, 0); /* StartInstanceLocation */ > + intel_ring_emit(ring, 0); /* BaseVertexLocation */ > + } else { > + int i; > + for (i = 0; i < 11; i++) > + intel_ring_emit(ring, MI_NOOP); > + } > +} > + > static inline int > mi_set_context(struct intel_ring_buffer *ring, > struct i915_hw_context *new_context, > @@ -602,7 +654,10 @@ mi_set_context(struct intel_ring_buffer *ring, > return ret; > } > > - ret = intel_ring_begin(ring, 6); > + if (IS_VALLEYVIEW(ring->dev)) > + ret = intel_ring_begin(ring, 6+4+8); > + else > + ret = intel_ring_begin(ring, 6); > if (ret) > return ret; > > @@ -626,7 +681,13 @@ mi_set_context(struct intel_ring_buffer *ring, > intel_ring_emit(ring, MI_NOOP); > > if (IS_GEN7(ring->dev)) > - intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); > + if (IS_VALLEYVIEW(ring->dev)) { > + /* FIXME, should also apply to ivb */ > + mi_set_context_dummy3d_prim_wa(ring); > + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); > + intel_ring_emit(ring, MI_NOOP); > + } else > + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); > else > intel_ring_emit(ring, MI_NOOP); > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index adcb9c7..fd25e8e4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -348,6 +348,9 @@ > #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) > #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ > > +#define GFX_OP_3DPRIMITIVE() \ > + ((0x3<<29)|(0x3<<27)|(0x3<<24)| \ > + (0x0<<16)|(0x0<<10)|(0x0<<8)|(7-2)) Please emulate the style we use else where for splitting this up into client, opcode, subop, len etc. -Chris -- Chris Wilson, Intel Open Source Technology Centre