Re: [PATCH v5] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore'

[Chris Wilson <chris@chris-wilson.co.uk>]

On Tue, Mar 25, 2014 at 02:01:05PM +0530, sourab.gupta@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> This workaround has to be applied before doing TLB Invalidation.
> In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
> Store data commands.
> Without this, hardware cannot guarantee the command after the PIPE_CONTROL
> with TLB inv will not use the old TLB values.
> 
> v2: Modified the WA comment (Ville)
> 
> v3: Added the vlv identifier with WA name (Damien)
> 
> v4: Reworked based on Chris' comments (WA moved to gen7 ring flush func,
> sending 6 dwords instead of 8) (Chris)
> 
> v5: Enhancing the scope of WA to gen6, gen7. Having a common WA func being
> called from gen6, gen7 flush functions. (Ville)
> 
> @@ -1733,6 +1771,13 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
>  	uint32_t cmd;
>  	int ret;
>  
> +	/* Apply WaTlbInvalidateStoreDataBefore workaround */
> +	if (invalidate) {
> +		ret = gen6_tlb_invalidate_wa(ring);
> +		if (ret)
> +			return ret;
> +	}

BSD uses MI_FLUSH_DW. Does this w/a still apply? Do we need it for BLT
as well? VEBOX?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre