From mboxrd@z Thu Jan  1 00:00:00 1970
From: Damien Lespiau <damien.lespiau@intel.com>
Subject: Re: [PATCH 17/49] drm/i915/bdw: A bit more advanced
 context init/fini
Date: Tue, 1 Apr 2014 14:51:27 +0100
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To: "Mateo Lozano, Oscar" <oscar.mateo@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>, Ben Widawsky <ben@bwidawsk.net>, "Widawsky,
 Benjamin" <benjamin.widawsky@intel.com>
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On Tue, Apr 01, 2014 at 02:47:19PM +0100, Mateo Lozano, Oscar wrote:
> > > --- a/drivers/gpu/drm/i915/i915_lrc.c
> > > +++ b/drivers/gpu/drm/i915/i915_lrc.c
> > > @@ -41,7 +41,45 @@
> > >  #include <drm/i915_drm.h>
> > >  #include "i915_drv.h"
> > >
> > > +#define GEN8_LR_CONTEXT_SIZE (21 * PAGE_SIZE)
> > =

> > I'm a bit puzzled by that number:
> >   - I found a sentence saying: "the Context Image for the rendering
> >     engine consists of 20 4K pages", which seems that it includes the
> >     HWS page (on the same page it says context layout =3D HWS Page +
> >     register state context).
> >   - When looking at the register state context for the render engine:
> >     18096 dwords -> 18 pages, so in total it'd be 19 pages (need to add
> >     the HWS Page)
> >   - Clearly I must be missing something :)
> >   - That's only for the render engine, other engines have a much smaller
> >     context, smaller enough that it's worth looking at their exact size.
> >   - It'd be nice to work out the real size from the *CXT_*SIZE
> >     registers.
> =

> Hmmmm... I=B4ll try to get the real context sizes from the registers and
> compare. At least for RCS, VCS and BCS since there doesn=B4t seem to be
> a register for VECS?

Couldn't find it either. I guess we'll need to ask the help of a friend.
Or the 50/50 joker maybe.

-- =

Damien