From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH 17/49] drm/i915/bdw: A bit more advanced context init/fini Date: Tue, 1 Apr 2014 22:05:12 +0100 Message-ID: <20140401210512.GH16291@strange.amr.corp.intel.com> References: <1395943218-7708-1-git-send-email-oscar.mateo@intel.com> <1395943218-7708-18-git-send-email-oscar.mateo@intel.com> <20140401003804.GA26578@strange.amr.corp.intel.com> <92648605EABDA246B775AAB04C95A7A3012BE598@IRSMSX103.ger.corp.intel.com> <20140401135127.GD16291@strange.amr.corp.intel.com> <20140401191824.GA19493@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A5F06E868 for ; Tue, 1 Apr 2014 14:05:22 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140401191824.GA19493@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: "intel-gfx@lists.freedesktop.org" , "Widawsky, Benjamin" List-Id: intel-gfx@lists.freedesktop.org On Tue, Apr 01, 2014 at 12:18:24PM -0700, Ben Widawsky wrote: > On Tue, Apr 01, 2014 at 02:51:27PM +0100, Damien Lespiau wrote: > > On Tue, Apr 01, 2014 at 02:47:19PM +0100, Mateo Lozano, Oscar wrote: > > > > > --- a/drivers/gpu/drm/i915/i915_lrc.c > > > > > +++ b/drivers/gpu/drm/i915/i915_lrc.c > > > > > @@ -41,7 +41,45 @@ > > > > > #include > > > > > #include "i915_drv.h" > > > > > > > > > > +#define GEN8_LR_CONTEXT_SIZE (21 * PAGE_SIZE) > > > > = > > > > I'm a bit puzzled by that number: > > > > - I found a sentence saying: "the Context Image for the rendering > > > > engine consists of 20 4K pages", which seems that it includes t= he > > > > HWS page (on the same page it says context layout =3D HWS Page + > > > > register state context). > > > > - When looking at the register state context for the render engin= e: > > > > 18096 dwords -> 18 pages, so in total it'd be 19 pages (need to= add > > > > the HWS Page) > > > > - Clearly I must be missing something :) > > > > - That's only for the render engine, other engines have a much sm= aller > > > > context, smaller enough that it's worth looking at their exact = size. > > > > - It'd be nice to work out the real size from the *CXT_*SIZE > > > > registers. > > > = > > > Hmmmm... I=B4ll try to get the real context sizes from the registers = and > > > compare. At least for RCS, VCS and BCS since there doesn=B4t seem to = be > > > a register for VECS? > > = > > Couldn't find it either. I guess we'll need to ask the help of a friend. > > Or the 50/50 joker maybe. > > = > > -- = > > Damien > = > CXT_SIZE is total garbage on anything past Ivybridge. That's why we > don't use it for HSW either... I know, right? We should request the spec > get updated. I have no excuse for not requesting that sooner. (talking about BDW only) For the render ring: HWSP: 4KB Ring context: CTX_SIZE[26:24] 5 cache lines -> offsets (in DW) 0x0 to 0x4f = (=3D 5 * 64 / 4) Render context: CTX_SIZE[23:16] -> 0x65 caches lines -> offets (in DW) 0x50= to 0x69f (=3D 0x50 + 0x65 * 64 / 4 - 1) VF/VFE context CTX_SIZE[7:0] -> 0x82 cache lines -> offsets (in DW) 0x6A0 t= o 0xebf (=3D 0x6a0 + 0x82*64/4 - 1) Atomic storage is the max that you can allocate, 32KB ie 8192 DWords So we're almost there. What's missing here is the RS context size, couldn't= find it in the spec :/ Maybe because that is a "well known" value. Note that I don't actually know what we read back from hw. Considering that the BCS context size seems to be 2 pages, I think it's wor= th digging a bit more to save ~66KB per BCS context (for instance). Even if we have to hardcode the different context sizes. -- = Damien