From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH 42/49] drm/i915/bdw: Get prepared for a two-stage execlist submit process Date: Fri, 4 Apr 2014 12:12:35 +0100 Message-ID: <20140404111235.GB28222@strange.amr.corp.intel.com> References: <1395943218-7708-1-git-send-email-oscar.mateo@intel.com> <1395943218-7708-43-git-send-email-oscar.mateo@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 76E0C6ED3D for ; Fri, 4 Apr 2014 04:12:43 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1395943218-7708-43-git-send-email-oscar.mateo@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: oscar.mateo@intel.com Cc: Thomas Daniel , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Mar 27, 2014 at 06:00:11PM +0000, oscar.mateo@intel.com wrote: > +int gen8_switch_context_queue(struct intel_engine *ring, > + struct i915_hw_context *to, > + u32 tail) > +{ > + struct drm_i915_gem_request *req = NULL; > + unsigned long flags; > + bool was_empty; > + > + req = (struct drm_i915_gem_request *) > + kmalloc(sizeof(struct drm_i915_gem_request), GFP_KERNEL); > + req->ring = ring; > + req->ctx = to; > + i915_gem_context_reference(req->ctx); > + req->tail = tail; Need to test if the allocation has succeeded and return an error if not. -- Damien