From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2 10/25] drm/i915: gen2: move error capture of IER to its correct place Date: Wed, 16 Apr 2014 15:22:32 +0300 Message-ID: <20140416122232.GE18465@intel.com> References: <1397496286-29649-1-git-send-email-imre.deak@intel.com> <1397496286-29649-11-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id CA3966E38A for ; Wed, 16 Apr 2014 05:22:43 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397496286-29649-11-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 14, 2014 at 08:24:31PM +0300, Imre Deak wrote: > While checking the error capture path I noticed that this register is > read twice for GEN2, so fix this and also move the read where it's done > for other platforms. > = > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_gpu_error.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915= /i915_gpu_error.c > index 4865ade..ba79b59 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1053,9 +1053,6 @@ static void i915_capture_reg_state(struct drm_i915_= private *dev_priv, > error->gfx_mode =3D I915_READ(GFX_MODE); > } > = > - if (IS_GEN2(dev)) > - error->ier =3D I915_READ16(IER); > - > /* 2: Registers which belong to multiple generations */ > if (INTEL_INFO(dev)->gen >=3D 7) > error->forcewake =3D I915_READ(FORCEWAKE_MT); > @@ -1079,7 +1076,10 @@ static void i915_capture_reg_state(struct drm_i915= _private *dev_priv, > if (HAS_PCH_SPLIT(dev)) > error->ier =3D I915_READ(DEIER) | I915_READ(GTIER); > else { > - error->ier =3D I915_READ(IER); > + if (IS_GEN2(dev)) > + error->ier =3D I915_READ16(IER); > + else > + error->ier =3D I915_READ(IER); > for_each_pipe(pipe) > error->pipestat[pipe] =3D I915_READ(PIPESTAT(pipe)); > } The IER handling seems fairly bogus all around. On VLV and PCH platforms we smash both the display and GT IER into the same u32. So probably no one can make any sense of the result. Also I don't know why we try to dump only these two interrupt registers but not the others. So seems like there's more work that needs to be done here. > -- = > 1.8.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC