From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v3 21/25] drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending force-off Date: Wed, 23 Apr 2014 11:11:47 +0300 Message-ID: <20140423081147.GC18465@intel.com> References: <1397496286-29649-22-git-send-email-imre.deak@intel.com> <1397828102-11139-1-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 8545F6EA0F for ; Wed, 23 Apr 2014 01:12:21 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397828102-11139-1-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Apr 18, 2014 at 04:35:02PM +0300, Imre Deak wrote: > This will be needed by the VLV runtime PM helpers too, so factor it out. > = > Also add a safety check for the case where the previous force-off is > still pending, since I'm not sure if Punit can handle a new setting > while the previous one hasn't settled yet. > = > v2: > - unchanged > v3: > - add a note to the commit message about the safety check (Ville) > = > Signed-off-by: Imre Deak Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_drv.c | 37 +++++++++++++++++++++++++++++++++++= ++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 16 ++-------------- > 3 files changed, 40 insertions(+), 14 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_= drv.c > index 1f88917..795caea 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -905,6 +905,43 @@ static void hsw_runtime_resume(struct drm_i915_priva= te *dev_priv) > hsw_disable_pc8(dev_priv); > } > = > +int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) > +{ > + u32 val; > + int err; > + > + val =3D I915_READ(VLV_GTLC_SURVIVABILITY_REG); > + WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) =3D=3D force_on); > + > +#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS= _BIT) > + /* Wait for a previous force-off to settle */ > + if (force_on) { > + err =3D wait_for(!COND, 5); > + if (err) { > + DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", > + I915_READ(VLV_GTLC_SURVIVABILITY_REG)); > + return err; > + } > + } > + > + val =3D I915_READ(VLV_GTLC_SURVIVABILITY_REG); > + val &=3D ~VLV_GFX_CLK_FORCE_ON_BIT; > + if (force_on) > + val |=3D VLV_GFX_CLK_FORCE_ON_BIT; > + I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); > + > + if (!force_on) > + return 0; > + > + err =3D wait_for(COND, 5); > + if (err) > + DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", > + I915_READ(VLV_GTLC_SURVIVABILITY_REG)); > + > + return err; > +#undef COND > +} > + > static int intel_runtime_suspend(struct device *device) > { > struct pci_dev *pdev =3D to_pci_dev(device); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index 5254f4b..3cac434 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1968,6 +1968,7 @@ extern unsigned long i915_chipset_val(struct drm_i9= 15_private *dev_priv); > extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); > extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); > extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); > +int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); > = > extern void intel_console_resume(struct work_struct *work); > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index c45e5c1..d64ac32 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3129,16 +3129,7 @@ static void vlv_set_rps_idle(struct drm_i915_priva= te *dev_priv) > /* Mask turbo interrupt so that they will not come in between */ > I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); > = > - /* Bring up the Gfx clock */ > - I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, > - I915_READ(VLV_GTLC_SURVIVABILITY_REG) | > - VLV_GFX_CLK_FORCE_ON_BIT); > - > - if (wait_for(((VLV_GFX_CLK_STATUS_BIT & > - I915_READ(VLV_GTLC_SURVIVABILITY_REG)) !=3D 0), 5)) { > - DRM_ERROR("GFX_CLK_ON request timed out\n"); > - return; > - } > + vlv_force_gfx_clock(dev_priv, true); > = > dev_priv->rps.cur_freq =3D dev_priv->rps.min_freq_softlimit; > = > @@ -3149,10 +3140,7 @@ static void vlv_set_rps_idle(struct drm_i915_priva= te *dev_priv) > & GENFREQSTATUS) =3D=3D 0, 5)) > DRM_ERROR("timed out waiting for Punit\n"); > = > - /* Release the Gfx clock */ > - I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, > - I915_READ(VLV_GTLC_SURVIVABILITY_REG) & > - ~VLV_GFX_CLK_FORCE_ON_BIT); > + vlv_force_gfx_clock(dev_priv, false); > = > I915_WRITE(GEN6_PMINTRMSK, > gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); > -- = > 1.8.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC