From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/bdw: Don't allow the FBC base to be 0 Date: Thu, 15 May 2014 17:05:05 +0300 Message-ID: <20140515140505.GC27580@intel.com> References: <1398995274-1317-1-git-send-email-benjamin.widawsky@intel.com> <20140502081927.GR18465@intel.com> <20140502083811.GA21695@nuc-i3427.alporthouse.com> <20140502130024.GT18465@intel.com> <20140502170000.GA11639@bwidawsk.net> <20140502203520.GA9420@nuc-i3427.alporthouse.com> <20140503014851.GA22130@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 4091A6EE4F for ; Thu, 15 May 2014 07:05:36 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140503014851.GA22130@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: Art Runyan , Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Fri, May 02, 2014 at 06:48:52PM -0700, Ben Widawsky wrote: > On Fri, May 02, 2014 at 09:35:20PM +0100, Chris Wilson wrote: > > On Fri, May 02, 2014 at 10:00:01AM -0700, Ben Widawsky wrote: > > > On Fri, May 02, 2014 at 04:00:25PM +0300, Ville Syrj=E4l=E4 wrote: > > > > On Fri, May 02, 2014 at 09:38:11AM +0100, Chris Wilson wrote: > > > > > On Fri, May 02, 2014 at 11:19:27AM +0300, Ville Syrj=E4l=E4 wrote: > > > > > > On Thu, May 01, 2014 at 06:47:54PM -0700, Ben Widawsky wrote: > > > > > > > "Restriction : > > > > > > > The offset must be greater than 4K bytes, avoiding the first = 4KB of > > > > > > > stolen memory." > > > > > > = > > > > > > Isn't this a more generic issue that we must avoid the first 4k= ? If so > > > > > > I think we should just reserve the first 4k permanently at driv= er init > > > > > > time. > > > = > > > Is anyone opposed to this plan? Realistically it won't make a > > > difference. > > > = > > > > > = > > > > > What? On many machines the vga framebuffer is allocated from offs= et 0. I > > > > > think some explanation is in order. > > > = > > > The chopped off part of the commit message explained it (if I underst= ood > > > your point). > > = > > How do we handle the inherited fb if it starts at offset 0? > > -Chris > > = > = > I must be missing something important. The FBC buffer is the only one > requiring a non-zero offset from the base of stolen memory. Nothing important can be placed there since the CS apparently writes there without anyone explicitly telling it to do so. That's what I gathered from the hsd anyway. I don't have a real answer for the inherited config thing. Should we just not inherit in that case? One would hope that the BIOS doesn't put the FB at offset 0, but this being the BIOS I'm pretty sure it does. I guess we could always make a copy and flip, but it would be nice if we didn't have to. Or maybe just copy the first page somewhere else and set up the PTE to compensate? Though that might violate some assumption we have about stolen being always contiguous... On a related note our FB takeover code is anywya rather optimistic since it blindly assumes that the ggtt offset matches the stolen offet. We never actually look at the PTEs to confirm that. -- = Ville Syrj=E4l=E4 Intel OTC