From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40552) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmNi4-00022e-11 for qemu-devel@nongnu.org; Mon, 19 May 2014 09:34:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WmNhu-0001L4-Nk for qemu-devel@nongnu.org; Mon, 19 May 2014 09:34:31 -0400 Received: from userp1040.oracle.com ([156.151.31.81]:49622) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmNhu-0001Ka-Hc for qemu-devel@nongnu.org; Mon, 19 May 2014 09:34:22 -0400 Date: Mon, 19 May 2014 09:34:00 -0400 From: Konrad Rzeszutek Wilk Message-ID: <20140519133400.GA3152@phenom.dumpdata.com> References: <1400237624-8505-1-git-send-email-tiejun.chen@intel.com> <1400237624-8505-7-git-send-email-tiejun.chen@intel.com> <20140516143511.GE3154@phenom.dumpdata.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [Xen-devel] [v2][PATCH 6/8] xen, gfx passthrough: support Intel IGD passthrough with VT-D List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Zhang, Yang Z" Cc: "peter.maydell@linaro.org" , "xen-devel@lists.xensource.com" , "mst@redhat.com" , "Kay, Allen M" , "stefano.stabellini@eu.citrix.com" , "weidong.han@intel.com" , "Kelly.Zytaruk@amd.com" , "jean.guyader@eu.citrix.com" , "qemu-devel@nongnu.org" , "anthony@codemonkey.ws" , "anthony.perard@citrix.com" , "Chen, Tiejun" On Mon, May 19, 2014 at 12:58:50AM +0000, Zhang, Yang Z wrote: > Konrad Rzeszutek Wilk wrote on 2014-05-16: > > On Fri, May 16, 2014 at 06:53:42PM +0800, Tiejun Chen wrote: > > > Some registers of Intel IGD are mapped in host bridge, so it needs to > > > passthrough these registers of physical host bridge to guest because > > > emulated host bridge in guest doesn't have these mappings. > > Thanks for your review for the whole series patch. Sure thing! .. snip.. > > > +write_default: > > > + pci_default_write_config(pci_dev, config_addr, val, len); > > > > > > and we just allow it through. But what happens if the guest decides to change > > the BAR sizes? Or fiddle with the GTT? > > > > Ouch. That really looks dangerous - or maybe I am too paranoid? > > > > I do not quite understand your concern. We only pass through PAVPC to physical host bridge. The others are handled by current logic. We don't change any of it. So what problem will be exposed by this patch? Ah, I assumed that pci_default_write_config would be writting everything without any checks. But it looks to be doing the right thing and just sets the emulated values. Could we just add comment saying that it writes to the emulated values? That way it won't trip folks. > > Best regards, > Yang > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Konrad Rzeszutek Wilk Subject: Re: [Xen-devel] [v2][PATCH 6/8] xen, gfx passthrough: support Intel IGD passthrough with VT-D Date: Mon, 19 May 2014 09:34:00 -0400 Message-ID: <20140519133400.GA3152@phenom.dumpdata.com> References: <1400237624-8505-1-git-send-email-tiejun.chen@intel.com> <1400237624-8505-7-git-send-email-tiejun.chen@intel.com> <20140516143511.GE3154@phenom.dumpdata.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org Sender: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org To: "Zhang, Yang Z" Cc: "peter.maydell@linaro.org" , "xen-devel@lists.xensource.com" , "mst@redhat.com" , "Kay, Allen M" , "stefano.stabellini@eu.citrix.com" , "weidong.han@intel.com" , "Kelly.Zytaruk@amd.com" , "jean.guyader@eu.citrix.com" , "qemu-devel@nongnu.org" , "anthony@codemonkey.ws" , "anthony.perard@citrix.com" , "Chen, Tiejun" List-Id: xen-devel@lists.xenproject.org On Mon, May 19, 2014 at 12:58:50AM +0000, Zhang, Yang Z wrote: > Konrad Rzeszutek Wilk wrote on 2014-05-16: > > On Fri, May 16, 2014 at 06:53:42PM +0800, Tiejun Chen wrote: > > > Some registers of Intel IGD are mapped in host bridge, so it needs to > > > passthrough these registers of physical host bridge to guest because > > > emulated host bridge in guest doesn't have these mappings. > > Thanks for your review for the whole series patch. Sure thing! .. snip.. > > > +write_default: > > > + pci_default_write_config(pci_dev, config_addr, val, len); > > > > > > and we just allow it through. But what happens if the guest decides to change > > the BAR sizes? Or fiddle with the GTT? > > > > Ouch. That really looks dangerous - or maybe I am too paranoid? > > > > I do not quite understand your concern. We only pass through PAVPC to physical host bridge. The others are handled by current logic. We don't change any of it. So what problem will be exposed by this patch? Ah, I assumed that pci_default_write_config would be writting everything without any checks. But it looks to be doing the right thing and just sets the emulated values. Could we just add comment saying that it writes to the emulated values? That way it won't trip folks. > > Best regards, > Yang > >