From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v2 49/71] drm/i915/chv: Add CHV display support Date: Tue, 20 May 2014 15:22:46 +0200 Message-ID: <20140520132246.GU8790@phenom.ffwll.local> References: <877g6x160g.fsf@intel.com> <1398682842-8114-1-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f53.google.com (mail-ee0-f53.google.com [74.125.83.53]) by gabe.freedesktop.org (Postfix) with ESMTP id E9CE36E7F4 for ; Tue, 20 May 2014 06:22:50 -0700 (PDT) Received: by mail-ee0-f53.google.com with SMTP id c13so587243eek.12 for ; Tue, 20 May 2014 06:22:50 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1398682842-8114-1-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 28, 2014 at 02:00:42PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Rafael Barbalho > = > Add support for the third pipe in cherrview > = > v2: Don't use spaces for indentation (Jani) > Wrap long lines > = > Reviewed-by: Imre Deak > Signed-off-by: Rafael Barbalho > [vsyrjala: slightly massaged the patch] > Signed-off-by: Ville Syrj=E4l=E4 Queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/i915_drv.c | 12 ++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++--- > 2 files changed, 20 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_= drv.c > index 3f57237..0fd3046 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -49,6 +49,17 @@ static struct drm_driver driver; > .dpll_md_offsets =3D { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \ > .palette_offsets =3D { PALETTE_A_OFFSET, PALETTE_B_OFFSET } > = > +#define GEN_CHV_PIPEOFFSETS \ > + .pipe_offsets =3D { PIPE_A_OFFSET, PIPE_B_OFFSET, \ > + CHV_PIPE_C_OFFSET }, \ > + .trans_offsets =3D { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ > + CHV_TRANSCODER_C_OFFSET, }, \ > + .dpll_offsets =3D { DPLL_A_OFFSET, DPLL_B_OFFSET, \ > + CHV_DPLL_C_OFFSET }, \ > + .dpll_md_offsets =3D { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \ > + CHV_DPLL_C_MD_OFFSET }, \ > + .palette_offsets =3D { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ > + CHV_PALETTE_C_OFFSET } > = > static const struct intel_device_info intel_i830_info =3D { > .gen =3D 2, .is_mobile =3D 1, .cursor_needs_physical =3D 1, .num_pipes = =3D 2, > @@ -286,6 +297,7 @@ static const struct intel_device_info intel_cherryvie= w_info =3D { > .ring_mask =3D RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > .is_valleyview =3D 1, > .display_mmio_offset =3D VLV_DISPLAY_BASE, > + GEN_CHV_PIPEOFFSETS, > }; > = > /* > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 74ac1c2..9138eff 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1440,6 +1440,7 @@ enum punit_power_well { > */ > #define DPLL_A_OFFSET 0x6014 > #define DPLL_B_OFFSET 0x6018 > +#define CHV_DPLL_C_OFFSET 0x6030 > #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \ > dev_priv->info.display_mmio_offset) > = > @@ -1531,6 +1532,7 @@ enum punit_power_well { > = > #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */ > #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */ > +#define CHV_DPLL_C_MD_OFFSET 0x603c > #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \ > dev_priv->info.display_mmio_offset) > = > @@ -1727,6 +1729,7 @@ enum punit_power_well { > */ > #define PALETTE_A_OFFSET 0xa000 > #define PALETTE_B_OFFSET 0xa800 > +#define CHV_PALETTE_C_OFFSET 0xc000 > #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ > dev_priv->info.display_mmio_offset) > = > @@ -2216,6 +2219,7 @@ enum punit_power_well { > #define TRANSCODER_A_OFFSET 0x60000 > #define TRANSCODER_B_OFFSET 0x61000 > #define TRANSCODER_C_OFFSET 0x62000 > +#define CHV_TRANSCODER_C_OFFSET 0x63000 > #define TRANSCODER_EDP_OFFSET 0x6f000 > = > #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ > @@ -3543,9 +3547,10 @@ enum punit_power_well { > #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 > #define PIPESTAT_INT_STATUS_MASK 0x0000ffff > = > -#define PIPE_A_OFFSET 0x70000 > -#define PIPE_B_OFFSET 0x71000 > -#define PIPE_C_OFFSET 0x72000 > +#define PIPE_A_OFFSET 0x70000 > +#define PIPE_B_OFFSET 0x71000 > +#define PIPE_C_OFFSET 0x72000 > +#define CHV_PIPE_C_OFFSET 0x74000 > /* > * There's actually no pipe EDP. Some pipe registers have > * simply shifted from the pipe to the transcoder, while > -- = > 1.8.3.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch