From: Greg Kurz <gkurz@linux.vnet.ibm.com>
To: Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: Tom Musta <tommusta@gmail.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class
Date: Tue, 3 Jun 2014 17:40:57 +0200 [thread overview]
Message-ID: <20140603174057.38316acb@bahia.local> (raw)
In-Reply-To: <1401787684-31895-3-git-send-email-aik@ozlabs.ru>
On Tue, 3 Jun 2014 19:27:37 +1000
Alexey Kardashevskiy <aik@ozlabs.ru> wrote:
> The differences between classes were:
> 1. SLB size, was 32 for 970 and 64 for others, should be 64 for all;
> 2. check_pow() callback, HID0 format is the same so should be the same
> 0x01C00000 which means "deep nap", "doze" and "nap" bits set;
> 3. LPCR - 970 does not have it but 970MP had one (by mistake).
>
> This fixes wrong differences and makes one 970 class.
>
> This fixes wrong registration of LPCR which is not present on 970.
>
> This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to
> 970 class as we do not emulate hypervisor in QEMU anyway.
>
> This does not remove check_pow_970FX now as it is still used by POWER5+
> class, this will be addressed later.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu-models.c | 14 +--
> target-ppc/translate_init.c | 222 ++++----------------------------------------
> 2 files changed, 23 insertions(+), 213 deletions(-)
>
> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
> index 9a66c03..97a81d8 100644
> --- a/target-ppc/cpu-models.c
> +++ b/target-ppc/cpu-models.c
> @@ -1142,19 +1142,19 @@
> "POWER8 v1.0")
> POWERPC_DEF("970", CPU_POWERPC_970, 970,
> "PowerPC 970")
> - POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX,
> + POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970,
> "PowerPC 970FX v1.0 (G5)")
> - POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX,
> + POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970,
> "PowerPC 970FX v2.0 (G5)")
> - POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX,
> + POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970,
> "PowerPC 970FX v2.1 (G5)")
> - POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX,
> + POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970,
> "PowerPC 970FX v3.0 (G5)")
> - POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX,
> + POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970,
> "PowerPC 970FX v3.1 (G5)")
> - POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP,
> + POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970,
> "PowerPC 970MP v1.0")
> - POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP,
> + POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970,
> "PowerPC 970MP v1.1")
> #if defined(TODO)
> POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970,
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index fa137af..2f40d0d 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7268,8 +7268,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
>
> static int check_pow_970 (CPUPPCState *env)
> {
> - if (env->spr[SPR_HID0] & 0x00600000)
> + if (env->spr[SPR_HID0] & 0x01C00000) {
What about killing magic numbers with something like:
#define HID0_DEEPNAP (1<<24)
#define HID0_DOZE (1<<23)
#define HID0_NAP (1<<22)
> return 1;
> + }
>
> return 0;
> }
> @@ -7303,8 +7304,21 @@ static void init_proc_970 (CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_hior, &spr_write_hior,
> 0x00000000);
> +
> + spr_register(env, SPR_CTRL, "SPR_CTRL",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_UCTRL, "SPR_UCTRL",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> #if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 32;
> + env->slb_nr = 64;
> #endif
> init_excp_970(env);
> env->dcache_line_size = 128;
> @@ -7334,7 +7348,6 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
> PPC_64B | PPC_ALTIVEC |
> PPC_SEGMENT_64B | PPC_SLBI;
> pcc->msr_mask = (1ull << MSR_SF) |
> - (1ull << MSR_SHV) |
> (1ull << MSR_VR) |
> (1ull << MSR_POW) |
> (1ull << MSR_EE) |
> @@ -7371,209 +7384,6 @@ static int check_pow_970FX (CPUPPCState *env)
> return 0;
> }
>
> -static void init_proc_970FX (CPUPPCState *env)
> -{
> - gen_spr_ne_601(env);
> - gen_spr_7xx(env);
> - /* Time base */
> - gen_tbl(env);
> - /* Hardware implementation registers */
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID0, "HID0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_clear,
> - 0x60000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID1, "HID1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_970_HID5, "HID5",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - POWERPC970_HID5_INIT);
> - /* Memory management */
> - /* XXX: not correct */
> - gen_low_BATs(env);
> - spr_register(env, SPR_HIOR, "SPR_HIOR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_hior, &spr_write_hior,
> - 0x00000000);
> - spr_register(env, SPR_CTRL, "SPR_CTRL",
> - SPR_NOACCESS, SPR_NOACCESS,
> - SPR_NOACCESS, &spr_write_generic,
> - 0x00000000);
> - spr_register(env, SPR_UCTRL, "SPR_UCTRL",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, SPR_NOACCESS,
> - 0x00000000);
> - spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
> - &spr_read_generic, &spr_write_generic,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -#if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 64;
> -#endif
> - init_excp_970(env);
> - env->dcache_line_size = 128;
> - env->icache_line_size = 128;
> - /* Allocate hardware IRQ controller */
> - ppc970_irq_init(env);
> - /* Can't find information on what this should be on reset. This
> - * value is the one used by 74xx processors. */
> - vscr_init(env, 0x00010000);
> -}
> -
> -POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> -
> - dc->desc = "PowerPC 970FX (aka G5)";
> - pcc->init_proc = init_proc_970FX;
> - pcc->check_pow = check_pow_970FX;
> - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
> - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> - PPC_FLOAT_STFIWX |
> - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> - PPC_MEM_SYNC | PPC_MEM_EIEIO |
> - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> - PPC_64B | PPC_ALTIVEC |
> - PPC_SEGMENT_64B | PPC_SLBI;
> - pcc->msr_mask = (1ull << MSR_SF) |
> - (1ull << MSR_VR) |
> - (1ull << MSR_POW) |
> - (1ull << MSR_EE) |
> - (1ull << MSR_PR) |
> - (1ull << MSR_FP) |
> - (1ull << MSR_ME) |
> - (1ull << MSR_FE0) |
> - (1ull << MSR_SE) |
> - (1ull << MSR_DE) |
> - (1ull << MSR_FE1) |
> - (1ull << MSR_IR) |
> - (1ull << MSR_DR) |
> - (1ull << MSR_PMM) |
> - (1ull << MSR_RI);
> - pcc->mmu_model = POWERPC_MMU_64B;
> -#if defined(CONFIG_SOFTMMU)
> - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> -#endif
> - pcc->excp_model = POWERPC_EXCP_970;
> - pcc->bus_model = PPC_FLAGS_INPUT_970;
> - pcc->bfd_mach = bfd_mach_ppc64;
> - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> - POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> - POWERPC_FLAG_BUS_CLK;
> - pcc->l1_dcache_size = 0x8000;
> - pcc->l1_icache_size = 0x10000;
> -}
> -
> -static int check_pow_970MP (CPUPPCState *env)
> -{
> - if (env->spr[SPR_HID0] & 0x01C00000)
> - return 1;
> -
> - return 0;
> -}
> -
> -static void init_proc_970MP (CPUPPCState *env)
> -{
> - gen_spr_ne_601(env);
> - gen_spr_7xx(env);
> - /* Time base */
> - gen_tbl(env);
> - /* Hardware implementation registers */
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID0, "HID0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_clear,
> - 0x60000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID1, "HID1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_970_HID5, "HID5",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - POWERPC970_HID5_INIT);
> - /* XXX : not implemented */
> - /* Memory management */
> - /* XXX: not correct */
> - gen_low_BATs(env);
> - spr_register(env, SPR_HIOR, "SPR_HIOR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_hior, &spr_write_hior,
> - 0x00000000);
> - /* Logical partitionning */
> - spr_register_kvm(env, SPR_LPCR, "LPCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_LPCR, 0x00000000);
> -#if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 32;
> -#endif
> - init_excp_970(env);
> - env->dcache_line_size = 128;
> - env->icache_line_size = 128;
> - /* Allocate hardware IRQ controller */
> - ppc970_irq_init(env);
> - /* Can't find information on what this should be on reset. This
> - * value is the one used by 74xx processors. */
> - vscr_init(env, 0x00010000);
> -}
> -
> -POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> -
> - dc->desc = "PowerPC 970 MP";
> - pcc->init_proc = init_proc_970MP;
> - pcc->check_pow = check_pow_970MP;
> - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
> - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> - PPC_FLOAT_STFIWX |
> - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> - PPC_MEM_SYNC | PPC_MEM_EIEIO |
> - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> - PPC_64B | PPC_ALTIVEC |
> - PPC_SEGMENT_64B | PPC_SLBI;
> - pcc->msr_mask = (1ull << MSR_SF) |
> - (1ull << MSR_SHV) |
> - (1ull << MSR_VR) |
> - (1ull << MSR_POW) |
> - (1ull << MSR_EE) |
> - (1ull << MSR_PR) |
> - (1ull << MSR_FP) |
> - (1ull << MSR_ME) |
> - (1ull << MSR_FE0) |
> - (1ull << MSR_SE) |
> - (1ull << MSR_DE) |
> - (1ull << MSR_FE1) |
> - (1ull << MSR_IR) |
> - (1ull << MSR_DR) |
> - (1ull << MSR_PMM) |
> - (1ull << MSR_RI);
> - pcc->mmu_model = POWERPC_MMU_64B;
> -#if defined(CONFIG_SOFTMMU)
> - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> -#endif
> - pcc->excp_model = POWERPC_EXCP_970;
> - pcc->bus_model = PPC_FLAGS_INPUT_970;
> - pcc->bfd_mach = bfd_mach_ppc64;
> - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> - POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> - POWERPC_FLAG_BUS_CLK;
> - pcc->l1_dcache_size = 0x8000;
> - pcc->l1_icache_size = 0x10000;
> -}
> -
> static void init_proc_power5plus(CPUPPCState *env)
> {
> gen_spr_ne_601(env);
--
Gregory Kurz kurzgreg@fr.ibm.com
gkurz@linux.vnet.ibm.com
Software Engineer @ IBM/Meiosys http://www.ibm.com
Tel +33 (0)562 165 496
"Anarchy is about taking complete responsibility for yourself."
Alan Moore.
next prev parent reply other threads:[~2014-06-03 15:41 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 01/29] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs Alexey Kardashevskiy
2014-06-03 16:32 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class Alexey Kardashevskiy
2014-06-03 15:40 ` Greg Kurz [this message]
2014-06-03 16:11 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-06-03 16:25 ` [Qemu-devel] " Tom Musta
2014-06-04 4:48 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 03/29] target-ppc: Refactor PPC970 Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970 Alexey Kardashevskiy
2014-06-03 16:32 ` Tom Musta
2014-06-04 5:09 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers Alexey Kardashevskiy
2014-06-03 16:35 ` Tom Musta
2014-06-04 1:36 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family Alexey Kardashevskiy
2014-06-03 16:36 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class Alexey Kardashevskiy
2014-06-03 16:37 ` Tom Musta
2014-06-03 16:42 ` Tom Musta
2014-06-04 5:25 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 08/29] target-ppc: Add HID4 SPR for PPC970 Alexey Kardashevskiy
2014-06-03 16:43 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 09/29] target-ppc: Introduce and reuse generalized init_proc_book3s_64() Alexey Kardashevskiy
2014-06-03 16:45 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 10/29] target-ppc: Remove check_pow_970FX Alexey Kardashevskiy
2014-06-03 16:45 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration Alexey Kardashevskiy
2014-06-03 16:47 ` Tom Musta
2014-06-04 1:46 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 12/29] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers Alexey Kardashevskiy
2014-06-03 16:48 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper Alexey Kardashevskiy
2014-06-03 16:48 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 14/29] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers Alexey Kardashevskiy
2014-06-03 16:54 ` Tom Musta
2014-06-04 2:02 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8 Alexey Kardashevskiy
2014-06-03 16:54 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() " Alexey Kardashevskiy
2014-06-03 16:54 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs Alexey Kardashevskiy
2014-06-03 16:55 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8 Alexey Kardashevskiy
2014-06-03 16:57 ` Tom Musta
2014-06-04 2:09 ` Alexey Kardashevskiy
2014-06-04 12:24 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR Alexey Kardashevskiy
2014-06-03 16:59 ` Tom Musta
2014-06-04 2:14 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 20/29] target-ppc: Add POWER8's FSCR SPR Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR Alexey Kardashevskiy
2014-06-03 17:08 ` Tom Musta
2014-06-04 2:37 ` Alexey Kardashevskiy
2014-06-04 12:25 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs Alexey Kardashevskiy
2014-06-03 17:10 ` Tom Musta
2014-06-03 23:42 ` Alexey Kardashevskiy
2014-06-04 5:26 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs Alexey Kardashevskiy
2014-06-03 17:58 ` Tom Musta
2014-06-04 2:54 ` Alexey Kardashevskiy
2014-06-04 12:30 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 24/29] KVM: target-ppc: Enable TM state migration Alexey Kardashevskiy
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 25/29] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs Alexey Kardashevskiy
2014-06-03 18:01 ` Tom Musta
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 26/29] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7 Alexey Kardashevskiy
2014-06-03 18:05 ` Tom Musta
2014-06-04 3:12 ` Alexey Kardashevskiy
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 28/29] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
2014-06-03 16:51 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2014-06-03 23:44 ` Alexey Kardashevskiy
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