From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/chv: WaDisablePwrmtrEvent:chv on CHV only Date: Tue, 10 Jun 2014 20:16:28 +0300 Message-ID: <20140610171628.GF27580@intel.com> References: <1402333609-5782-1-git-send-email-Tom.O'Rourke@intel.com> <20140609173238.GA27756@strange.amr.corp.intel.com> <87k38ou6hd.fsf@intel.com> <87ha3su6bp.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id A6B8A6E704 for ; Tue, 10 Jun 2014 10:18:19 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87ha3su6bp.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jun 10, 2014 at 06:34:18PM +0300, Jani Nikula wrote: > On Tue, 10 Jun 2014, Jani Nikula wrote: > > On Mon, 09 Jun 2014, Damien Lespiau wrote: > >> On Mon, Jun 09, 2014 at 10:06:49AM -0700, Tom.O'Rourke@intel.com wrote: > >>> From: Tom O'Rourke > >>> = > >>> In gen8_enable_rps, don't write CHV registers unless IS_CHERRYVIEW. > >>> = > >>> Signed-off-by: Tom O'Rourke > >> > >> A lovely catch. > > > > Sadly gen8_enable_rps does not get called on chv, so the fix is wrong. > = > To elaborate, I think we need a patch dropping the wa altogether (which > we can queue for 3.15 through stable because the change affects > broadwell) and another patch, if needed, adding the wa in the chv > specific function. This is just a merge mishap in one the chv patches. Someone just needs to send a patch that moves the misapplied stuff to the appropriate chv function. -- = Ville Syrj=E4l=E4 Intel OTC