From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Force full PSR setup during crtc enable. Date: Wed, 11 Jun 2014 11:42:27 +0200 Message-ID: <20140611094226.GE5821@phenom.ffwll.local> References: <20140610152457.GY5821@phenom.ffwll.local> <1402397397-914-1-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 085216E2F2 for ; Wed, 11 Jun 2014 02:42:32 -0700 (PDT) Received: by mail-wi0-f171.google.com with SMTP id n15so4688519wiw.16 for ; Wed, 11 Jun 2014 02:42:32 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1402397397-914-1-git-send-email-rodrigo.vivi@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Rodrigo Vivi Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, Joe Konno , Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Tue, Jun 10, 2014 at 03:49:57AM -0700, Rodrigo Vivi wrote: > Some registers set during setup might not be persistent after suspend/resume, > and also on crtc off/on cycles. > > This was causing bugs for some people that was unable to get PSR entry state > after suspend/resume cycle. > > v2: Adding some comments and better commit message explaining why this is > needed. (by Paulo) > v3: Moving psr.setup_done reset to crtc_enable because same issues might apply > also on crtc off/on cycle. (by Daniel) > > Cc: Paulo Zanoni > Cc: Daniel Vetter > Cc: Joe Konno > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index b5cbb28..077ab0e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3938,6 +3938,10 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc) > > mutex_lock(&dev->struct_mutex); > intel_update_fbc(dev); > + /* Forcing a full init sequence here to make sure all > + * registers are properly set. Some might not be persistent after > + * crtc on/off cycle. */ > + dev_priv->psr.setup_done = false; > intel_edp_psr_update(dev); I think splitting edp_psr_update into a setup and an update function would be cleaner. We kinda should have the same for fbc I think. This should also help with the locking since at least for fbc the setup and the update don't really need to do the same tasks. For now I think you can just add a bool do_setup to edp_psr_update and drop the dev_priv->psr.setup_done boolean instead. -Daniel > mutex_unlock(&dev->struct_mutex); > } > -- > 1.9.3 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch