From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915/chv: WaDisablePwrmtrEvent:chv on CHV only Date: Thu, 12 Jun 2014 14:42:37 +0200 Message-ID: <20140612124237.GY5821@phenom.ffwll.local> References: <1402333609-5782-1-git-send-email-Tom.O'Rourke@intel.com> <20140609173238.GA27756@strange.amr.corp.intel.com> <87k38ou6hd.fsf@intel.com> <87ha3su6bp.fsf@intel.com> <20140610171628.GF27580@intel.com> <87tx7ssk6o.fsf@intel.com> <87zjhibeo3.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 59DEA6E4B2 for ; Thu, 12 Jun 2014 05:42:44 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id u56so1230945wes.36 for ; Thu, 12 Jun 2014 05:42:43 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87zjhibeo3.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jun 12, 2014 at 01:33:32PM +0300, Jani Nikula wrote: > On Tue, 10 Jun 2014, Jani Nikula wrote: > > On Tue, 10 Jun 2014, Ville Syrj=E4l=E4 = wrote: > >> On Tue, Jun 10, 2014 at 06:34:18PM +0300, Jani Nikula wrote: > >>> On Tue, 10 Jun 2014, Jani Nikula wrote: > >>> > On Mon, 09 Jun 2014, Damien Lespiau wrot= e: > >>> >> On Mon, Jun 09, 2014 at 10:06:49AM -0700, Tom.O'Rourke@intel.com w= rote: > >>> >>> From: Tom O'Rourke > >>> >>> = > >>> >>> In gen8_enable_rps, don't write CHV registers unless IS_CHERRYVIE= W. > >>> >>> = > >>> >>> Signed-off-by: Tom O'Rourke > >>> >> > >>> >> A lovely catch. > >>> > > >>> > Sadly gen8_enable_rps does not get called on chv, so the fix is wro= ng. > >>> = > >>> To elaborate, I think we need a patch dropping the wa altogether (whi= ch > >>> we can queue for 3.15 through stable because the change affects > >>> broadwell) and another patch, if needed, adding the wa in the chv > >>> specific function. > >> > >> This is just a merge mishap in one the chv patches. Someone just > >> needs to send a patch that moves the misapplied stuff to the > >> appropriate chv function. > > > > Right. So my first comment was correct, and my elaboration total > > bullcrap. This is not present in 3.15, but we've queued the screwup for > > 3.16. Thanks for the correction Ville. > = > Argh. I'm really confusing myself and others here. Please bear with me. > = > So we've added > = > commit e4443e459ccf43f2c139358400365fd6a839d40d > Author: Ville Syrj=E4l=E4 > Date: Wed Apr 9 13:28:41 2014 +0300 > = > drm/i915/chv: Add a bunch of pre production workarounds > = > which contains the chv specific w/a in bdw code. This is now going to > 3.16, and we need to fix this for 3.16 through > drm-intel-fixes. Effectively the hunk touching gen8_enable_rps() from > Tom's new patch [1]. Right? > = > However the new patch from Tom moves those bits to > cherryview_enable_rps(), which is only present since > = > commit 38807746fa2ce44b79957ff07813d10fcaf3d311 > Author: Deepak S > Date: Fri May 23 21:00:15 2014 +0530 > = > drm/i915/chv: Enable Render Standby (RC6) for Cherryview > = > and queued for 3.17. So we need another patch adding the bits to > cherryview_enable_rps() on top of drm-intel-next-queued, effectively the > second hunk from Tom's new patch. Right? > = > So Tom, please split your patch in two, one on top of drm-intel-fixes, > and another on top of drm-intel-next-queued, and I think we'll be fine. I've already merged Tom's patch to dinq since it's fully needed there. So I think we just need a new patch version for -fixes only and resolve the mess in a merge (shouldn't cause one). If we split the patch also for dinq then I need to rebase/merge again. I guess you could simply apply Tom's fix to -fixes and drop the unecessary hunk yourself. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch