From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37748) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxjXd-000698-I8 for qemu-devel@nongnu.org; Thu, 19 Jun 2014 17:06:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WxjXc-0003XP-99 for qemu-devel@nongnu.org; Thu, 19 Jun 2014 17:06:41 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:51175) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxjXc-0003Ue-3X for qemu-devel@nongnu.org; Thu, 19 Jun 2014 17:06:40 -0400 Date: Thu, 19 Jun 2014 23:06:28 +0200 From: Aurelien Jarno Message-ID: <20140619210628.GA13901@ohm.rr44.fr> References: <1402499992-64851-1-git-send-email-leon.alrae@imgtec.com> <1402499992-64851-2-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1402499992-64851-2-git-send-email-leon.alrae@imgtec.com> Subject: Re: [Qemu-devel] [PATCH v2 01/22] target-mips: define ISA_MIPS64R6 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, qemu-devel@nongnu.org, rth@twiddle.net On Wed, Jun 11, 2014 at 04:19:31PM +0100, Leon Alrae wrote: > Signed-off-by: Leon Alrae > --- > v2: > * move new CPU definition to a separate patch > --- > target-mips/mips-defs.h | 28 +++++++++++++++++++--------- > 1 files changed, 19 insertions(+), 9 deletions(-) > > diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h > index 9dfa516..6cb62b2 100644 > --- a/target-mips/mips-defs.h > +++ b/target-mips/mips-defs.h > @@ -30,17 +30,21 @@ > #define ISA_MIPS64 0x00000080 > #define ISA_MIPS64R2 0x00000100 > #define ISA_MIPS32R3 0x00000200 > -#define ISA_MIPS32R5 0x00000400 > +#define ISA_MIPS64R3 0x00000400 > +#define ISA_MIPS32R5 0x00000800 > +#define ISA_MIPS64R5 0x00001000 > +#define ISA_MIPS32R6 0x00002000 > +#define ISA_MIPS64R6 0x00004000 > > /* MIPS ASEs. */ > -#define ASE_MIPS16 0x00001000 > -#define ASE_MIPS3D 0x00002000 > -#define ASE_MDMX 0x00004000 > -#define ASE_DSP 0x00008000 > -#define ASE_DSPR2 0x00010000 > -#define ASE_MT 0x00020000 > -#define ASE_SMARTMIPS 0x00040000 > -#define ASE_MICROMIPS 0x00080000 > +#define ASE_MIPS16 0x00010000 > +#define ASE_MIPS3D 0x00020000 > +#define ASE_MDMX 0x00040000 > +#define ASE_DSP 0x00080000 > +#define ASE_DSPR2 0x00100000 > +#define ASE_MT 0x00200000 > +#define ASE_SMARTMIPS 0x00400000 > +#define ASE_MICROMIPS 0x00800000 > > /* Chip specific instructions. */ > #define INSN_LOONGSON2E 0x20000000 > @@ -68,9 +72,15 @@ > > /* MIPS Technologies "Release 3" */ > #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) > +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) > > /* MIPS Technologies "Release 5" */ > #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) > +#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) > + > +/* MIPS Technologies "Release 6" */ > +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) > +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) > > /* Strictly follow the architecture standard: > - Disallow "special" instruction handling for PMON/SPIM. Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net