From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43075) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxjri-0003Y5-T6 for qemu-devel@nongnu.org; Thu, 19 Jun 2014 17:27:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wxjrh-000227-ST for qemu-devel@nongnu.org; Thu, 19 Jun 2014 17:27:26 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:51820) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxjrh-00021C-NB for qemu-devel@nongnu.org; Thu, 19 Jun 2014 17:27:25 -0400 Date: Thu, 19 Jun 2014 23:27:23 +0200 From: Aurelien Jarno Message-ID: <20140619212723.GB14144@ohm.rr44.fr> References: <1402499992-64851-1-git-send-email-leon.alrae@imgtec.com> <1402499992-64851-19-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1402499992-64851-19-git-send-email-leon.alrae@imgtec.com> Subject: Re: [Qemu-devel] [PATCH v2 18/22] target-mips: do not allow Status.FR=0 mode in 64-bit FPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, qemu-devel@nongnu.org, rth@twiddle.net On Wed, Jun 11, 2014 at 04:19:48PM +0100, Leon Alrae wrote: > Status.FR bit must be ignored on write and read as 1 when an implementation of > Release 6 of the Architecture in which a 64-bit floating point unit is > implemented. > > Signed-off-by: Leon Alrae > --- > target-mips/translate.c | 7 +++++++ > 1 files changed, 7 insertions(+), 0 deletions(-) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 4c75006..e635999 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -17899,6 +17899,13 @@ void cpu_state_reset(CPUMIPSState *env) > } > } > #endif > + if ((env->insn_flags & ISA_MIPS32R6) && > + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { > + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ > + env->CP0_Status |= (1 << CP0St_FR); This is fine > + env->CP0_Status_rw_bitmask &= ~(1 << CP0St_FR); IMHO This should be done directly in the CPU definition. > + } > + > compute_hflags(env); > cs->exception_index = EXCP_NONE; > } > -- > 1.7.5.4 > > -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net