From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxkfB-00034o-Aj for qemu-devel@nongnu.org; Thu, 19 Jun 2014 18:18:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WxkfA-0001la-64 for qemu-devel@nongnu.org; Thu, 19 Jun 2014 18:18:33 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:53393) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxkfA-0001lU-05 for qemu-devel@nongnu.org; Thu, 19 Jun 2014 18:18:32 -0400 Date: Fri, 20 Jun 2014 00:18:30 +0200 From: Aurelien Jarno Message-ID: <20140619221830.GA14303@ohm.rr44.fr> References: <1402499992-64851-1-git-send-email-leon.alrae@imgtec.com> <1402499992-64851-22-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1402499992-64851-22-git-send-email-leon.alrae@imgtec.com> Subject: Re: [Qemu-devel] [PATCH v2 21/22] target-mips: use pointers referring to appropriate decoding function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, qemu-devel@nongnu.org, rth@twiddle.net On Wed, Jun 11, 2014 at 04:19:51PM +0100, Leon Alrae wrote: > After selecting CPU in QEMU the base ISA will not change. Therefore > introducing *_arch function pointers that are set in cpu_state_reset to > point at the appropriate SPECIAL and SPECIAL3 decoding functions, and avoid > unnecessary 'if' statements. > > Signed-off-by: Leon Alrae > --- > target-mips/translate.c | 32 +++++++++++++++++++++----------- > 1 files changed, 21 insertions(+), 11 deletions(-) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index de35b77..7ff7829 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -15634,6 +15634,13 @@ out: > tcg_temp_free(t1); > } > > +/* Some instructions from MIPS32R6 and pre-MIPS32R6 have identical encoding. > + > + decode_opc_*_arch are pointing at the appropriate decoding functions > + depending on a base ISA supported by selected MIPS CPU. */ > +static void (*decode_opc_special_arch) (CPUMIPSState*, DisasContext*); > +static void (*decode_opc_special3_arch) (CPUMIPSState*, DisasContext*); > + > static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) > { > int rs, rt, rd, sa; > @@ -16002,11 +16009,8 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) > break; > #endif > default: > - if (ctx->insn_flags & ISA_MIPS32R6) { > - decode_opc_special_r6(env, ctx); > - } else { > - decode_opc_special_legacy(env, ctx); > - } > + decode_opc_special_arch(env, ctx); > + break; > } > } > > @@ -16799,12 +16803,9 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) > tcg_temp_free(t0); > } > break; > - default: /* Invalid */ > - if (ctx->insn_flags & ISA_MIPS32R6) { > - decode_opc_special3_r6(env, ctx); > - } else { > - decode_opc_special3_legacy(env, ctx); > - } > + default: > + decode_opc_special3_arch(env, ctx); > + break; > } > } > > @@ -17831,6 +17832,15 @@ void cpu_state_reset(CPUMIPSState *env) > env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; > env->insn_flags = env->cpu_model->insn_flags; > > + /* Select decoding functions appropriate for supported ISA */ > + if (env->insn_flags & ISA_MIPS32R6) { > + decode_opc_special_arch = decode_opc_special_r6; > + decode_opc_special3_arch = decode_opc_special3_r6; > + } else { > + decode_opc_special_arch = decode_opc_special_legacy; > + decode_opc_special3_arch = decode_opc_special3_legacy; > + } > + > #if defined(CONFIG_USER_ONLY) > env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); > # ifdef TARGET_MIPS64 I have mixed filling about that. While it clearly makes the code more readable, I am not sure it would be any faster given that it might kill branch prediction. Any opinion from others? -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net