From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [RFC 05/44] drm/i915: Updating assorted register
 and status page definitions
Date: Wed, 2 Jul 2014 10:49:44 -0700
Message-ID: <20140702104944.27a27637@jbarnes-desktop>
References: <1403803475-16337-1-git-send-email-John.C.Harrison@Intel.com>
 <1403803475-16337-6-git-send-email-John.C.Harrison@Intel.com>
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On Thu, 26 Jun 2014 18:23:56 +0100
John.C.Harrison@Intel.com wrote:

> + * Premption-related registers
> + */
> +#define RING_UHPTR(base)	((base)+0x134)
> +#define   UHPTR_GFX_ADDR_ALIGN		(0x7)
> +#define   UHPTR_VALID			(0x1)
> +#define RING_PREEMPT_ADDR	0x0214c
> +#define   PREEMPT_BATCH_LEVEL_MASK	(0x3)
> +#define BB_PREEMPT_ADDR		0x02148
> +#define SBB_PREEMPT_ADDR	0x0213c
> +#define RS_PREEMPT_STATUS	0x0215c

I couldn't find these easily, and the GFX_ADDR_ALIGN is just page
alignment right?  So you might not need that one.  But overall looks
fine.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center