From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 12/14] drm/i915: Turn on panel power before doing aux transfers Date: Tue, 19 Aug 2014 13:57:57 +0300 Message-ID: <20140819105757.GB4193@intel.com> References: <1408389369-22898-1-git-send-email-ville.syrjala@linux.intel.com> <1408389369-22898-13-git-send-email-ville.syrjala@linux.intel.com> <87wqa5gchw.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 080FF6E30C for ; Tue, 19 Aug 2014 03:58:00 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87wqa5gchw.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Aug 19, 2014 at 10:33:15AM +0300, Jani Nikula wrote: > On Mon, 18 Aug 2014, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj=E4l=E4 > > > > On VLV/CHV the panel power sequencer may need to be "kicked" a bit to > > lock onto the new port, and that needs to happen before any aux > > transfers are attempted if we want the aux transfers to actaully > > succeed. So turn on panel power (part of the "kick") before aux > > transfers (DPMS_ON + link training). > > > > This also matches the documented modeset sequence better for pch > > platforms. The documentation doesn't explicitly state anything about the > > DPMS or link training DPCD writes, but the panel power on step is > > always listed before link training is mentioned. > > > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_dp.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > > index 4952783..28bc652 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -2275,10 +2275,10 @@ static void intel_enable_dp(struct intel_encode= r *encoder) > > return; > > = > > intel_edp_panel_vdd_on(intel_dp); > > - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > > - intel_dp_start_link_train(intel_dp); > > intel_edp_panel_on(intel_dp); > > intel_edp_panel_vdd_off(intel_dp, true); > > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > > + intel_dp_start_link_train(intel_dp); > = > Please dig into the git history in this area. I fear this may > regress. We've juggled this too many times... I did. But I couldn't spot much solid analysis of the problems in the earlier patches/reverts. It's mostly been guesswork AFAICS. Most of it seems to be back and forth with the force vdd on/off vs. panel power on, but this patch doesn't change that order. Also: a) we need this patch on VLV/CHV at the very least b) this agrees with the bspec modeset sequence for pch platforms better c) my ILK with CPU eDP seems happy with the new order -- = Ville Syrj=E4l=E4 Intel OTC