From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Fri, 22 Aug 2014 21:41:46 +0200 Subject: [U-Boot] [PATCH 15/23] pci: tegra: Add Tegra PCIe driver In-Reply-To: <53F77EF3.6090903@wwwdotorg.org> References: <1408346196-30419-1-git-send-email-thierry.reding@gmail.com> <1408346196-30419-16-git-send-email-thierry.reding@gmail.com> <53F4F136.7010708@wwwdotorg.org> <53F77EF3.6090903@wwwdotorg.org> Message-ID: <20140822194145.GC31506@ulmo> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Fri, Aug 22, 2014 at 11:33:39AM -0600, Stephen Warren wrote: > On 08/20/2014 01:04 PM, Stephen Warren wrote: > >On 08/18/2014 01:16 AM, Thierry Reding wrote: > >>From: Thierry Reding > >> > >>Add support for the PCIe controller found on some generations of Tegra. > >>Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root > >>ports with a total of 6 lanes and Tegra124 has 2 root ports with a total > >>of 5 lanes. > > > >>diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c > > >>+static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) > >>+{ > >>+ unsigned int retries = 3; > >>+ unsigned long value; > >>+ > >>+ value = rp_readl(port, RP_PRIV_MISC); > >>+ value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; > >>+ value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; > >>+ rp_writel(port, value, RP_PRIV_MISC); > >>+ > >>+ do { > >>+ unsigned int timeout = 200; > >>+ > >>+ do { > >>+ value = rp_readl(port, RP_VEND_XP); > >>+ if (value & RP_VEND_XP_DL_UP) > >>+ break; > > > >On my board, this almost never succeeds for Jetson TK1's built-in NIC, > >although it works fine for the mini-PCIe slot. On the other two boards I > >borrowed, this succeeds almost always. I'd prefer if we could get to the > >bottom of this before we actually apply this, although the bug is > >proving quite perplexing. The mainline kernel PCIe patches have the same > >issue. > > I tracked the issue down to some missing pinmux configuration for the PCIe > reset lane. With that in place, both U-Boot and the mainline Linux kernel > PCIe support appear to work reliably. I'll work on patches to resolve that. Hey, that's great news. > So, I think we can go ahead and merge these patches without issue ASAP, as > soon as any review comments are addressed. Okay, I have v2 pretty much ready with all the review comments addressed and just need some time to write up a cover letter and send the series out. Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 819 bytes Desc: not available URL: