From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier Date: Tue, 26 Aug 2014 15:58:51 +0300 Message-ID: <20140826125851.GK4193@intel.com> References: <1408389369-22898-1-git-send-email-ville.syrjala@linux.intel.com> <1408389369-22898-3-git-send-email-ville.syrjala@linux.intel.com> <87egwdhsk8.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id F387A6E4E7 for ; Tue, 26 Aug 2014 06:01:03 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87egwdhsk8.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Aug 19, 2014 at 10:00:55AM +0300, Jani Nikula wrote: > On Mon, 18 Aug 2014, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj=E4l=E4 > > > > Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check > > and flatten the rest of the function. > = > Please imagine adding another platform there, and realize this just adds > unnecessary churn. I'd just add another reboot notifier then. Frankly I don't understand the current one either. Why does it need to set the delay to max for instance? And does this mean that the PANEL_POWER_RESET bit doesn't actually work as advertised in the docs? > = > BR, > Jani. > = > = > > > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++------------ > > 1 file changed, 12 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > > index 43dd226..a9ed2a6 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -347,22 +347,22 @@ static int edp_notify_handler(struct notifier_blo= ck *this, unsigned long code, > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > u32 pp_div; > > u32 pp_ctrl_reg, pp_div_reg; > > - enum pipe pipe =3D vlv_power_sequencer_pipe(intel_dp); > > + enum pipe pipe; > > = > > - if (!is_edp(intel_dp) || code !=3D SYS_RESTART) > > + if (!IS_VALLEYVIEW(dev) || !is_edp(intel_dp) || code !=3D SYS_RESTART) > > return 0; > > = > > - if (IS_VALLEYVIEW(dev)) { > > - pp_ctrl_reg =3D VLV_PIPE_PP_CONTROL(pipe); > > - pp_div_reg =3D VLV_PIPE_PP_DIVISOR(pipe); > > - pp_div =3D I915_READ(pp_div_reg); > > - pp_div &=3D PP_REFERENCE_DIVIDER_MASK; > > + pipe =3D vlv_power_sequencer_pipe(intel_dp); > > = > > - /* 0x1F write to PP_DIV_REG sets max cycle delay */ > > - I915_WRITE(pp_div_reg, pp_div | 0x1F); > > - I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); > > - msleep(intel_dp->panel_power_cycle_delay); > > - } > > + pp_ctrl_reg =3D VLV_PIPE_PP_CONTROL(pipe); > > + pp_div_reg =3D VLV_PIPE_PP_DIVISOR(pipe); > > + pp_div =3D I915_READ(pp_div_reg); > > + pp_div &=3D PP_REFERENCE_DIVIDER_MASK; > > + > > + /* 0x1F write to PP_DIV_REG sets max cycle delay */ > > + I915_WRITE(pp_div_reg, pp_div | 0x1F); > > + I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); > > + msleep(intel_dp->panel_power_cycle_delay); > > = > > return 0; > > } > > -- = > > 1.8.5.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Jani Nikula, Intel Open Source Technology Center -- = Ville Syrj=E4l=E4 Intel OTC