From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH v2] drm/i915: Rework workaround init functions for BDW and CHV Date: Tue, 2 Sep 2014 10:49:31 +0100 Message-ID: <20140902094931.GI1118@strange.amr.corp.intel.com> References: <1409578133-2800-2-git-send-email-arun.siluvery@linux.intel.com> <1409649257-12114-1-git-send-email-arun.siluvery@linux.intel.com> <20140902094545.GH1118@strange.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id EB7916E041 for ; Tue, 2 Sep 2014 02:49:51 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140902094545.GH1118@strange.amr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Arun Siluvery Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Sep 02, 2014 at 10:45:45AM +0100, Damien Lespiau wrote: > There's one case when this won't work, when several WAs for a single > 'normal' register are defined. The read done here means only the last of > those W/As will end up being applied (because the last LRI to that > register will be the value that ends up in the register. We'll probably > need to coalesce all W/A defined for a single normal register into one > write. To more correct/clear, it's not the read that's the problem, in the case where a normal register has several W/A, the last write will override the previous ones. -- Damien