From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 669591A01DD for ; Thu, 4 Sep 2014 12:31:24 +1000 (EST) Received: from mail-qa0-x232.google.com (mail-qa0-x232.google.com [IPv6:2607:f8b0:400d:c00::232]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D1D6B1401F6 for ; Thu, 4 Sep 2014 12:31:23 +1000 (EST) Received: by mail-qa0-f50.google.com with SMTP id cm18so8609446qab.23 for ; Wed, 03 Sep 2014 19:31:21 -0700 (PDT) Date: Wed, 3 Sep 2014 22:31:18 -0400 From: Jerome Glisse To: Benjamin Herrenschmidt Subject: Re: TTM placement & caching issue/questions Message-ID: <20140904023117.GD4835@gmail.com> References: <1409789547.30640.136.camel@pasglop> <20140904015548.GB4835@gmail.com> <20140904020742.GC4835@gmail.com> <1409797523.25089.8.camel@pasglop> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="2B/JsCI69OhZNC5r" In-Reply-To: <1409797523.25089.8.camel@pasglop> Cc: Alex Deucher , linuxppc-dev@ozlabs.org, Michel =?iso-8859-1?Q?D=E4nzer?= , Christian Koenig , dri-devel@lists.freedesktop.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , --2B/JsCI69OhZNC5r Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit On Thu, Sep 04, 2014 at 12:25:23PM +1000, Benjamin Herrenschmidt wrote: > On Wed, 2014-09-03 at 22:07 -0400, Jerome Glisse wrote: > > > So in the meantime the attached patch should work, it just silently ignore > > the caching attribute request on non x86 instead of pretending that things > > are setup as expected and then latter the radeon ou nouveau hw unsetting > > the snoop bit. > > > > It's not tested but i think it should work. > > I'm still getting placements with !CACHED going from bo_memcpy in > ttm_io_prot() though ... I'm looking at filtering the placement > attributes instead. > > Ben. Ok so this one should do the trick. > > > > > > > Cheers, > > > Jérôme > > > > > > > > > > > Cheers, > > > > Ben. > > > > > > > > > > > > _______________________________________________ > > > > dri-devel mailing list > > > > dri-devel@lists.freedesktop.org > > > > http://lists.freedesktop.org/mailman/listinfo/dri-devel > > --2B/JsCI69OhZNC5r Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: attachment; filename="0001-drm-ttm-force-cached-mapping-on-non-x86-platform.patch" Content-Transfer-Encoding: 8bit >>From def7a056d042220f91016d0a7c245ba8e96f90ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= Date: Wed, 3 Sep 2014 22:04:34 -0400 Subject: [PATCH] drm/ttm: force cached mapping on non x86 platform. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit People interested in providing uncached or write combined mapping on there architecture need to do the ground work inside there arch specific code to allow to break the linear kernel mapping so that page mapping attributes can be updated, in the meantime force cached mapping for non x86 architecture. Signed-off-by: Jérôme Glisse --- drivers/gpu/drm/radeon/radeon_ttm.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- drivers/gpu/drm/ttm/ttm_tt.c | 47 ++++++++++++++++++++++++++++--------- include/drm/ttm/ttm_bo_driver.h | 2 +- 4 files changed, 39 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 72afe82..4dd5060 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -304,7 +304,7 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, return r; } - r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); + r = ttm_tt_set_placement_caching(bo->ttm, &tmp_mem.placement); if (unlikely(r)) { goto out_cleanup; } diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 3da89d5..4dc21c3 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -305,7 +305,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, goto out_err; } - ret = ttm_tt_set_placement_caching(bo->ttm, mem->placement); + ret = ttm_tt_set_placement_caching(bo->ttm, &mem->placement); if (ret) goto out_err; diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index bf080ab..7cbdb48 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -89,14 +89,6 @@ static inline int ttm_tt_set_page_caching(struct page *p, return ret; } -#else /* CONFIG_X86 */ -static inline int ttm_tt_set_page_caching(struct page *p, - enum ttm_caching_state c_old, - enum ttm_caching_state c_new) -{ - return 0; -} -#endif /* CONFIG_X86 */ /* * Change caching policy for the linear kernel map @@ -149,19 +141,52 @@ out_err: return ret; } -int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement) +int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t *placement) { enum ttm_caching_state state; - if (placement & TTM_PL_FLAG_WC) + if (*placement & TTM_PL_FLAG_WC) state = tt_wc; - else if (placement & TTM_PL_FLAG_UNCACHED) + else if (*placement & TTM_PL_FLAG_UNCACHED) state = tt_uncached; else state = tt_cached; return ttm_tt_set_caching(ttm, state); } +#else /* CONFIG_X86 */ +int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t *placement) +{ + if (placement & (TTM_PL_TT | TTM_PL_FLAG_SYSTEM)) { + ttm->caching_state = tt_cached; + } else { + if (placement & TTM_PL_FLAG_WC) + ttm->caching_state = tt_wc; + else if (placement & TTM_PL_FLAG_UNCACHED) + ttm->caching_state = tt_uncached; + else + ttm->caching_state = tt_cached; + } + /* + * Some architecture force cached so we need to reflect the + * new ttm->caching_state into the mem->placement flags. + */ + *placement &= ~TTM_PL_MASK_CACHING; + switch (bo->ttm->caching_state) { + case tt_wc: + *placement |= TTM_PL_FLAG_WC; + break; + case tt_uncached: + *placement |= TTM_PL_FLAG_UNCACHED; + break; + case tt_cached: + default: + *placement |= TTM_PL_FLAG_CACHED; + break; + } + return 0; +} +#endif /* CONFIG_X86 */ EXPORT_SYMBOL(ttm_tt_set_placement_caching); void ttm_tt_destroy(struct ttm_tt *ttm) diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index 1d9f0f1..cbc5ad2 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -669,7 +669,7 @@ extern int ttm_tt_swapin(struct ttm_tt *ttm); * hit RAM. This function may be very costly as it involves global TLB * and cache flushes and potential page splitting / combining. */ -extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement); +extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t *placement); extern int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage); -- 1.9.3 --2B/JsCI69OhZNC5r-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerome Glisse Subject: Re: TTM placement & caching issue/questions Date: Wed, 3 Sep 2014 22:31:18 -0400 Message-ID: <20140904023117.GD4835@gmail.com> References: <1409789547.30640.136.camel@pasglop> <20140904015548.GB4835@gmail.com> <20140904020742.GC4835@gmail.com> <1409797523.25089.8.camel@pasglop> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="2B/JsCI69OhZNC5r" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qg0-f45.google.com (mail-qg0-f45.google.com [209.85.192.45]) by gabe.freedesktop.org (Postfix) with ESMTP id 24D026E62C for ; Wed, 3 Sep 2014 19:31:22 -0700 (PDT) Received: by mail-qg0-f45.google.com with SMTP id e89so9319693qgf.18 for ; Wed, 03 Sep 2014 19:31:21 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1409797523.25089.8.camel@pasglop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Benjamin Herrenschmidt Cc: Alex Deucher , linuxppc-dev@ozlabs.org, Michel =?iso-8859-1?Q?D=E4nzer?= , Christian Koenig , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --2B/JsCI69OhZNC5r Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Sep 04, 2014 at 12:25:23PM +1000, Benjamin Herrenschmidt wrote: > On Wed, 2014-09-03 at 22:07 -0400, Jerome Glisse wrote: >=20 > > So in the meantime the attached patch should work, it just silently i= gnore > > the caching attribute request on non x86 instead of pretending that t= hings > > are setup as expected and then latter the radeon ou nouveau hw unsett= ing > > the snoop bit. > >=20 > > It's not tested but i think it should work. >=20 > I'm still getting placements with !CACHED going from bo_memcpy in > ttm_io_prot() though ... I'm looking at filtering the placement > attributes instead. >=20 > Ben. Ok so this one should do the trick. >=20 > > >=20 > > > Cheers, > > > J=E9r=F4me > > >=20 > > > >=20 > > > > Cheers, > > > > Ben. > > > >=20 > > > >=20 > > > > _______________________________________________ > > > > dri-devel mailing list > > > > dri-devel@lists.freedesktop.org > > > > http://lists.freedesktop.org/mailman/listinfo/dri-devel >=20 >=20 --2B/JsCI69OhZNC5r Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: attachment; filename="0001-drm-ttm-force-cached-mapping-on-non-x86-platform.patch" Content-Transfer-Encoding: quoted-printable >>From def7a056d042220f91016d0a7c245ba8e96f90ba Mon Sep 17 00:00:00 2001 From: =3D?UTF-8?q?J=3DC3=3DA9r=3DC3=3DB4me=3D20Glisse?=3D Date: Wed, 3 Sep 2014 22:04:34 -0400 Subject: [PATCH] drm/ttm: force cached mapping on non x86 platform. MIME-Version: 1.0 Content-Type: text/plain; charset=3DUTF-8 Content-Transfer-Encoding: 8bit People interested in providing uncached or write combined mapping on there architecture need to do the ground work inside there arch specific code to allow to break the linear kernel mapping so that page mapping attributes can be updated, in the meantime force cached mapping for non x86 architecture. Signed-off-by: J=E9r=F4me Glisse --- drivers/gpu/drm/radeon/radeon_ttm.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- drivers/gpu/drm/ttm/ttm_tt.c | 47 ++++++++++++++++++++++++++++---= ------ include/drm/ttm/ttm_bo_driver.h | 2 +- 4 files changed, 39 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon= /radeon_ttm.c index 72afe82..4dd5060 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -304,7 +304,7 @@ static int radeon_move_vram_ram(struct ttm_buffer_obj= ect *bo, return r; } =20 - r =3D ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); + r =3D ttm_tt_set_placement_caching(bo->ttm, &tmp_mem.placement); if (unlikely(r)) { goto out_cleanup; } diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 3da89d5..4dc21c3 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -305,7 +305,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_o= bject *bo, goto out_err; } =20 - ret =3D ttm_tt_set_placement_caching(bo->ttm, mem->placement); + ret =3D ttm_tt_set_placement_caching(bo->ttm, &mem->placement); if (ret) goto out_err; =20 diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index bf080ab..7cbdb48 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -89,14 +89,6 @@ static inline int ttm_tt_set_page_caching(struct page = *p, =20 return ret; } -#else /* CONFIG_X86 */ -static inline int ttm_tt_set_page_caching(struct page *p, - enum ttm_caching_state c_old, - enum ttm_caching_state c_new) -{ - return 0; -} -#endif /* CONFIG_X86 */ =20 /* * Change caching policy for the linear kernel map @@ -149,19 +141,52 @@ out_err: return ret; } =20 -int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement) +int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t *placement= ) { enum ttm_caching_state state; =20 - if (placement & TTM_PL_FLAG_WC) + if (*placement & TTM_PL_FLAG_WC) state =3D tt_wc; - else if (placement & TTM_PL_FLAG_UNCACHED) + else if (*placement & TTM_PL_FLAG_UNCACHED) state =3D tt_uncached; else state =3D tt_cached; =20 return ttm_tt_set_caching(ttm, state); } +#else /* CONFIG_X86 */ +int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t *placement= ) +{ + if (placement & (TTM_PL_TT | TTM_PL_FLAG_SYSTEM)) { + ttm->caching_state =3D tt_cached; + } else { + if (placement & TTM_PL_FLAG_WC) + ttm->caching_state =3D tt_wc; + else if (placement & TTM_PL_FLAG_UNCACHED) + ttm->caching_state =3D tt_uncached; + else + ttm->caching_state =3D tt_cached; + } + /* + * Some architecture force cached so we need to reflect the + * new ttm->caching_state into the mem->placement flags. + */ + *placement &=3D ~TTM_PL_MASK_CACHING; + switch (bo->ttm->caching_state) { + case tt_wc: + *placement |=3D TTM_PL_FLAG_WC; + break; + case tt_uncached: + *placement |=3D TTM_PL_FLAG_UNCACHED; + break; + case tt_cached: + default: + *placement |=3D TTM_PL_FLAG_CACHED; + break; + } + return 0; +} +#endif /* CONFIG_X86 */ EXPORT_SYMBOL(ttm_tt_set_placement_caching); =20 void ttm_tt_destroy(struct ttm_tt *ttm) diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_dri= ver.h index 1d9f0f1..cbc5ad2 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -669,7 +669,7 @@ extern int ttm_tt_swapin(struct ttm_tt *ttm); * hit RAM. This function may be very costly as it involves global TLB * and cache flushes and potential page splitting / combining. */ -extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t pla= cement); +extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t *pl= acement); extern int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage); =20 --=20 1.9.3 --2B/JsCI69OhZNC5r Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel --2B/JsCI69OhZNC5r--