From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC Date: Fri, 5 Sep 2014 08:35:25 +0800 Message-ID: <20140905003523.GD10809@dragon> References: <1409729805-9741-1-git-send-email-b20788@freescale.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Fabio Estevam Cc: "devicetree@vger.kernel.org" , Anson Huang , "linux-arm-kernel@lists.infradead.org" , Sascha Hauer List-Id: devicetree@vger.kernel.org On Thu, Sep 04, 2014 at 07:50:35PM -0300, Fabio Estevam wrote: > This patch series works fine if we use the new dtb and new kernel. > > However, booting a kernel with these series applied and using an old > dtb we get a system with broken timer. > > 'sleep 1' takes something like 20 seconds in this case. Oh, yes. It breaks the compatibility with existing DTB. Dropped the patches for now. Anson, We may need to query the clock rate and then decide how to set up those register bits? Shawn From mboxrd@z Thu Jan 1 00:00:00 1970 From: shawn.guo@freescale.com (Shawn Guo) Date: Fri, 5 Sep 2014 08:35:25 +0800 Subject: [PATCH 0/3] move gpt per clk parent for ipg_per to OSC In-Reply-To: References: <1409729805-9741-1-git-send-email-b20788@freescale.com> Message-ID: <20140905003523.GD10809@dragon> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Sep 04, 2014 at 07:50:35PM -0300, Fabio Estevam wrote: > This patch series works fine if we use the new dtb and new kernel. > > However, booting a kernel with these series applied and using an old > dtb we get a system with broken timer. > > 'sleep 1' takes something like 20 seconds in this case. Oh, yes. It breaks the compatibility with existing DTB. Dropped the patches for now. Anson, We may need to query the clock rate and then decide how to set up those register bits? Shawn