From mboxrd@z Thu Jan  1 00:00:00 1970
From: Damien Lespiau <damien.lespiau@intel.com>
Subject: Re: [PATCH 43/89] drm/i915/skl: Read the Memory Latency
 Values for WM computation
Date: Fri, 5 Sep 2014 09:29:33 +0100
Message-ID: <20140905082933.GE24533@strange.ger.corp.intel.com>
References: <1409830075-11139-1-git-send-email-damien.lespiau@intel.com>
 <1409830075-11139-44-git-send-email-damien.lespiau@intel.com>
 <20140905082530.GR4193@intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga14.intel.com (mga14.intel.com [192.55.52.115])
 by gabe.freedesktop.org (Postfix) with ESMTP id DE24B6E7E6
 for <intel-gfx@lists.freedesktop.org>; Fri,  5 Sep 2014 01:30:30 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20140905082530.GR4193@intel.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, Pradeep Bhat <pradeep.bhat@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Sep 05, 2014 at 11:25:30AM +0300, Ville Syrj=E4l=E4 wrote:
> > +/* SKL GT Driver Mailbox registers for reading memory latencies */
> > +#define GEN9_MAILBOX_DATA1		0x13812C
> > +#define   GEN9_MAILBOX_READ_MEM_LAT	(0x6)
> > +#define   GEN9_MAILBOX_READ_TIMEOUT	150
> =

> Timeout not used anywhere. Also spec says 100us.
> =

> > +#define   GEN9_MEM_LAT_LEVEL_MASK	0xFF
> > +#define   GEN9_MEM_LAT_LEVEL_1_5_SHIFT	8
> > +#define   GEN9_MEM_LAT_LEVEL_2_6_SHIFT	16
> > +#define   GEN9_MEM_LAT_LEVEL_3_7_SHIFT	24
> =

> This stuff should be grouped along the other pcode register defines.

Funny you mention this, I fixed those two in the v6 sent as reply
yesterday.

-- =

Damien