From: Chris Wilson <chris@chris-wilson.co.uk>
To: Keith Packard <keithp@keithp.com>
Cc: xorg-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 0/2 xf86-video-intel] Two DRI3/Present bug fixes for UXA
Date: Thu, 11 Sep 2014 07:37:16 +0100 [thread overview]
Message-ID: <20140911063716.GB28332@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <1410383349-27678-1-git-send-email-keithp@keithp.com>
On Wed, Sep 10, 2014 at 02:09:07PM -0700, Keith Packard wrote:
> [PATCH 2/2] Correct BO allocation alignment
>
> This patch makes UXA and Mesa agree about how buffers are allocated
> for images. Without this, UXA was requiring larger padding, which
> meant that converting some textures into pixmaps using DRI3 would
> fail.
That extra alignment is due to gen2 and early gen3 (if
(!intel->has_relaxed_fencing) covers them).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2014-09-11 6:37 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-10 21:09 [PATCH 0/2 xf86-video-intel] Two DRI3/Present bug fixes for UXA Keith Packard
[not found] ` <1410383349-27678-1-git-send-email-keithp-aN4HjG94KOLQT0dZR+AlfA@public.gmane.org>
2014-09-10 21:09 ` [PATCH 1/2] Do not clear pending kernel events on mode switch Keith Packard
2014-09-10 21:09 ` [PATCH 2/2] Correct BO allocation alignment Keith Packard
2014-09-11 6:37 ` Chris Wilson [this message]
[not found] ` <20140911063716.GB28332-aII6DKEyn0pWYbfKqPwjAkR8Iwp7RQ6xAL8bYrjMMd8@public.gmane.org>
2014-09-11 6:47 ` [Intel-gfx] [PATCH 0/2 xf86-video-intel] Two DRI3/Present bug fixes for UXA Jasper St. Pierre
2014-09-11 6:52 ` Chris Wilson
2014-09-11 19:53 ` [Intel-gfx] " Keith Packard
[not found] ` <86r3ziorwl.fsf-6d7jPg3SX/+z9DMzp4kqnw@public.gmane.org>
2014-09-13 8:28 ` Chris Wilson
[not found] ` <20140913082824.GM16043-aII6DKEyn0pWYbfKqPwjAkR8Iwp7RQ6xAL8bYrjMMd8@public.gmane.org>
2014-09-13 17:31 ` Keith Packard
2014-09-12 19:13 ` Kenneth Graunke
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