From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 0/2 xf86-video-intel] Two DRI3/Present bug fixes for UXA Date: Thu, 11 Sep 2014 07:52:09 +0100 Message-ID: <20140911065209.GD28332@nuc-i3427.alporthouse.com> References: <1410383349-27678-1-git-send-email-keithp@keithp.com> <20140911063716.GB28332@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Jasper St. Pierre" Cc: "X.Org Devel List" , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Sep 11, 2014 at 12:47:21AM -0600, Jasper St. Pierre wrote: > Why doesn't mesa allocate buffers in the same way for those chips, then? Good question. -Chris -- Chris Wilson, Intel Open Source Technology Centre