[PATCH v2 0/3] add basic rk3288 smp support

[PATCH v2 0/3] add basic rk3288 smp support

[Kever Yang]

rk3288 is qual-core CPU Soc, we need to enable the smp.
This patchset works with either arch-timer use the phisical counter
in kernel or the firmware initialize the arch-timer virtual counter
offset and use virtual counter in kernel.

Changes in v2:
- add documentation
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment

Kever Yang (3):
  Documentation: dt-bindings: add dt binding info for rk3288-smp
  ARM: rockchip: add basic smp support for rk3288
  ARM: dts: add intmem node for rk3288 smp support

 Documentation/devicetree/bindings/arm/cpus.txt |  1 +
 arch/arm/boot/dts/rk3288.dtsi                  | 18 ++++++++
 arch/arm/mach-rockchip/core.h                  |  1 +
 arch/arm/mach-rockchip/headsmp.S               | 14 ++++++
 arch/arm/mach-rockchip/platsmp.c               | 63 +++++++++++++++++++++++---
 5 files changed, 91 insertions(+), 6 deletions(-)

-- 
1.9.1

[PATCH v2 0/3] add basic rk3288 smp support

[Kever Yang]

rk3288 is qual-core CPU Soc, we need to enable the smp.
This patchset works with either arch-timer use the phisical counter
in kernel or the firmware initialize the arch-timer virtual counter
offset and use virtual counter in kernel.

Changes in v2:
- add documentation
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment

Kever Yang (3):
  Documentation: dt-bindings: add dt binding info for rk3288-smp
  ARM: rockchip: add basic smp support for rk3288
  ARM: dts: add intmem node for rk3288 smp support

 Documentation/devicetree/bindings/arm/cpus.txt |  1 +
 arch/arm/boot/dts/rk3288.dtsi                  | 18 ++++++++
 arch/arm/mach-rockchip/core.h                  |  1 +
 arch/arm/mach-rockchip/headsmp.S               | 14 ++++++
 arch/arm/mach-rockchip/platsmp.c               | 63 +++++++++++++++++++++++---
 5 files changed, 91 insertions(+), 6 deletions(-)

-- 
1.9.1

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[PATCH v2 0/3] add basic rk3288 smp support

[Kever Yang]

rk3288 is qual-core CPU Soc, we need to enable the smp.
This patchset works with either arch-timer use the phisical counter
in kernel or the firmware initialize the arch-timer virtual counter
offset and use virtual counter in kernel.

Changes in v2:
- add documentation
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment

Kever Yang (3):
  Documentation: dt-bindings: add dt binding info for rk3288-smp
  ARM: rockchip: add basic smp support for rk3288
  ARM: dts: add intmem node for rk3288 smp support

 Documentation/devicetree/bindings/arm/cpus.txt |  1 +
 arch/arm/boot/dts/rk3288.dtsi                  | 18 ++++++++
 arch/arm/mach-rockchip/core.h                  |  1 +
 arch/arm/mach-rockchip/headsmp.S               | 14 ++++++
 arch/arm/mach-rockchip/platsmp.c               | 63 +++++++++++++++++++++++---
 5 files changed, 91 insertions(+), 6 deletions(-)

-- 
1.9.1

[PATCH v2 1/3] Documentation: dt-bindings: add dt binding info for rk3288-smp

[Kever Yang]

This add documentation for rk3288 smp dt binding

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v2:
- add documentation

 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 298e2f6..4b46233 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -195,6 +195,7 @@ nodes to be present and contain the properties described below.
 			    "qcom,kpss-acc-v1"
 			    "qcom,kpss-acc-v2"
 			    "rockchip,rk3066-smp"
+			    "rockchip,rk3288-smp"
 
 	- cpu-release-addr
 		Usage: required for systems that have an "enable-method"
-- 
1.9.1

[PATCH v2 2/3] ARM: rockchip: add basic smp support for rk3288

[Kever Yang]

This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
when get into kernel.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v2:
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'

 arch/arm/mach-rockchip/core.h    |  1 +
 arch/arm/mach-rockchip/headsmp.S | 14 +++++++++
 arch/arm/mach-rockchip/platsmp.c | 63 ++++++++++++++++++++++++++++++++++++----
 3 files changed, 72 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
index 39bca96..13de05a 100644
--- a/arch/arm/mach-rockchip/core.h
+++ b/arch/arm/mach-rockchip/core.h
@@ -18,3 +18,4 @@ extern char rockchip_secondary_trampoline_end;
 
 extern unsigned long rockchip_boot_fn;
 extern void rockchip_secondary_startup(void);
+extern void rk3288_secondary_startup(void);
diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
index 73206e3..bacdb56 100644
--- a/arch/arm/mach-rockchip/headsmp.S
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -20,6 +20,20 @@ ENTRY(rockchip_secondary_startup)
 	b	secondary_startup
 ENDPROC(rockchip_secondary_startup)
 
+ENTRY(rk3288_secondary_startup)
+	mrc p15, 0, r0, c0, c0, 5
+	mov r2, #3
+	and r0, r0, r2
+	ldr r1, =0xff700000
+	ldr r1, [r1]
+	cmp r0, r1
+	beq 2f
+	ldr r2, =0xfffd0000
+	mov pc, r2
+2:
+	b	secondary_startup
+ENDPROC(rk3288_secondary_startup)
+
 ENTRY(rockchip_secondary_trampoline)
 	ldr	pc, 1f
 ENDPROC(rockchip_secondary_trampoline)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 189684f..022a01d 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -60,7 +60,7 @@ static void pmu_set_power_domain(int pd, bool on)
  * Handling of CPU cores
  */
 
-static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
+static int __cpuinit rk3066_boot_secondary(unsigned int cpu,
 					     struct task_struct *idle)
 {
 	if (!sram_base_addr || !pmu_base_addr) {
@@ -80,6 +80,28 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
 	return 0;
 }
 
+static int __cpuinit rk3288_boot_secondary(unsigned int cpu,
+					     struct task_struct *idle)
+{
+	if (!sram_base_addr) {
+		pr_err("%s: sram missing for cpu boot\n", __func__);
+		return -ENXIO;
+	}
+
+	if (cpu >= ncores) {
+		pr_err("%s: cpu %d outside maximum number of cpus %d\n",
+							__func__, cpu, ncores);
+		return -ENXIO;
+	}
+	/* start the core */
+	writel(virt_to_phys(rk3288_secondary_startup), sram_base_addr + 8);
+	writel(0xDEADBEAF, sram_base_addr + 4);
+	writel(cpu, sram_base_addr + 0);
+	dsb_sev();
+
+	return 0;
+}
+
 /**
  * rockchip_smp_prepare_sram - populate necessary sram block
  * Starting cores execute the code residing at the start of the on-chip sram
@@ -125,7 +147,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
 	return 0;
 }
 
-static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
+static void __init rk3066_smp_prepare_cpus(unsigned int max_cpus)
 {
 	struct device_node *node;
 	unsigned int i;
@@ -194,12 +216,41 @@ static void rockchip_cpu_die(unsigned int cpu)
 }
 #endif
 
-static struct smp_operations rockchip_smp_ops __initdata = {
-	.smp_prepare_cpus	= rockchip_smp_prepare_cpus,
-	.smp_boot_secondary	= rockchip_boot_secondary,
+static void __init rk3288_smp_prepare_cpus(unsigned int max_cpus)
+{
+	struct device_node *node;
+
+	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
+	if (!node) {
+		pr_err("%s: could not find sram dt node\n", __func__);
+		return;
+	}
+
+	sram_base_addr = of_iomap(node, 0);
+	if (!sram_base_addr) {
+		pr_err("%s: could not map pmu registers\n", __func__);
+		return;
+	}
+
+	ncores = 4;
+}
+
+static struct smp_operations rockchip3066_smp_ops __initdata = {
+	.smp_prepare_cpus	= rk3066_smp_prepare_cpus,
+	.smp_boot_secondary	= rk3066_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_kill		= rockchip_cpu_kill,
+	.cpu_die		= rockchip_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip3066_smp_ops);
+
+static struct smp_operations rockchip3288_smp_ops __initdata = {
+	.smp_prepare_cpus	= rk3288_smp_prepare_cpus,
+	.smp_boot_secondary	= rk3288_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_kill		= rockchip_cpu_kill,
 	.cpu_die		= rockchip_cpu_die,
 #endif
 };
-CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
+CPU_METHOD_OF_DECLARE(rk3288_smp, "rockchip,rk3288-smp", &rockchip3288_smp_ops);
-- 
1.9.1

[PATCH v2 2/3] ARM: rockchip: add basic smp support for rk3288

[Kever Yang]

This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
when get into kernel.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v2:
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'

 arch/arm/mach-rockchip/core.h    |  1 +
 arch/arm/mach-rockchip/headsmp.S | 14 +++++++++
 arch/arm/mach-rockchip/platsmp.c | 63 ++++++++++++++++++++++++++++++++++++----
 3 files changed, 72 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
index 39bca96..13de05a 100644
--- a/arch/arm/mach-rockchip/core.h
+++ b/arch/arm/mach-rockchip/core.h
@@ -18,3 +18,4 @@ extern char rockchip_secondary_trampoline_end;
 
 extern unsigned long rockchip_boot_fn;
 extern void rockchip_secondary_startup(void);
+extern void rk3288_secondary_startup(void);
diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
index 73206e3..bacdb56 100644
--- a/arch/arm/mach-rockchip/headsmp.S
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -20,6 +20,20 @@ ENTRY(rockchip_secondary_startup)
 	b	secondary_startup
 ENDPROC(rockchip_secondary_startup)
 
+ENTRY(rk3288_secondary_startup)
+	mrc p15, 0, r0, c0, c0, 5
+	mov r2, #3
+	and r0, r0, r2
+	ldr r1, =0xff700000
+	ldr r1, [r1]
+	cmp r0, r1
+	beq 2f
+	ldr r2, =0xfffd0000
+	mov pc, r2
+2:
+	b	secondary_startup
+ENDPROC(rk3288_secondary_startup)
+
 ENTRY(rockchip_secondary_trampoline)
 	ldr	pc, 1f
 ENDPROC(rockchip_secondary_trampoline)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 189684f..022a01d 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -60,7 +60,7 @@ static void pmu_set_power_domain(int pd, bool on)
  * Handling of CPU cores
  */
 
-static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
+static int __cpuinit rk3066_boot_secondary(unsigned int cpu,
 					     struct task_struct *idle)
 {
 	if (!sram_base_addr || !pmu_base_addr) {
@@ -80,6 +80,28 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
 	return 0;
 }
 
+static int __cpuinit rk3288_boot_secondary(unsigned int cpu,
+					     struct task_struct *idle)
+{
+	if (!sram_base_addr) {
+		pr_err("%s: sram missing for cpu boot\n", __func__);
+		return -ENXIO;
+	}
+
+	if (cpu >= ncores) {
+		pr_err("%s: cpu %d outside maximum number of cpus %d\n",
+							__func__, cpu, ncores);
+		return -ENXIO;
+	}
+	/* start the core */
+	writel(virt_to_phys(rk3288_secondary_startup), sram_base_addr + 8);
+	writel(0xDEADBEAF, sram_base_addr + 4);
+	writel(cpu, sram_base_addr + 0);
+	dsb_sev();
+
+	return 0;
+}
+
 /**
  * rockchip_smp_prepare_sram - populate necessary sram block
  * Starting cores execute the code residing at the start of the on-chip sram
@@ -125,7 +147,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
 	return 0;
 }
 
-static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
+static void __init rk3066_smp_prepare_cpus(unsigned int max_cpus)
 {
 	struct device_node *node;
 	unsigned int i;
@@ -194,12 +216,41 @@ static void rockchip_cpu_die(unsigned int cpu)
 }
 #endif
 
-static struct smp_operations rockchip_smp_ops __initdata = {
-	.smp_prepare_cpus	= rockchip_smp_prepare_cpus,
-	.smp_boot_secondary	= rockchip_boot_secondary,
+static void __init rk3288_smp_prepare_cpus(unsigned int max_cpus)
+{
+	struct device_node *node;
+
+	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
+	if (!node) {
+		pr_err("%s: could not find sram dt node\n", __func__);
+		return;
+	}
+
+	sram_base_addr = of_iomap(node, 0);
+	if (!sram_base_addr) {
+		pr_err("%s: could not map pmu registers\n", __func__);
+		return;
+	}
+
+	ncores = 4;
+}
+
+static struct smp_operations rockchip3066_smp_ops __initdata = {
+	.smp_prepare_cpus	= rk3066_smp_prepare_cpus,
+	.smp_boot_secondary	= rk3066_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_kill		= rockchip_cpu_kill,
+	.cpu_die		= rockchip_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip3066_smp_ops);
+
+static struct smp_operations rockchip3288_smp_ops __initdata = {
+	.smp_prepare_cpus	= rk3288_smp_prepare_cpus,
+	.smp_boot_secondary	= rk3288_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_kill		= rockchip_cpu_kill,
 	.cpu_die		= rockchip_cpu_die,
 #endif
 };
-CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
+CPU_METHOD_OF_DECLARE(rk3288_smp, "rockchip,rk3288-smp", &rockchip3288_smp_ops);
-- 
1.9.1

[PATCH v2 3/3] ARM: dts: add intmem node for rk3288 smp support

[Kever Yang]

This patch add intmem node des which is needed by platsmp.c
and enable the smp.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v2:
- adjust the alignment

 arch/arm/boot/dts/rk3288.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index dca586e..bcc4dad 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -40,6 +40,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		enable-method = "rockchip,rk3288-smp";
 		cpu@500 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
@@ -353,6 +354,23 @@
 		status = "disabled";
 	};
 
+	bus_intmem@ff700000 {
+		compatible = "mmio-sram";
+		reg = <0xff700000 0x18000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xff700000 0x18000>;
+		smp-sram@0 {
+			compatible = "rockchip,rk3066-smp-sram";
+			reg = <0x00 0x10>;
+		};
+	};
+
+	pmu_intmem@ff720000 {
+		compatible = "mmio-sram";
+		reg = <0xff720000 0x4000>;
+	};
+
 	pmu: power-management@ff730000 {
 		compatible = "rockchip,rk3288-pmu", "syscon";
 		reg = <0xff730000 0x100>;
-- 
1.9.1

[PATCH v2 3/3] ARM: dts: add intmem node for rk3288 smp support

[Kever Yang]

This patch add intmem node des which is needed by platsmp.c
and enable the smp.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v2:
- adjust the alignment

 arch/arm/boot/dts/rk3288.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index dca586e..bcc4dad 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -40,6 +40,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		enable-method = "rockchip,rk3288-smp";
 		cpu at 500 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
@@ -353,6 +354,23 @@
 		status = "disabled";
 	};
 
+	bus_intmem at ff700000 {
+		compatible = "mmio-sram";
+		reg = <0xff700000 0x18000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xff700000 0x18000>;
+		smp-sram at 0 {
+			compatible = "rockchip,rk3066-smp-sram";
+			reg = <0x00 0x10>;
+		};
+	};
+
+	pmu_intmem at ff720000 {
+		compatible = "mmio-sram";
+		reg = <0xff720000 0x4000>;
+	};
+
 	pmu: power-management at ff730000 {
 		compatible = "rockchip,rk3288-pmu", "syscon";
 		reg = <0xff730000 0x100>;
-- 
1.9.1

Re: [PATCH v2 1/3] Documentation: dt-bindings: add dt binding info for rk3288-smp

[Mark Rutland]

On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
> This add documentation for rk3288 smp dt binding
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v2:
> - add documentation
> 
>  Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 298e2f6..4b46233 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -195,6 +195,7 @@ nodes to be present and contain the properties described below.
>  			    "qcom,kpss-acc-v1"
>  			    "qcom,kpss-acc-v2"
>  			    "rockchip,rk3066-smp"
> +			    "rockchip,rk3288-smp"

How do these differ?

What does "rockchip,rk3288-smp" mean exactly?

Presumably other nodes / properties are required?

Mark.

Re: [PATCH v2 1/3] Documentation: dt-bindings: add dt binding info for rk3288-smp

[Mark Rutland]

On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
> This add documentation for rk3288 smp dt binding
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v2:
> - add documentation
> 
>  Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 298e2f6..4b46233 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -195,6 +195,7 @@ nodes to be present and contain the properties described below.
>  			    "qcom,kpss-acc-v1"
>  			    "qcom,kpss-acc-v2"
>  			    "rockchip,rk3066-smp"
> +			    "rockchip,rk3288-smp"

How do these differ?

What does "rockchip,rk3288-smp" mean exactly?

Presumably other nodes / properties are required?

Mark.

Re: [PATCH v2 2/3] ARM: rockchip: add basic smp support for rk3288

[Sonny Rao]

On Tue, Sep 16, 2014 at 3:44 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
> This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
> when get into kernel.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - use rk3288_boot_secondary instead ofsmp_boot_secondary
> - discards the power domain operation
> - handle the per cpu starup when actived by 'sev'
>
>  arch/arm/mach-rockchip/core.h    |  1 +
>  arch/arm/mach-rockchip/headsmp.S | 14 +++++++++
>  arch/arm/mach-rockchip/platsmp.c | 63 ++++++++++++++++++++++++++++++++++++----
>  3 files changed, 72 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
> index 39bca96..13de05a 100644
> --- a/arch/arm/mach-rockchip/core.h
> +++ b/arch/arm/mach-rockchip/core.h
> @@ -18,3 +18,4 @@ extern char rockchip_secondary_trampoline_end;
>
>  extern unsigned long rockchip_boot_fn;
>  extern void rockchip_secondary_startup(void);
> +extern void rk3288_secondary_startup(void);
> diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
> index 73206e3..bacdb56 100644
> --- a/arch/arm/mach-rockchip/headsmp.S
> +++ b/arch/arm/mach-rockchip/headsmp.S
> @@ -20,6 +20,20 @@ ENTRY(rockchip_secondary_startup)
>         b       secondary_startup
>  ENDPROC(rockchip_secondary_startup)
>
> +ENTRY(rk3288_secondary_startup)
> +       mrc p15, 0, r0, c0, c0, 5
> +       mov r2, #3
> +       and r0, r0, r2
> +       ldr r1, =0xff700000
> +       ldr r1, [r1]
> +       cmp r0, r1
> +       beq 2f
> +       ldr r2, =0xfffd0000
> +       mov pc, r2
> +2:
> +       b       secondary_startup
> +ENDPROC(rk3288_secondary_startup)

Comments on what's going on here would be nice.
It looks like what you're doing is checking to see whether this CPU is
the one that is supposed to wake up or not, but looking at sram
(written by the C code below), and this isn't the correct CPU then go
back to boot rom?  Since we read in int-mem from the device-tree it
would also probably be good to make that ldr r1, 0xff700000 reference
the sram_base_addr variable rather than hard coding here.

> +
>  ENTRY(rockchip_secondary_trampoline)
>         ldr     pc, 1f
>  ENDPROC(rockchip_secondary_trampoline)
> diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
> index 189684f..022a01d 100644
> --- a/arch/arm/mach-rockchip/platsmp.c
> +++ b/arch/arm/mach-rockchip/platsmp.c
> @@ -60,7 +60,7 @@ static void pmu_set_power_domain(int pd, bool on)
>   * Handling of CPU cores
>   */
>
> -static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
> +static int __cpuinit rk3066_boot_secondary(unsigned int cpu,
>                                              struct task_struct *idle)
>  {
>         if (!sram_base_addr || !pmu_base_addr) {
> @@ -80,6 +80,28 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
>         return 0;
>  }
>
> +static int __cpuinit rk3288_boot_secondary(unsigned int cpu,
> +                                            struct task_struct *idle)
> +{
> +       if (!sram_base_addr) {
> +               pr_err("%s: sram missing for cpu boot\n", __func__);
> +               return -ENXIO;
> +       }
> +
> +       if (cpu >= ncores) {
> +               pr_err("%s: cpu %d outside maximum number of cpus %d\n",
> +                                                       __func__, cpu, ncores);
> +               return -ENXIO;
> +       }
> +       /* start the core */
> +       writel(virt_to_phys(rk3288_secondary_startup), sram_base_addr + 8);
> +       writel(0xDEADBEAF, sram_base_addr + 4);
> +       writel(cpu, sram_base_addr + 0);

I guess the boot rom is looking for 0xDEADBEEF here at sram_base_addr
+ 4, but the cpu itself will be looking at sram_base_addr + 0.
Again, might be good to somehow document what the protocol is.

> +       dsb_sev();
> +
> +       return 0;
> +}
> +
>  /**
>   * rockchip_smp_prepare_sram - populate necessary sram block
>   * Starting cores execute the code residing at the start of the on-chip sram
> @@ -125,7 +147,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
>         return 0;
>  }
>
> -static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
> +static void __init rk3066_smp_prepare_cpus(unsigned int max_cpus)
>  {
>         struct device_node *node;
>         unsigned int i;
> @@ -194,12 +216,41 @@ static void rockchip_cpu_die(unsigned int cpu)
>  }
>  #endif
>
> -static struct smp_operations rockchip_smp_ops __initdata = {
> -       .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
> -       .smp_boot_secondary     = rockchip_boot_secondary,
> +static void __init rk3288_smp_prepare_cpus(unsigned int max_cpus)
> +{
> +       struct device_node *node;
> +
> +       node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
> +       if (!node) {
> +               pr_err("%s: could not find sram dt node\n", __func__);
> +               return;
> +       }
> +
> +       sram_base_addr = of_iomap(node, 0);
> +       if (!sram_base_addr) {
> +               pr_err("%s: could not map pmu registers\n", __func__);
> +               return;
> +       }
> +
> +       ncores = 4;
> +}
> +
> +static struct smp_operations rockchip3066_smp_ops __initdata = {
> +       .smp_prepare_cpus       = rk3066_smp_prepare_cpus,
> +       .smp_boot_secondary     = rk3066_boot_secondary,
> +#ifdef CONFIG_HOTPLUG_CPU
> +       .cpu_kill               = rockchip_cpu_kill,
> +       .cpu_die                = rockchip_cpu_die,
> +#endif
> +};
> +CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip3066_smp_ops);
> +
> +static struct smp_operations rockchip3288_smp_ops __initdata = {
> +       .smp_prepare_cpus       = rk3288_smp_prepare_cpus,
> +       .smp_boot_secondary     = rk3288_boot_secondary,
>  #ifdef CONFIG_HOTPLUG_CPU
>         .cpu_kill               = rockchip_cpu_kill,
>         .cpu_die                = rockchip_cpu_die,
>  #endif
>  };
> -CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
> +CPU_METHOD_OF_DECLARE(rk3288_smp, "rockchip,rk3288-smp", &rockchip3288_smp_ops);
> --
> 1.9.1
>

[PATCH v2 2/3] ARM: rockchip: add basic smp support for rk3288

[Sonny Rao]

On Tue, Sep 16, 2014 at 3:44 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
> This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
> when get into kernel.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - use rk3288_boot_secondary instead ofsmp_boot_secondary
> - discards the power domain operation
> - handle the per cpu starup when actived by 'sev'
>
>  arch/arm/mach-rockchip/core.h    |  1 +
>  arch/arm/mach-rockchip/headsmp.S | 14 +++++++++
>  arch/arm/mach-rockchip/platsmp.c | 63 ++++++++++++++++++++++++++++++++++++----
>  3 files changed, 72 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
> index 39bca96..13de05a 100644
> --- a/arch/arm/mach-rockchip/core.h
> +++ b/arch/arm/mach-rockchip/core.h
> @@ -18,3 +18,4 @@ extern char rockchip_secondary_trampoline_end;
>
>  extern unsigned long rockchip_boot_fn;
>  extern void rockchip_secondary_startup(void);
> +extern void rk3288_secondary_startup(void);
> diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
> index 73206e3..bacdb56 100644
> --- a/arch/arm/mach-rockchip/headsmp.S
> +++ b/arch/arm/mach-rockchip/headsmp.S
> @@ -20,6 +20,20 @@ ENTRY(rockchip_secondary_startup)
>         b       secondary_startup
>  ENDPROC(rockchip_secondary_startup)
>
> +ENTRY(rk3288_secondary_startup)
> +       mrc p15, 0, r0, c0, c0, 5
> +       mov r2, #3
> +       and r0, r0, r2
> +       ldr r1, =0xff700000
> +       ldr r1, [r1]
> +       cmp r0, r1
> +       beq 2f
> +       ldr r2, =0xfffd0000
> +       mov pc, r2
> +2:
> +       b       secondary_startup
> +ENDPROC(rk3288_secondary_startup)

Comments on what's going on here would be nice.
It looks like what you're doing is checking to see whether this CPU is
the one that is supposed to wake up or not, but looking at sram
(written by the C code below), and this isn't the correct CPU then go
back to boot rom?  Since we read in int-mem from the device-tree it
would also probably be good to make that ldr r1, 0xff700000 reference
the sram_base_addr variable rather than hard coding here.

> +
>  ENTRY(rockchip_secondary_trampoline)
>         ldr     pc, 1f
>  ENDPROC(rockchip_secondary_trampoline)
> diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
> index 189684f..022a01d 100644
> --- a/arch/arm/mach-rockchip/platsmp.c
> +++ b/arch/arm/mach-rockchip/platsmp.c
> @@ -60,7 +60,7 @@ static void pmu_set_power_domain(int pd, bool on)
>   * Handling of CPU cores
>   */
>
> -static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
> +static int __cpuinit rk3066_boot_secondary(unsigned int cpu,
>                                              struct task_struct *idle)
>  {
>         if (!sram_base_addr || !pmu_base_addr) {
> @@ -80,6 +80,28 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
>         return 0;
>  }
>
> +static int __cpuinit rk3288_boot_secondary(unsigned int cpu,
> +                                            struct task_struct *idle)
> +{
> +       if (!sram_base_addr) {
> +               pr_err("%s: sram missing for cpu boot\n", __func__);
> +               return -ENXIO;
> +       }
> +
> +       if (cpu >= ncores) {
> +               pr_err("%s: cpu %d outside maximum number of cpus %d\n",
> +                                                       __func__, cpu, ncores);
> +               return -ENXIO;
> +       }
> +       /* start the core */
> +       writel(virt_to_phys(rk3288_secondary_startup), sram_base_addr + 8);
> +       writel(0xDEADBEAF, sram_base_addr + 4);
> +       writel(cpu, sram_base_addr + 0);

I guess the boot rom is looking for 0xDEADBEEF here at sram_base_addr
+ 4, but the cpu itself will be looking at sram_base_addr + 0.
Again, might be good to somehow document what the protocol is.

> +       dsb_sev();
> +
> +       return 0;
> +}
> +
>  /**
>   * rockchip_smp_prepare_sram - populate necessary sram block
>   * Starting cores execute the code residing at the start of the on-chip sram
> @@ -125,7 +147,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
>         return 0;
>  }
>
> -static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
> +static void __init rk3066_smp_prepare_cpus(unsigned int max_cpus)
>  {
>         struct device_node *node;
>         unsigned int i;
> @@ -194,12 +216,41 @@ static void rockchip_cpu_die(unsigned int cpu)
>  }
>  #endif
>
> -static struct smp_operations rockchip_smp_ops __initdata = {
> -       .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
> -       .smp_boot_secondary     = rockchip_boot_secondary,
> +static void __init rk3288_smp_prepare_cpus(unsigned int max_cpus)
> +{
> +       struct device_node *node;
> +
> +       node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
> +       if (!node) {
> +               pr_err("%s: could not find sram dt node\n", __func__);
> +               return;
> +       }
> +
> +       sram_base_addr = of_iomap(node, 0);
> +       if (!sram_base_addr) {
> +               pr_err("%s: could not map pmu registers\n", __func__);
> +               return;
> +       }
> +
> +       ncores = 4;
> +}
> +
> +static struct smp_operations rockchip3066_smp_ops __initdata = {
> +       .smp_prepare_cpus       = rk3066_smp_prepare_cpus,
> +       .smp_boot_secondary     = rk3066_boot_secondary,
> +#ifdef CONFIG_HOTPLUG_CPU
> +       .cpu_kill               = rockchip_cpu_kill,
> +       .cpu_die                = rockchip_cpu_die,
> +#endif
> +};
> +CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip3066_smp_ops);
> +
> +static struct smp_operations rockchip3288_smp_ops __initdata = {
> +       .smp_prepare_cpus       = rk3288_smp_prepare_cpus,
> +       .smp_boot_secondary     = rk3288_boot_secondary,
>  #ifdef CONFIG_HOTPLUG_CPU
>         .cpu_kill               = rockchip_cpu_kill,
>         .cpu_die                = rockchip_cpu_die,
>  #endif
>  };
> -CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
> +CPU_METHOD_OF_DECLARE(rk3288_smp, "rockchip,rk3288-smp", &rockchip3288_smp_ops);
> --
> 1.9.1
>

Re: [PATCH v2 2/3] ARM: rockchip: add basic smp support for rk3288

[Kever Yang]

Sonny,

On 09/17/2014 04:17 AM, Sonny Rao wrote:
> On Tue, Sep 16, 2014 at 3:44 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
>> This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
>> when get into kernel.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> Changes in v2:
>> - use rk3288_boot_secondary instead ofsmp_boot_secondary
>> - discards the power domain operation
>> - handle the per cpu starup when actived by 'sev'
>>
>>   arch/arm/mach-rockchip/core.h    |  1 +
>>   arch/arm/mach-rockchip/headsmp.S | 14 +++++++++
>>   arch/arm/mach-rockchip/platsmp.c | 63 ++++++++++++++++++++++++++++++++++++----
>>   3 files changed, 72 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
>> index 39bca96..13de05a 100644
>> --- a/arch/arm/mach-rockchip/core.h
>> +++ b/arch/arm/mach-rockchip/core.h
>> @@ -18,3 +18,4 @@ extern char rockchip_secondary_trampoline_end;
>>
>>   extern unsigned long rockchip_boot_fn;
>>   extern void rockchip_secondary_startup(void);
>> +extern void rk3288_secondary_startup(void);
>> diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
>> index 73206e3..bacdb56 100644
>> --- a/arch/arm/mach-rockchip/headsmp.S
>> +++ b/arch/arm/mach-rockchip/headsmp.S
>> @@ -20,6 +20,20 @@ ENTRY(rockchip_secondary_startup)
>>          b       secondary_startup
>>   ENDPROC(rockchip_secondary_startup)
>>
>> +ENTRY(rk3288_secondary_startup)
>> +       mrc p15, 0, r0, c0, c0, 5
>> +       mov r2, #3
>> +       and r0, r0, r2
>> +       ldr r1, =0xff700000
>> +       ldr r1, [r1]
>> +       cmp r0, r1
>> +       beq 2f
>> +       ldr r2, =0xfffd0000
>> +       mov pc, r2
>> +2:
>> +       b       secondary_startup
>> +ENDPROC(rk3288_secondary_startup)
> Comments on what's going on here would be nice.
I will do that in next version.
> It looks like what you're doing is checking to see whether this CPU is
> the one that is supposed to wake up or not, but looking at sram
> (written by the C code below), and this isn't the correct CPU then go
> back to boot rom?  Since we read in int-mem from the device-tree it
> would also probably be good to make that ldr r1, 0xff700000 reference
> the sram_base_addr variable rather than hard coding here.
I don't like the hard coding either, but I don't know how to get the
physical base of sram and bootrom address in the assemble code.
>
>> +
>>   ENTRY(rockchip_secondary_trampoline)
>>          ldr     pc, 1f
>>   ENDPROC(rockchip_secondary_trampoline)
>> diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
>> index 189684f..022a01d 100644
>> --- a/arch/arm/mach-rockchip/platsmp.c
>> +++ b/arch/arm/mach-rockchip/platsmp.c
>> @@ -60,7 +60,7 @@ static void pmu_set_power_domain(int pd, bool on)
>>    * Handling of CPU cores
>>    */
>>
>> -static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
>> +static int __cpuinit rk3066_boot_secondary(unsigned int cpu,
>>                                               struct task_struct *idle)
>>   {
>>          if (!sram_base_addr || !pmu_base_addr) {
>> @@ -80,6 +80,28 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
>>          return 0;
>>   }
>>
>> +static int __cpuinit rk3288_boot_secondary(unsigned int cpu,
>> +                                            struct task_struct *idle)
>> +{
>> +       if (!sram_base_addr) {
>> +               pr_err("%s: sram missing for cpu boot\n", __func__);
>> +               return -ENXIO;
>> +       }
>> +
>> +       if (cpu >= ncores) {
>> +               pr_err("%s: cpu %d outside maximum number of cpus %d\n",
>> +                                                       __func__, cpu, ncores);
>> +               return -ENXIO;
>> +       }
>> +       /* start the core */
>> +       writel(virt_to_phys(rk3288_secondary_startup), sram_base_addr + 8);
>> +       writel(0xDEADBEAF, sram_base_addr + 4);
>> +       writel(cpu, sram_base_addr + 0);
> I guess the boot rom is looking for 0xDEADBEEF here at sram_base_addr
> + 4, but the cpu itself will be looking at sram_base_addr + 0.
> Again, might be good to somehow document what the protocol is.
>
>> +       dsb_sev();
>> +
>> +       return 0;
>> +}
>> +
>>   /**
>>    * rockchip_smp_prepare_sram - populate necessary sram block
>>    * Starting cores execute the code residing at the start of the on-chip sram
>> @@ -125,7 +147,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
>>          return 0;
>>   }
>>
>> -static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
>> +static void __init rk3066_smp_prepare_cpus(unsigned int max_cpus)
>>   {
>>          struct device_node *node;
>>          unsigned int i;
>> @@ -194,12 +216,41 @@ static void rockchip_cpu_die(unsigned int cpu)
>>   }
>>   #endif
>>
>> -static struct smp_operations rockchip_smp_ops __initdata = {
>> -       .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
>> -       .smp_boot_secondary     = rockchip_boot_secondary,
>> +static void __init rk3288_smp_prepare_cpus(unsigned int max_cpus)
>> +{
>> +       struct device_node *node;
>> +
>> +       node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
>> +       if (!node) {
>> +               pr_err("%s: could not find sram dt node\n", __func__);
>> +               return;
>> +       }
>> +
>> +       sram_base_addr = of_iomap(node, 0);
>> +       if (!sram_base_addr) {
>> +               pr_err("%s: could not map pmu registers\n", __func__);
>> +               return;
>> +       }
>> +
>> +       ncores = 4;
>> +}
>> +
>> +static struct smp_operations rockchip3066_smp_ops __initdata = {
>> +       .smp_prepare_cpus       = rk3066_smp_prepare_cpus,
>> +       .smp_boot_secondary     = rk3066_boot_secondary,
>> +#ifdef CONFIG_HOTPLUG_CPU
>> +       .cpu_kill               = rockchip_cpu_kill,
>> +       .cpu_die                = rockchip_cpu_die,
>> +#endif
>> +};
>> +CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip3066_smp_ops);
>> +
>> +static struct smp_operations rockchip3288_smp_ops __initdata = {
>> +       .smp_prepare_cpus       = rk3288_smp_prepare_cpus,
>> +       .smp_boot_secondary     = rk3288_boot_secondary,
>>   #ifdef CONFIG_HOTPLUG_CPU
>>          .cpu_kill               = rockchip_cpu_kill,
>>          .cpu_die                = rockchip_cpu_die,
>>   #endif
>>   };
>> -CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
>> +CPU_METHOD_OF_DECLARE(rk3288_smp, "rockchip,rk3288-smp", &rockchip3288_smp_ops);
>> --
>> 1.9.1
>>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
>
>

[PATCH v2 2/3] ARM: rockchip: add basic smp support for rk3288

[Kever Yang]

Sonny,

On 09/17/2014 04:17 AM, Sonny Rao wrote:
> On Tue, Sep 16, 2014 at 3:44 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
>> This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
>> when get into kernel.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> Changes in v2:
>> - use rk3288_boot_secondary instead ofsmp_boot_secondary
>> - discards the power domain operation
>> - handle the per cpu starup when actived by 'sev'
>>
>>   arch/arm/mach-rockchip/core.h    |  1 +
>>   arch/arm/mach-rockchip/headsmp.S | 14 +++++++++
>>   arch/arm/mach-rockchip/platsmp.c | 63 ++++++++++++++++++++++++++++++++++++----
>>   3 files changed, 72 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
>> index 39bca96..13de05a 100644
>> --- a/arch/arm/mach-rockchip/core.h
>> +++ b/arch/arm/mach-rockchip/core.h
>> @@ -18,3 +18,4 @@ extern char rockchip_secondary_trampoline_end;
>>
>>   extern unsigned long rockchip_boot_fn;
>>   extern void rockchip_secondary_startup(void);
>> +extern void rk3288_secondary_startup(void);
>> diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
>> index 73206e3..bacdb56 100644
>> --- a/arch/arm/mach-rockchip/headsmp.S
>> +++ b/arch/arm/mach-rockchip/headsmp.S
>> @@ -20,6 +20,20 @@ ENTRY(rockchip_secondary_startup)
>>          b       secondary_startup
>>   ENDPROC(rockchip_secondary_startup)
>>
>> +ENTRY(rk3288_secondary_startup)
>> +       mrc p15, 0, r0, c0, c0, 5
>> +       mov r2, #3
>> +       and r0, r0, r2
>> +       ldr r1, =0xff700000
>> +       ldr r1, [r1]
>> +       cmp r0, r1
>> +       beq 2f
>> +       ldr r2, =0xfffd0000
>> +       mov pc, r2
>> +2:
>> +       b       secondary_startup
>> +ENDPROC(rk3288_secondary_startup)
> Comments on what's going on here would be nice.
I will do that in next version.
> It looks like what you're doing is checking to see whether this CPU is
> the one that is supposed to wake up or not, but looking at sram
> (written by the C code below), and this isn't the correct CPU then go
> back to boot rom?  Since we read in int-mem from the device-tree it
> would also probably be good to make that ldr r1, 0xff700000 reference
> the sram_base_addr variable rather than hard coding here.
I don't like the hard coding either, but I don't know how to get the
physical base of sram and bootrom address in the assemble code.
>
>> +
>>   ENTRY(rockchip_secondary_trampoline)
>>          ldr     pc, 1f
>>   ENDPROC(rockchip_secondary_trampoline)
>> diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
>> index 189684f..022a01d 100644
>> --- a/arch/arm/mach-rockchip/platsmp.c
>> +++ b/arch/arm/mach-rockchip/platsmp.c
>> @@ -60,7 +60,7 @@ static void pmu_set_power_domain(int pd, bool on)
>>    * Handling of CPU cores
>>    */
>>
>> -static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
>> +static int __cpuinit rk3066_boot_secondary(unsigned int cpu,
>>                                               struct task_struct *idle)
>>   {
>>          if (!sram_base_addr || !pmu_base_addr) {
>> @@ -80,6 +80,28 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
>>          return 0;
>>   }
>>
>> +static int __cpuinit rk3288_boot_secondary(unsigned int cpu,
>> +                                            struct task_struct *idle)
>> +{
>> +       if (!sram_base_addr) {
>> +               pr_err("%s: sram missing for cpu boot\n", __func__);
>> +               return -ENXIO;
>> +       }
>> +
>> +       if (cpu >= ncores) {
>> +               pr_err("%s: cpu %d outside maximum number of cpus %d\n",
>> +                                                       __func__, cpu, ncores);
>> +               return -ENXIO;
>> +       }
>> +       /* start the core */
>> +       writel(virt_to_phys(rk3288_secondary_startup), sram_base_addr + 8);
>> +       writel(0xDEADBEAF, sram_base_addr + 4);
>> +       writel(cpu, sram_base_addr + 0);
> I guess the boot rom is looking for 0xDEADBEEF here at sram_base_addr
> + 4, but the cpu itself will be looking at sram_base_addr + 0.
> Again, might be good to somehow document what the protocol is.
>
>> +       dsb_sev();
>> +
>> +       return 0;
>> +}
>> +
>>   /**
>>    * rockchip_smp_prepare_sram - populate necessary sram block
>>    * Starting cores execute the code residing at the start of the on-chip sram
>> @@ -125,7 +147,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
>>          return 0;
>>   }
>>
>> -static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
>> +static void __init rk3066_smp_prepare_cpus(unsigned int max_cpus)
>>   {
>>          struct device_node *node;
>>          unsigned int i;
>> @@ -194,12 +216,41 @@ static void rockchip_cpu_die(unsigned int cpu)
>>   }
>>   #endif
>>
>> -static struct smp_operations rockchip_smp_ops __initdata = {
>> -       .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
>> -       .smp_boot_secondary     = rockchip_boot_secondary,
>> +static void __init rk3288_smp_prepare_cpus(unsigned int max_cpus)
>> +{
>> +       struct device_node *node;
>> +
>> +       node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
>> +       if (!node) {
>> +               pr_err("%s: could not find sram dt node\n", __func__);
>> +               return;
>> +       }
>> +
>> +       sram_base_addr = of_iomap(node, 0);
>> +       if (!sram_base_addr) {
>> +               pr_err("%s: could not map pmu registers\n", __func__);
>> +               return;
>> +       }
>> +
>> +       ncores = 4;
>> +}
>> +
>> +static struct smp_operations rockchip3066_smp_ops __initdata = {
>> +       .smp_prepare_cpus       = rk3066_smp_prepare_cpus,
>> +       .smp_boot_secondary     = rk3066_boot_secondary,
>> +#ifdef CONFIG_HOTPLUG_CPU
>> +       .cpu_kill               = rockchip_cpu_kill,
>> +       .cpu_die                = rockchip_cpu_die,
>> +#endif
>> +};
>> +CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip3066_smp_ops);
>> +
>> +static struct smp_operations rockchip3288_smp_ops __initdata = {
>> +       .smp_prepare_cpus       = rk3288_smp_prepare_cpus,
>> +       .smp_boot_secondary     = rk3288_boot_secondary,
>>   #ifdef CONFIG_HOTPLUG_CPU
>>          .cpu_kill               = rockchip_cpu_kill,
>>          .cpu_die                = rockchip_cpu_die,
>>   #endif
>>   };
>> -CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
>> +CPU_METHOD_OF_DECLARE(rk3288_smp, "rockchip,rk3288-smp", &rockchip3288_smp_ops);
>> --
>> 1.9.1
>>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
>
>

Re: [PATCH v2 1/3] Documentation: dt-bindings: add dt binding info for rk3288-smp

[Kever Yang]

Hi Mark,

     Thanks for your comment.
On 09/17/2014 02:54 AM, Mark Rutland wrote:
> On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
>> This add documentation for rk3288 smp dt binding
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> Changes in v2:
>> - add documentation
>>
>>   Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 298e2f6..4b46233 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -195,6 +195,7 @@ nodes to be present and contain the properties described below.
>>   			    "qcom,kpss-acc-v1"
>>   			    "qcom,kpss-acc-v2"
>>   			    "rockchip,rk3066-smp"
>> +			    "rockchip,rk3288-smp"
> How do these differ?
rk3066 and rk3288 smp bring up code is quite different, so I need a new 
node "rockchip,rk3288-smp"
other than "rockchip,rk3066-smp".
>
> What does "rockchip,rk3288-smp" mean exactly?
The driver who using this node is in 2/3 of this patchset, it goes to 
linux-arm-kernel list and linux-rockchip
list, I'm not sure if you have get that, maybe I need a RESEND?
>
> Presumably other nodes / properties are required?
Base on linux-next, I think only "rockchip,rk3288-smp" is new node to my 
driver.

BR
-Kever

Re: [PATCH v2 1/3] Documentation: dt-bindings: add dt binding info for rk3288-smp

[Kever Yang]

Hi Mark,

     Thanks for your comment.
On 09/17/2014 02:54 AM, Mark Rutland wrote:
> On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
>> This add documentation for rk3288 smp dt binding
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> Changes in v2:
>> - add documentation
>>
>>   Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 298e2f6..4b46233 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -195,6 +195,7 @@ nodes to be present and contain the properties described below.
>>   			    "qcom,kpss-acc-v1"
>>   			    "qcom,kpss-acc-v2"
>>   			    "rockchip,rk3066-smp"
>> +			    "rockchip,rk3288-smp"
> How do these differ?
rk3066 and rk3288 smp bring up code is quite different, so I need a new 
node "rockchip,rk3288-smp"
other than "rockchip,rk3066-smp".
>
> What does "rockchip,rk3288-smp" mean exactly?
The driver who using this node is in 2/3 of this patchset, it goes to 
linux-arm-kernel list and linux-rockchip
list, I'm not sure if you have get that, maybe I need a RESEND?
>
> Presumably other nodes / properties are required?
Base on linux-next, I think only "rockchip,rk3288-smp" is new node to my 
driver.

BR
-Kever

Re: [PATCH v2 2/3] ARM: rockchip: add basic smp support for rk3288

[Heiko Stübner]

Hi Kever,

Am Mittwoch, 17. September 2014, 09:03:37 schrieb Kever Yang:
> Sonny,
> 
> On 09/17/2014 04:17 AM, Sonny Rao wrote:
> > On Tue, Sep 16, 2014 at 3:44 AM, Kever Yang <kever.yang@rock-chips.com> 
wrote:
> >> This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
> >> when get into kernel.
> >> 
> >> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> >> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> >> ---
> >> 
> >> Changes in v2:
> >> - use rk3288_boot_secondary instead ofsmp_boot_secondary
> >> - discards the power domain operation
> >> - handle the per cpu starup when actived by 'sev'
> >> 
> >>   arch/arm/mach-rockchip/core.h    |  1 +
> >>   arch/arm/mach-rockchip/headsmp.S | 14 +++++++++
> >>   arch/arm/mach-rockchip/platsmp.c | 63
> >>   ++++++++++++++++++++++++++++++++++++---- 3 files changed, 72
> >>   insertions(+), 6 deletions(-)
> >> 
> >> diff --git a/arch/arm/mach-rockchip/core.h
> >> b/arch/arm/mach-rockchip/core.h
> >> index 39bca96..13de05a 100644
> >> --- a/arch/arm/mach-rockchip/core.h
> >> +++ b/arch/arm/mach-rockchip/core.h
> >> @@ -18,3 +18,4 @@ extern char rockchip_secondary_trampoline_end;
> >> 
> >>   extern unsigned long rockchip_boot_fn;
> >>   extern void rockchip_secondary_startup(void);
> >> 
> >> +extern void rk3288_secondary_startup(void);
> >> diff --git a/arch/arm/mach-rockchip/headsmp.S
> >> b/arch/arm/mach-rockchip/headsmp.S index 73206e3..bacdb56 100644
> >> --- a/arch/arm/mach-rockchip/headsmp.S
> >> +++ b/arch/arm/mach-rockchip/headsmp.S
> >> @@ -20,6 +20,20 @@ ENTRY(rockchip_secondary_startup)
> >> 
> >>          b       secondary_startup
> >>   
> >>   ENDPROC(rockchip_secondary_startup)
> >> 
> >> +ENTRY(rk3288_secondary_startup)
> >> +       mrc p15, 0, r0, c0, c0, 5
> >> +       mov r2, #3
> >> +       and r0, r0, r2
> >> +       ldr r1, =0xff700000
> >> +       ldr r1, [r1]
> >> +       cmp r0, r1
> >> +       beq 2f
> >> +       ldr r2, =0xfffd0000
> >> +       mov pc, r2
> >> +2:
> >> +       b       secondary_startup
> >> +ENDPROC(rk3288_secondary_startup)
> > 
> > Comments on what's going on here would be nice.
> 
> I will do that in next version.
> 
> > It looks like what you're doing is checking to see whether this CPU is
> > the one that is supposed to wake up or not, but looking at sram
> > (written by the C code below), and this isn't the correct CPU then go
> > back to boot rom?  Since we read in int-mem from the device-tree it
> > would also probably be good to make that ldr r1, 0xff700000 reference
> > the sram_base_addr variable rather than hard coding here.
> 
> I don't like the hard coding either, but I don't know how to get the
> physical base of sram and bootrom address in the assemble code.

Take a look at how the rk3066 smp code handles the address: defining 
rockchip_boot_fn in headsmp.S, having it in core.h and filling it with the 
address in platsmp.c

I would think transfering the address read from dt could work similarly.


Heiko

[PATCH v2 2/3] ARM: rockchip: add basic smp support for rk3288

[Heiko Stübner]

Hi Kever,

Am Mittwoch, 17. September 2014, 09:03:37 schrieb Kever Yang:
> Sonny,
> 
> On 09/17/2014 04:17 AM, Sonny Rao wrote:
> > On Tue, Sep 16, 2014 at 3:44 AM, Kever Yang <kever.yang@rock-chips.com> 
wrote:
> >> This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
> >> when get into kernel.
> >> 
> >> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> >> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> >> ---
> >> 
> >> Changes in v2:
> >> - use rk3288_boot_secondary instead ofsmp_boot_secondary
> >> - discards the power domain operation
> >> - handle the per cpu starup when actived by 'sev'
> >> 
> >>   arch/arm/mach-rockchip/core.h    |  1 +
> >>   arch/arm/mach-rockchip/headsmp.S | 14 +++++++++
> >>   arch/arm/mach-rockchip/platsmp.c | 63
> >>   ++++++++++++++++++++++++++++++++++++---- 3 files changed, 72
> >>   insertions(+), 6 deletions(-)
> >> 
> >> diff --git a/arch/arm/mach-rockchip/core.h
> >> b/arch/arm/mach-rockchip/core.h
> >> index 39bca96..13de05a 100644
> >> --- a/arch/arm/mach-rockchip/core.h
> >> +++ b/arch/arm/mach-rockchip/core.h
> >> @@ -18,3 +18,4 @@ extern char rockchip_secondary_trampoline_end;
> >> 
> >>   extern unsigned long rockchip_boot_fn;
> >>   extern void rockchip_secondary_startup(void);
> >> 
> >> +extern void rk3288_secondary_startup(void);
> >> diff --git a/arch/arm/mach-rockchip/headsmp.S
> >> b/arch/arm/mach-rockchip/headsmp.S index 73206e3..bacdb56 100644
> >> --- a/arch/arm/mach-rockchip/headsmp.S
> >> +++ b/arch/arm/mach-rockchip/headsmp.S
> >> @@ -20,6 +20,20 @@ ENTRY(rockchip_secondary_startup)
> >> 
> >>          b       secondary_startup
> >>   
> >>   ENDPROC(rockchip_secondary_startup)
> >> 
> >> +ENTRY(rk3288_secondary_startup)
> >> +       mrc p15, 0, r0, c0, c0, 5
> >> +       mov r2, #3
> >> +       and r0, r0, r2
> >> +       ldr r1, =0xff700000
> >> +       ldr r1, [r1]
> >> +       cmp r0, r1
> >> +       beq 2f
> >> +       ldr r2, =0xfffd0000
> >> +       mov pc, r2
> >> +2:
> >> +       b       secondary_startup
> >> +ENDPROC(rk3288_secondary_startup)
> > 
> > Comments on what's going on here would be nice.
> 
> I will do that in next version.
> 
> > It looks like what you're doing is checking to see whether this CPU is
> > the one that is supposed to wake up or not, but looking at sram
> > (written by the C code below), and this isn't the correct CPU then go
> > back to boot rom?  Since we read in int-mem from the device-tree it
> > would also probably be good to make that ldr r1, 0xff700000 reference
> > the sram_base_addr variable rather than hard coding here.
> 
> I don't like the hard coding either, but I don't know how to get the
> physical base of sram and bootrom address in the assemble code.

Take a look at how the rk3066 smp code handles the address: defining 
rockchip_boot_fn in headsmp.S, having it in core.h and filling it with the 
address in platsmp.c

I would think transfering the address read from dt could work similarly.


Heiko

Re: [PATCH v2 1/3] Documentation: dt-bindings: add dt binding info for rk3288-smp

[Mark Rutland]

On Wed, Sep 17, 2014 at 02:12:28AM +0100, Kever Yang wrote:
> Hi Mark,
> 
>      Thanks for your comment.
> On 09/17/2014 02:54 AM, Mark Rutland wrote:
> > On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
> >> This add documentation for rk3288 smp dt binding
> >>
> >> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> >> ---
> >>
> >> Changes in v2:
> >> - add documentation
> >>
> >>   Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> >>   1 file changed, 1 insertion(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> >> index 298e2f6..4b46233 100644
> >> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> >> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> >> @@ -195,6 +195,7 @@ nodes to be present and contain the properties described below.
> >>   			    "qcom,kpss-acc-v1"
> >>   			    "qcom,kpss-acc-v2"
> >>   			    "rockchip,rk3066-smp"
> >> +			    "rockchip,rk3288-smp"
> > How do these differ?
> rk3066 and rk3288 smp bring up code is quite different, so I need a new 
> node "rockchip,rk3288-smp"
> other than "rockchip,rk3066-smp".

The code being different is a Linux detail. What is different in the HW
that necessitates the code being different?

> > What does "rockchip,rk3288-smp" mean exactly?
> The driver who using this node is in 2/3 of this patchset, it goes to 
> linux-arm-kernel list and linux-rockchip
> list, I'm not sure if you have get that, maybe I need a RESEND?

Documentaiton and drivers are different things. A binding is a contract,
and for that contract to be meaningful it needs to be described.

> > Presumably other nodes / properties are required?
> Base on linux-next, I think only "rockchip,rk3288-smp" is new node to my 
> driver.

But presumably there are other resources that you require (e.g. a system
controller, perhaps a specific portion of sram). I can't just put
"rockchip,rk3288-smp" into an otherwise empty DT and get SMP support, I
would assume.

Mark.

Re: [PATCH v2 1/3] Documentation: dt-bindings: add dt binding info for rk3288-smp

[Mark Rutland]

On Wed, Sep 17, 2014 at 02:12:28AM +0100, Kever Yang wrote:
> Hi Mark,
> 
>      Thanks for your comment.
> On 09/17/2014 02:54 AM, Mark Rutland wrote:
> > On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
> >> This add documentation for rk3288 smp dt binding
> >>
> >> Signed-off-by: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> >> ---
> >>
> >> Changes in v2:
> >> - add documentation
> >>
> >>   Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> >>   1 file changed, 1 insertion(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> >> index 298e2f6..4b46233 100644
> >> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> >> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> >> @@ -195,6 +195,7 @@ nodes to be present and contain the properties described below.
> >>   			    "qcom,kpss-acc-v1"
> >>   			    "qcom,kpss-acc-v2"
> >>   			    "rockchip,rk3066-smp"
> >> +			    "rockchip,rk3288-smp"
> > How do these differ?
> rk3066 and rk3288 smp bring up code is quite different, so I need a new 
> node "rockchip,rk3288-smp"
> other than "rockchip,rk3066-smp".

The code being different is a Linux detail. What is different in the HW
that necessitates the code being different?

> > What does "rockchip,rk3288-smp" mean exactly?
> The driver who using this node is in 2/3 of this patchset, it goes to 
> linux-arm-kernel list and linux-rockchip
> list, I'm not sure if you have get that, maybe I need a RESEND?

Documentaiton and drivers are different things. A binding is a contract,
and for that contract to be meaningful it needs to be described.

> > Presumably other nodes / properties are required?
> Base on linux-next, I think only "rockchip,rk3288-smp" is new node to my 
> driver.

But presumably there are other resources that you require (e.g. a system
controller, perhaps a specific portion of sram). I can't just put
"rockchip,rk3288-smp" into an otherwise empty DT and get SMP support, I
would assume.

Mark.
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