From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Tue, 16 Sep 2014 20:09:18 +0200
Subject: [U-Boot] [PATCH 15/35] arm: socfpga: clock: Add code to read
	clock configuration
In-Reply-To: <5417477E.70005@opensource.altera.com>
References: <1410779188-6880-1-git-send-email-marex@denx.de>
	<1410779188-6880-16-git-send-email-marex@denx.de>
	<5417477E.70005@opensource.altera.com>
Message-ID: <201409162009.18550.marex@denx.de>
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On Monday, September 15, 2014 at 10:09:34 PM, Dinh Nguyen wrote:
> On 09/15/2014 06:06 AM, Marek Vasut wrote:
[...]
> > +	/* get the L4 SP clock which supplied to UART */
> > +	reg = readl(&clock_manager_base->main_pll.maindiv);
> > +	reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
> > +	clock = clock / (reg + 1);
> 
> This is not a +1. The l4 mp clock divider is structured like this:
> 
> 0x0 = divide by 1
> 0x1 = divide by 2
> 0x2 = divide by 4
> 0x3 = divide by 8
> 0x4 = divide by 16
> 
> So it should be:
> clock = clock / (1 << reg);

Fixed, thanks! I also synched the clock code with your codebase for all but the 
SDRAM auto refresh part.

Best regards,
Marek Vasut