From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 52/89] drm/i915/gen9: Disable WM if corresponding latency is 0 Date: Fri, 19 Sep 2014 13:05:02 +0300 Message-ID: <20140919100502.GG12416@intel.com> References: <1409830075-11139-1-git-send-email-damien.lespiau@intel.com> <1409830075-11139-53-git-send-email-damien.lespiau@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 08A7F6E5F1 for ; Fri, 19 Sep 2014 03:05:06 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1409830075-11139-53-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Sep 04, 2014 at 12:27:18PM +0100, Damien Lespiau wrote: > From: Vandana Kannan > = > According to updated BSpec, If level 1 or any higher level has a value of= 0x00, > that level and any higher levels are unused and the associated watermark > registers must not be enabled. > = > This patch checks for latency 0 for level >=3D1 and does not enable WM > corresponding to level m | m>=3Dn, if level n (n !=3D 0) has a 0us latenc= y. > = > v2: Satheesh's review comments > - zero-out latency values (for all higher levels if latency of given > level is zero ) in read_wm_latency() function itself > = > v3: removed redundant check as per Satheesh's observation. > v4: rebase on top before merging (Damien) > = > Signed-off-by: Damien Lespiau > Signed-off-by: Vandana Kannan > Reviewed-by: Satheeshakrishna M (v3) > Cc: Satheeshakrishna M > --- > drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 16ad008..fdf297f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2253,7 +2253,7 @@ static void intel_read_wm_latency(struct drm_device= *dev, uint16_t wm[8]) > = > if (IS_GEN9(dev)) { > uint32_t val; > - int ret; > + int ret, i; > int level, max_level =3D ilk_wm_max_level(dev); > = > /* read the first set of memory latencies[0:3] */ > @@ -2305,12 +2305,22 @@ static void intel_read_wm_latency(struct drm_devi= ce *dev, uint16_t wm[8]) > * we always add 2us there. > * - For levels >=3D1, punit returns 0us latency when they are > * disabled, so we respect that and don't add 2us then > + * > + * Additionally, if a level n (n > 1) has a 0us latency, all > + * levels m (m >=3D n) need to be disabled. We make sure to > + * sanitize the values out of the punit to satisfy this > + * requirement. > */ > wm[0] +=3D 2; > for (level =3D 1; level <=3D max_level; level++) > if (wm[level] !=3D 0) > wm[level] +=3D 2; > + else { > + for (i =3D level + 1; i <=3D max_level; i++) > + wm[i] =3D 0; > = > + break; > + } If we're going to be paranoid I think we should disable all higher WM levels whose latency is lower than any of the lower levels. And I think we'll want something like dev_priv->wm.max_wm_level instead of relying on the zero latency tricks. That thing has been on my TODO list since forever. > } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > uint64_t sskpd =3D I915_READ64(MCH_SSKPD); > = > @@ -3253,7 +3263,7 @@ static bool skl_compute_plane_wm(struct skl_pipe_wm= _parameters *p, > uint32_t method1, method2, plane_bytes_per_line; > uint32_t result_bytes; > = > - if (!p->active || !p_params->enabled) { > + if (mem_value =3D=3D 0 || !p->active || !p_params->enabled) { > *res_blocks =3D PLANE_WM_BLOCKS_DEFAULT; > *res_lines =3D PLANE_WM_LINES_DEFAULT; > return false; > -- = > 1.8.3.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC