From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752722AbaIYHeo (ORCPT ); Thu, 25 Sep 2014 03:34:44 -0400 Received: from mail-we0-f174.google.com ([74.125.82.174]:56277 "EHLO mail-we0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751328AbaIYHel (ORCPT ); Thu, 25 Sep 2014 03:34:41 -0400 Date: Thu, 25 Sep 2014 09:34:36 +0200 From: Thierry Reding To: Yijing Wang Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Xinwei Hu , Wuyun , linux-arm-kernel@lists.infradead.org, Russell King , linux-arch@vger.kernel.org, arnab.basu@freescale.com, Bharat.Bhushan@freescale.com, x86@kernel.org, Arnd Bergmann , Thomas Gleixner , Konrad Rzeszutek Wilk , xen-devel@lists.xenproject.org, Joerg Roedel , iommu@lists.linux-foundation.org, linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, Sebastian Ott , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , Sergei Shtylyov , Michael Ellerman , Thomas Petazzoni Subject: Re: [PATCH v2 12/22] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq Message-ID: <20140925073435.GJ12423@ulmo> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <1411614872-4009-13-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="rwgQ89ZNnFUwFHTC" Content-Disposition: inline In-Reply-To: <1411614872-4009-13-git-send-email-wangyijing@huawei.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --rwgQ89ZNnFUwFHTC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Sep 25, 2014 at 11:14:22AM +0800, Yijing Wang wrote: [...] > diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c [...] > @@ -132,12 +132,12 @@ msi_irq_allocated: > /* Make sure the search for available interrupts didn't fail */ > if (irq >=3D 64) { > if (request_private_bits) { > - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying= just one", > + pr_err("octeon_setup_msi_irq: Unable to find %d free interrupts, tryi= ng just one", > 1 << request_private_bits); Perhaps while at it make this (and other similar changes in this patch): pr_err("%s(): Unable to ...", __func__, ...); So that it becomes more resilient against this kind of rename? > request_private_bits =3D 0; > goto try_only_one; > } else > - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); > + panic("octeon_setup_msi_irq: Unable to find a free MSI interrupt"); > @@ -210,14 +210,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nv= ec, int type) > =20 > return 0; > } > - This... > @@ -240,7 +239,7 @@ void arch_teardown_msi_irq(unsigned int irq) > */ > number_irqs =3D 0; > while ((irq0 + number_irqs < 64) && > - (msi_multiple_irq_bitmask[index] > + (msi_multiple_irq_bitmask[index] =2E.. and this seem like unrelated whitespace changes. > & (1ull << (irq0 + number_irqs)))) > number_irqs++; > number_irqs++; > @@ -249,8 +248,8 @@ void arch_teardown_msi_irq(unsigned int irq) > /* Shift the mask to the correct bit location */ > bitmask <<=3D irq0; > if ((msi_free_irq_bitmask[index] & bitmask) !=3D bitmask) > - panic("arch_teardown_msi_irq: Attempted to teardown MSI " > - "interrupt (%d) not in use", irq); > + panic("octeon_teardown_msi_irq: Attempted to teardown MSI " > + "interrupt (%d) not in use", irq); And the second line here also needlessly changes the indentation. Thierry --rwgQ89ZNnFUwFHTC Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUI8WLAAoJEN0jrNd/PrOhp2MQAK6S7hsneW6O97w/t1chjlGR ug1JLAxeP84A0Vj4I6KwfrHjux8rDqoByI5bDhH+ywcRQuf90Dx9+L9QEfWlzkcC K1qT+twZDUqVFhCIJtuEtNVJbEXb0NlPK74W/6cUubFdAKbY1+MZe66Z0BZlBl36 bjxEyTh6uZkemh8PLwP45mJQCTD/d5/lNGDCrgzKgurE1HIHXV1r0FoD9zLJZpfA UATpp5rQYfePlynE1mCT+G0QXcfo+zf8kp49jLxeciX5QZYs8DbZ2IwbhG4ov2je p8SHV5T+c8D1+Q7UjNbXpDGHz12Ctpby/bLd3+FGsmeIZJbE4o5NcE5pChZfI52v Rgl0wLOlswsM2xoSGdhA1x51QEHqFxShBf/+FwbxLA7shNWELd6gRpv9mcYSv6oy MgALA5tV5r18NZyBm+SsvwUrgAF7e1ndIU/UYhAH1lIz3CMtqTnZ2AZIpXoJeKLo rtzWB2MThJnnZXUpW3Umj3UWoZkcAy6zQSWBGV40hC+t3dkr1US9bOgGIrO6huyy qTqNG+A20dRO85W7LoslDg5CO401jS8JRiHbYQW9g+QhHkWLpROgcrCoK1dz+Q2B QjaLp2fjuM7wyyYXRLcQo68i7Y9AUv2R+k1fidvlfuWXfvzbeK6x0BHSx8nhBec6 SU2aBh+SOaTeNEFZjRFv =dRXg -----END PGP SIGNATURE----- --rwgQ89ZNnFUwFHTC-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [PATCH v2 12/22] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq Date: Thu, 25 Sep 2014 09:34:36 +0200 Message-ID: <20140925073435.GJ12423@ulmo> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <1411614872-4009-13-git-send-email-wangyijing@huawei.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============8355181659551532871==" Return-path: In-Reply-To: <1411614872-4009-13-git-send-email-wangyijing-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Yijing Wang Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org, linux-ia64-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, sparclinux-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arch-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-s390-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King , Michael Ellerman , x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Sebastian Ott , Benjamin Herrenschmidt , xen-devel-GuqFBffKawtpuQazS67q72D2FQJk+8+b@public.gmane.org, arnab.basu-KZfg59tc24xl57MIdRCFDg@public.gmane.org, Arnd Bergmann , Chris Metcalf , Bjorn Helgaas , Thomas Gleixner , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Thomas Petazzoni , Xinwei Hu , Tony Luck , Sergei Shtylyov , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ralf Baechle , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, David List-Id: linux-arch.vger.kernel.org --===============8355181659551532871== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="rwgQ89ZNnFUwFHTC" Content-Disposition: inline --rwgQ89ZNnFUwFHTC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Sep 25, 2014 at 11:14:22AM +0800, Yijing Wang wrote: [...] > diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c [...] > @@ -132,12 +132,12 @@ msi_irq_allocated: > /* Make sure the search for available interrupts didn't fail */ > if (irq >=3D 64) { > if (request_private_bits) { > - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying= just one", > + pr_err("octeon_setup_msi_irq: Unable to find %d free interrupts, tryi= ng just one", > 1 << request_private_bits); Perhaps while at it make this (and other similar changes in this patch): pr_err("%s(): Unable to ...", __func__, ...); So that it becomes more resilient against this kind of rename? > request_private_bits =3D 0; > goto try_only_one; > } else > - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); > + panic("octeon_setup_msi_irq: Unable to find a free MSI interrupt"); > @@ -210,14 +210,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nv= ec, int type) > =20 > return 0; > } > - This... > @@ -240,7 +239,7 @@ void arch_teardown_msi_irq(unsigned int irq) > */ > number_irqs =3D 0; > while ((irq0 + number_irqs < 64) && > - (msi_multiple_irq_bitmask[index] > + (msi_multiple_irq_bitmask[index] =2E.. and this seem like unrelated whitespace changes. > & (1ull << (irq0 + number_irqs)))) > number_irqs++; > number_irqs++; > @@ -249,8 +248,8 @@ void arch_teardown_msi_irq(unsigned int irq) > /* Shift the mask to the correct bit location */ > bitmask <<=3D irq0; > if ((msi_free_irq_bitmask[index] & bitmask) !=3D bitmask) > - panic("arch_teardown_msi_irq: Attempted to teardown MSI " > - "interrupt (%d) not in use", irq); > + panic("octeon_teardown_msi_irq: Attempted to teardown MSI " > + "interrupt (%d) not in use", irq); And the second line here also needlessly changes the indentation. Thierry --rwgQ89ZNnFUwFHTC Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUI8WLAAoJEN0jrNd/PrOhp2MQAK6S7hsneW6O97w/t1chjlGR ug1JLAxeP84A0Vj4I6KwfrHjux8rDqoByI5bDhH+ywcRQuf90Dx9+L9QEfWlzkcC K1qT+twZDUqVFhCIJtuEtNVJbEXb0NlPK74W/6cUubFdAKbY1+MZe66Z0BZlBl36 bjxEyTh6uZkemh8PLwP45mJQCTD/d5/lNGDCrgzKgurE1HIHXV1r0FoD9zLJZpfA UATpp5rQYfePlynE1mCT+G0QXcfo+zf8kp49jLxeciX5QZYs8DbZ2IwbhG4ov2je p8SHV5T+c8D1+Q7UjNbXpDGHz12Ctpby/bLd3+FGsmeIZJbE4o5NcE5pChZfI52v Rgl0wLOlswsM2xoSGdhA1x51QEHqFxShBf/+FwbxLA7shNWELd6gRpv9mcYSv6oy MgALA5tV5r18NZyBm+SsvwUrgAF7e1ndIU/UYhAH1lIz3CMtqTnZ2AZIpXoJeKLo rtzWB2MThJnnZXUpW3Umj3UWoZkcAy6zQSWBGV40hC+t3dkr1US9bOgGIrO6huyy qTqNG+A20dRO85W7LoslDg5CO401jS8JRiHbYQW9g+QhHkWLpROgcrCoK1dz+Q2B QjaLp2fjuM7wyyYXRLcQo68i7Y9AUv2R+k1fidvlfuWXfvzbeK6x0BHSx8nhBec6 SU2aBh+SOaTeNEFZjRFv =dRXg -----END PGP SIGNATURE----- --rwgQ89ZNnFUwFHTC-- --===============8355181659551532871== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline --===============8355181659551532871==-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Thu, 25 Sep 2014 07:34:36 +0000 Subject: Re: [PATCH v2 12/22] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq Message-Id: <20140925073435.GJ12423@ulmo> MIME-Version: 1 Content-Type: multipart/mixed; boundary="rwgQ89ZNnFUwFHTC" List-Id: References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <1411614872-4009-13-git-send-email-wangyijing@huawei.com> In-Reply-To: <1411614872-4009-13-git-send-email-wangyijing-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> To: Yijing Wang Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org, linux-ia64-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, sparclinux-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arch-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-s390-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King , Michael Ellerman , x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Sebastian Ott , Benjamin Herrenschmidt , xen-devel-GuqFBffKawtpuQazS67q72D2FQJk+8+b@public.gmane.org, arnab.basu-KZfg59tc24xl57MIdRCFDg@public.gmane.org, Arnd Bergmann , Chris Metcalf , Bjorn Helgaas , Thomas Gleixner , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Thomas Petazzoni , Xinwei Hu , Tony Luck , Sergei Shtylyov , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ralf Baechle , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, David --rwgQ89ZNnFUwFHTC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Sep 25, 2014 at 11:14:22AM +0800, Yijing Wang wrote: [...] > diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c [...] > @@ -132,12 +132,12 @@ msi_irq_allocated: > /* Make sure the search for available interrupts didn't fail */ > if (irq >=3D 64) { > if (request_private_bits) { > - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying= just one", > + pr_err("octeon_setup_msi_irq: Unable to find %d free interrupts, tryi= ng just one", > 1 << request_private_bits); Perhaps while at it make this (and other similar changes in this patch): pr_err("%s(): Unable to ...", __func__, ...); So that it becomes more resilient against this kind of rename? > request_private_bits =3D 0; > goto try_only_one; > } else > - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); > + panic("octeon_setup_msi_irq: Unable to find a free MSI interrupt"); > @@ -210,14 +210,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nv= ec, int type) > =20 > return 0; > } > - This... > @@ -240,7 +239,7 @@ void arch_teardown_msi_irq(unsigned int irq) > */ > number_irqs =3D 0; > while ((irq0 + number_irqs < 64) && > - (msi_multiple_irq_bitmask[index] > + (msi_multiple_irq_bitmask[index] =2E.. and this seem like unrelated whitespace changes. > & (1ull << (irq0 + number_irqs)))) > number_irqs++; > number_irqs++; > @@ -249,8 +248,8 @@ void arch_teardown_msi_irq(unsigned int irq) > /* Shift the mask to the correct bit location */ > bitmask <<=3D irq0; > if ((msi_free_irq_bitmask[index] & bitmask) !=3D bitmask) > - panic("arch_teardown_msi_irq: Attempted to teardown MSI " > - "interrupt (%d) not in use", irq); > + panic("octeon_teardown_msi_irq: Attempted to teardown MSI " > + "interrupt (%d) not in use", irq); And the second line here also needlessly changes the indentation. Thierry --rwgQ89ZNnFUwFHTC Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUI8WLAAoJEN0jrNd/PrOhp2MQAK6S7hsneW6O97w/t1chjlGR ug1JLAxeP84A0Vj4I6KwfrHjux8rDqoByI5bDhH+ywcRQuf90Dx9+L9QEfWlzkcC K1qT+twZDUqVFhCIJtuEtNVJbEXb0NlPK74W/6cUubFdAKbY1+MZe66Z0BZlBl36 bjxEyTh6uZkemh8PLwP45mJQCTD/d5/lNGDCrgzKgurE1HIHXV1r0FoD9zLJZpfA UATpp5rQYfePlynE1mCT+G0QXcfo+zf8kp49jLxeciX5QZYs8DbZ2IwbhG4ov2je p8SHV5T+c8D1+Q7UjNbXpDGHz12Ctpby/bLd3+FGsmeIZJbE4o5NcE5pChZfI52v Rgl0wLOlswsM2xoSGdhA1x51QEHqFxShBf/+FwbxLA7shNWELd6gRpv9mcYSv6oy MgALA5tV5r18NZyBm+SsvwUrgAF7e1ndIU/UYhAH1lIz3CMtqTnZ2AZIpXoJeKLo rtzWB2MThJnnZXUpW3Umj3UWoZkcAy6zQSWBGV40hC+t3dkr1US9bOgGIrO6huyy qTqNG+A20dRO85W7LoslDg5CO401jS8JRiHbYQW9g+QhHkWLpROgcrCoK1dz+Q2B QjaLp2fjuM7wyyYXRLcQo68i7Y9AUv2R+k1fidvlfuWXfvzbeK6x0BHSx8nhBec6 SU2aBh+SOaTeNEFZjRFv =dRXg -----END PGP SIGNATURE----- --rwgQ89ZNnFUwFHTC-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wg0-x22c.google.com (mail-wg0-x22c.google.com [IPv6:2a00:1450:400c:c00::22c]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 5AE5B1A009F for ; Thu, 25 Sep 2014 17:34:43 +1000 (EST) Received: by mail-wg0-f44.google.com with SMTP id z12so3591788wgg.15 for ; Thu, 25 Sep 2014 00:34:39 -0700 (PDT) Date: Thu, 25 Sep 2014 09:34:36 +0200 From: Thierry Reding To: Yijing Wang Subject: Re: [PATCH v2 12/22] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq Message-ID: <20140925073435.GJ12423@ulmo> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <1411614872-4009-13-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="rwgQ89ZNnFUwFHTC" In-Reply-To: <1411614872-4009-13-git-send-email-wangyijing@huawei.com> Cc: linux-mips@linux-mips.org, linux-ia64@vger.kernel.org, linux-pci@vger.kernel.org, Bharat.Bhushan@freescale.com, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org, linux-s390@vger.kernel.org, Russell King , Joerg Roedel , x86@kernel.org, Sebastian Ott , xen-devel@lists.xenproject.org, arnab.basu@freescale.com, Arnd Bergmann , Konrad Rzeszutek Wilk , Chris Metcalf , Bjorn Helgaas , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Xinwei Hu , Tony Luck , Sergei Shtylyov , linux-kernel@vger.kernel.org, Ralf Baechle , iommu@lists.linux-foundation.org, David Vrabel , Wuyun , linuxppc-dev@lists.ozlabs.org, "David S. Miller" , Lucas Stach List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , --rwgQ89ZNnFUwFHTC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Sep 25, 2014 at 11:14:22AM +0800, Yijing Wang wrote: [...] > diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c [...] > @@ -132,12 +132,12 @@ msi_irq_allocated: > /* Make sure the search for available interrupts didn't fail */ > if (irq >=3D 64) { > if (request_private_bits) { > - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying= just one", > + pr_err("octeon_setup_msi_irq: Unable to find %d free interrupts, tryi= ng just one", > 1 << request_private_bits); Perhaps while at it make this (and other similar changes in this patch): pr_err("%s(): Unable to ...", __func__, ...); So that it becomes more resilient against this kind of rename? > request_private_bits =3D 0; > goto try_only_one; > } else > - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); > + panic("octeon_setup_msi_irq: Unable to find a free MSI interrupt"); > @@ -210,14 +210,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nv= ec, int type) > =20 > return 0; > } > - This... > @@ -240,7 +239,7 @@ void arch_teardown_msi_irq(unsigned int irq) > */ > number_irqs =3D 0; > while ((irq0 + number_irqs < 64) && > - (msi_multiple_irq_bitmask[index] > + (msi_multiple_irq_bitmask[index] =2E.. and this seem like unrelated whitespace changes. > & (1ull << (irq0 + number_irqs)))) > number_irqs++; > number_irqs++; > @@ -249,8 +248,8 @@ void arch_teardown_msi_irq(unsigned int irq) > /* Shift the mask to the correct bit location */ > bitmask <<=3D irq0; > if ((msi_free_irq_bitmask[index] & bitmask) !=3D bitmask) > - panic("arch_teardown_msi_irq: Attempted to teardown MSI " > - "interrupt (%d) not in use", irq); > + panic("octeon_teardown_msi_irq: Attempted to teardown MSI " > + "interrupt (%d) not in use", irq); And the second line here also needlessly changes the indentation. Thierry --rwgQ89ZNnFUwFHTC Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUI8WLAAoJEN0jrNd/PrOhp2MQAK6S7hsneW6O97w/t1chjlGR ug1JLAxeP84A0Vj4I6KwfrHjux8rDqoByI5bDhH+ywcRQuf90Dx9+L9QEfWlzkcC K1qT+twZDUqVFhCIJtuEtNVJbEXb0NlPK74W/6cUubFdAKbY1+MZe66Z0BZlBl36 bjxEyTh6uZkemh8PLwP45mJQCTD/d5/lNGDCrgzKgurE1HIHXV1r0FoD9zLJZpfA UATpp5rQYfePlynE1mCT+G0QXcfo+zf8kp49jLxeciX5QZYs8DbZ2IwbhG4ov2je p8SHV5T+c8D1+Q7UjNbXpDGHz12Ctpby/bLd3+FGsmeIZJbE4o5NcE5pChZfI52v Rgl0wLOlswsM2xoSGdhA1x51QEHqFxShBf/+FwbxLA7shNWELd6gRpv9mcYSv6oy MgALA5tV5r18NZyBm+SsvwUrgAF7e1ndIU/UYhAH1lIz3CMtqTnZ2AZIpXoJeKLo rtzWB2MThJnnZXUpW3Umj3UWoZkcAy6zQSWBGV40hC+t3dkr1US9bOgGIrO6huyy qTqNG+A20dRO85W7LoslDg5CO401jS8JRiHbYQW9g+QhHkWLpROgcrCoK1dz+Q2B QjaLp2fjuM7wyyYXRLcQo68i7Y9AUv2R+k1fidvlfuWXfvzbeK6x0BHSx8nhBec6 SU2aBh+SOaTeNEFZjRFv =dRXg -----END PGP SIGNATURE----- --rwgQ89ZNnFUwFHTC-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: thierry.reding@gmail.com (Thierry Reding) Date: Thu, 25 Sep 2014 09:34:36 +0200 Subject: [PATCH v2 12/22] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq In-Reply-To: <1411614872-4009-13-git-send-email-wangyijing@huawei.com> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <1411614872-4009-13-git-send-email-wangyijing@huawei.com> Message-ID: <20140925073435.GJ12423@ulmo> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Sep 25, 2014 at 11:14:22AM +0800, Yijing Wang wrote: [...] > diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c [...] > @@ -132,12 +132,12 @@ msi_irq_allocated: > /* Make sure the search for available interrupts didn't fail */ > if (irq >= 64) { > if (request_private_bits) { > - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one", > + pr_err("octeon_setup_msi_irq: Unable to find %d free interrupts, trying just one", > 1 << request_private_bits); Perhaps while@it make this (and other similar changes in this patch): pr_err("%s(): Unable to ...", __func__, ...); So that it becomes more resilient against this kind of rename? > request_private_bits = 0; > goto try_only_one; > } else > - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); > + panic("octeon_setup_msi_irq: Unable to find a free MSI interrupt"); > @@ -210,14 +210,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > > return 0; > } > - This... > @@ -240,7 +239,7 @@ void arch_teardown_msi_irq(unsigned int irq) > */ > number_irqs = 0; > while ((irq0 + number_irqs < 64) && > - (msi_multiple_irq_bitmask[index] > + (msi_multiple_irq_bitmask[index] ... and this seem like unrelated whitespace changes. > & (1ull << (irq0 + number_irqs)))) > number_irqs++; > number_irqs++; > @@ -249,8 +248,8 @@ void arch_teardown_msi_irq(unsigned int irq) > /* Shift the mask to the correct bit location */ > bitmask <<= irq0; > if ((msi_free_irq_bitmask[index] & bitmask) != bitmask) > - panic("arch_teardown_msi_irq: Attempted to teardown MSI " > - "interrupt (%d) not in use", irq); > + panic("octeon_teardown_msi_irq: Attempted to teardown MSI " > + "interrupt (%d) not in use", irq); And the second line here also needlessly changes the indentation. Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 819 bytes Desc: not available URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Thu, 25 Sep 2014 07:34:36 +0000 Subject: Re: [PATCH v2 12/22] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq Message-Id: <20140925073435.GJ12423@ulmo> MIME-Version: 1 Content-Type: multipart/mixed; boundary="rwgQ89ZNnFUwFHTC" List-Id: References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <1411614872-4009-13-git-send-email-wangyijing@huawei.com> In-Reply-To: <1411614872-4009-13-git-send-email-wangyijing@huawei.com> To: Yijing Wang Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Xinwei Hu , Wuyun , linux-arm-kernel@lists.infradead.org, Russell King , linux-arch@vger.kernel.org, arnab.basu@freescale.com, Bharat.Bhushan@freescale.com, x86@kernel.org, Arnd Bergmann , Thomas Gleixner , Konrad Rzeszutek Wilk , xen-devel@lists.xenproject.org, Joerg Roedel , iommu@lists.linux-foundation.org, linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, Sebastian Ott , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , Sergei Shtylyov , Michael Ellerman , Thomas Petazzoni --rwgQ89ZNnFUwFHTC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Sep 25, 2014 at 11:14:22AM +0800, Yijing Wang wrote: [...] > diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c [...] > @@ -132,12 +132,12 @@ msi_irq_allocated: > /* Make sure the search for available interrupts didn't fail */ > if (irq >=3D 64) { > if (request_private_bits) { > - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying= just one", > + pr_err("octeon_setup_msi_irq: Unable to find %d free interrupts, tryi= ng just one", > 1 << request_private_bits); Perhaps while at it make this (and other similar changes in this patch): pr_err("%s(): Unable to ...", __func__, ...); So that it becomes more resilient against this kind of rename? > request_private_bits =3D 0; > goto try_only_one; > } else > - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); > + panic("octeon_setup_msi_irq: Unable to find a free MSI interrupt"); > @@ -210,14 +210,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nv= ec, int type) > =20 > return 0; > } > - This... > @@ -240,7 +239,7 @@ void arch_teardown_msi_irq(unsigned int irq) > */ > number_irqs =3D 0; > while ((irq0 + number_irqs < 64) && > - (msi_multiple_irq_bitmask[index] > + (msi_multiple_irq_bitmask[index] =2E.. and this seem like unrelated whitespace changes. > & (1ull << (irq0 + number_irqs)))) > number_irqs++; > number_irqs++; > @@ -249,8 +248,8 @@ void arch_teardown_msi_irq(unsigned int irq) > /* Shift the mask to the correct bit location */ > bitmask <<=3D irq0; > if ((msi_free_irq_bitmask[index] & bitmask) !=3D bitmask) > - panic("arch_teardown_msi_irq: Attempted to teardown MSI " > - "interrupt (%d) not in use", irq); > + panic("octeon_teardown_msi_irq: Attempted to teardown MSI " > + "interrupt (%d) not in use", irq); And the second line here also needlessly changes the indentation. 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