From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753747AbaIZJFt (ORCPT ); Fri, 26 Sep 2014 05:05:49 -0400 Received: from mail-we0-f175.google.com ([74.125.82.175]:49351 "EHLO mail-we0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752966AbaIZJFn (ORCPT ); Fri, 26 Sep 2014 05:05:43 -0400 Date: Fri, 26 Sep 2014 11:05:38 +0200 From: Thierry Reding To: Yijing Wang Cc: Liviu Dudau , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Xinwei Hu , Wuyun , linux-arm-kernel@lists.infradead.org, Russell King , linux-arch@vger.kernel.org, arnab.basu@freescale.com, Bharat.Bhushan@freescale.com, x86@kernel.org, Arnd Bergmann , Thomas Gleixner , Konrad Rzeszutek Wilk , xen-devel@lists.xenproject.org, Joerg Roedel , iommu@lists.linux-foundation.org, linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, Sebastian Ott , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , Sergei Shtylyov , Michael Ellerman , Thomas Petazzoni Subject: Re: [PATCH v2 00/22] Use MSI chip framework to configure MSI/MSI-X in all platforms Message-ID: <20140926090537.GH31106@ulmo> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <20140925074235.GN12423@ulmo> <20140925144855.GB31157@bart.dudau.co.uk> <20140925164937.GB30382@ulmo> <20140925171612.GC31157@bart.dudau.co.uk> <542505B3.7040208@huawei.com> <20140926085430.GG31106@ulmo> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="mhOzvPhkurUs4vA9" Content-Disposition: inline In-Reply-To: <20140926085430.GG31106@ulmo> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --mhOzvPhkurUs4vA9 Content-Type: multipart/mixed; boundary="7J16OGEJ/mt06A90" Content-Disposition: inline --7J16OGEJ/mt06A90 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Sep 26, 2014 at 10:54:32AM +0200, Thierry Reding wrote: [...] > At least for Tegra it's trivial to just hook it up in tegra_pcie_scan_bus() > directly (patch attached). Really attached this time. Thierry --7J16OGEJ/mt06A90 Content-Type: text/x-diff; charset=us-ascii Content-Disposition: inline; filename="0001-PCI-tegra-Remove-.add_bus-callback.patch" Content-Transfer-Encoding: quoted-printable =46rom 2cedfcf38cdfe21688d1363659f28e271ce43358 Mon Sep 17 00:00:00 2001 =46rom: Thierry Reding Date: Fri, 26 Sep 2014 10:35:47 +0200 Subject: [PATCH] PCI: tegra: Remove .add_bus() callback The .add_bus() callback is called for every bus and used to associate an MSI chip with each bus. However the PCI core code already propagates the root bus' MSI chip to child busses, so it is enough to associate the MSI chip with the root bus upon creation. Conveniently the Tegra PCIe host bridge driver creates the root bus directly, so the association can be done at the same time. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 3d43874319be..d314e549ac0c 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -694,15 +694,6 @@ static int tegra_pcie_map_irq(const struct pci_dev *pd= ev, u8 slot, u8 pin) return irq; } =20 -static void tegra_pcie_add_bus(struct pci_bus *bus) -{ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - struct tegra_pcie *pcie =3D sys_to_pcie(bus->sysdata); - - bus->msi =3D &pcie->msi.chip; - } -} - static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sy= s) { struct tegra_pcie *pcie =3D sys_to_pcie(sys); @@ -713,6 +704,9 @@ static struct pci_bus *tegra_pcie_scan_bus(int nr, stru= ct pci_sys_data *sys) if (!bus) return NULL; =20 + if (IS_ENABLED(CONFIG_PCI_MSI)) + bus->msi =3D &pcie->msi.chip; + pci_scan_child_bus(bus); =20 return bus; @@ -1885,7 +1879,6 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie) hw.private_data =3D (void **)&pcie; hw.setup =3D tegra_pcie_setup; hw.map_irq =3D tegra_pcie_map_irq; - hw.add_bus =3D tegra_pcie_add_bus; hw.scan =3D tegra_pcie_scan_bus; hw.ops =3D &tegra_pcie_ops; =20 --=20 2.1.0 --7J16OGEJ/mt06A90-- --mhOzvPhkurUs4vA9 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUJSxhAAoJEN0jrNd/PrOhoLsQAMJ5GxCoND9IRjKBHBmrC/51 EfiGjh/v0yQqfkGFBzV41mV+tCThGSuHsefr0h7ItMMzGSclLZNdT2VKt/KaFqem Q6V+CwdSlDiMMLcpCjAGvp4hdDi+0XDCy7Y8jkC2W03El4vSRXMuLEqqwrFdK0gB 05H6NYD2ozSZkLSz6kKZzDriAmV7soM2oCUtQ+lBTeYuz7dHFV0KFUtmka5mK5Hw WRmES6tba2YsjZcBnVOuEkrGOcXmV7rSG/Q4VI45Dcq0xyQIIoMbk5StAhi3htzg zmNTj58VhrHnqJeicxjD9PAwm2Pil1eAb97Rp/jTkGc7h8gdjHPjRiN4D2Hzv+3u POIs9Wnw/B7Nu+cbah6VrwbhkZJ6ONOdO969FwEKVqUAgrYQNOlpb764IfsNqWSd 4SrBJxcX6Rf49cDgpeVdMu2M+y3JrSx8B34Y2Jvrjqfu7+Fqg1oUmaiIraZTw7Mx 2L+r9XOSjoImov5pWFOQK6TQLFAQxg/Jzc3VbQW/Asthgh9J1IdnaawQ1tUmd7X3 2SkPbFifpMXG/q4Kzo7ziNHEChdugUtgjqSedknGrxRhTgYMcoFuvmqg11yv5giF cQ4aiPTi7iwKtIUJ6der5Ypyym8WH6g9McEkXHr8MHTPwy5VwjoOIa5f9h8c0DF3 JVw7pOJIyEgFtmcvn4p1 =YM+j -----END PGP SIGNATURE----- --mhOzvPhkurUs4vA9-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [PATCH v2 00/22] Use MSI chip framework to configure MSI/MSI-X in all platforms Date: Fri, 26 Sep 2014 11:05:38 +0200 Message-ID: <20140926090537.GH31106@ulmo> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <20140925074235.GN12423@ulmo> <20140925144855.GB31157@bart.dudau.co.uk> <20140925164937.GB30382@ulmo> <20140925171612.GC31157@bart.dudau.co.uk> <542505B3.7040208@huawei.com> <20140926085430.GG31106@ulmo> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2000916252416521293==" Return-path: In-Reply-To: <20140926085430.GG31106@ulmo> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Yijing Wang Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org, linux-ia64-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Xinwei Hu , sparclinux-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arch-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-s390-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King , Michael Ellerman , x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Sebastian Ott , Benjamin Herrenschmidt , xen-devel-GuqFBffKawtpuQazS67q72D2FQJk+8+b@public.gmane.org, arnab.basu-KZfg59tc24xl57MIdRCFDg@public.gmane.org, Arnd Bergmann , Chris Metcalf , Bjorn Helgaas , Thomas Gleixner , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Thomas Petazzoni , Liviu Dudau , Tony Luck , Sergei Shtylyov , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ralf Baechle , iommu@lists.l List-Id: linux-arch.vger.kernel.org --===============2000916252416521293== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="mhOzvPhkurUs4vA9" Content-Disposition: inline --mhOzvPhkurUs4vA9 Content-Type: multipart/mixed; boundary="7J16OGEJ/mt06A90" Content-Disposition: inline --7J16OGEJ/mt06A90 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Sep 26, 2014 at 10:54:32AM +0200, Thierry Reding wrote: [...] > At least for Tegra it's trivial to just hook it up in tegra_pcie_scan_bus() > directly (patch attached). Really attached this time. Thierry --7J16OGEJ/mt06A90 Content-Type: text/x-diff; charset=us-ascii Content-Disposition: inline; filename="0001-PCI-tegra-Remove-.add_bus-callback.patch" Content-Transfer-Encoding: quoted-printable =46rom 2cedfcf38cdfe21688d1363659f28e271ce43358 Mon Sep 17 00:00:00 2001 =46rom: Thierry Reding Date: Fri, 26 Sep 2014 10:35:47 +0200 Subject: [PATCH] PCI: tegra: Remove .add_bus() callback The .add_bus() callback is called for every bus and used to associate an MSI chip with each bus. However the PCI core code already propagates the root bus' MSI chip to child busses, so it is enough to associate the MSI chip with the root bus upon creation. Conveniently the Tegra PCIe host bridge driver creates the root bus directly, so the association can be done at the same time. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 3d43874319be..d314e549ac0c 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -694,15 +694,6 @@ static int tegra_pcie_map_irq(const struct pci_dev *pd= ev, u8 slot, u8 pin) return irq; } =20 -static void tegra_pcie_add_bus(struct pci_bus *bus) -{ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - struct tegra_pcie *pcie =3D sys_to_pcie(bus->sysdata); - - bus->msi =3D &pcie->msi.chip; - } -} - static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sy= s) { struct tegra_pcie *pcie =3D sys_to_pcie(sys); @@ -713,6 +704,9 @@ static struct pci_bus *tegra_pcie_scan_bus(int nr, stru= ct pci_sys_data *sys) if (!bus) return NULL; =20 + if (IS_ENABLED(CONFIG_PCI_MSI)) + bus->msi =3D &pcie->msi.chip; + pci_scan_child_bus(bus); =20 return bus; @@ -1885,7 +1879,6 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie) hw.private_data =3D (void **)&pcie; hw.setup =3D tegra_pcie_setup; hw.map_irq =3D tegra_pcie_map_irq; - hw.add_bus =3D tegra_pcie_add_bus; hw.scan =3D tegra_pcie_scan_bus; hw.ops =3D &tegra_pcie_ops; =20 --=20 2.1.0 --7J16OGEJ/mt06A90-- --mhOzvPhkurUs4vA9 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUJSxhAAoJEN0jrNd/PrOhoLsQAMJ5GxCoND9IRjKBHBmrC/51 EfiGjh/v0yQqfkGFBzV41mV+tCThGSuHsefr0h7ItMMzGSclLZNdT2VKt/KaFqem Q6V+CwdSlDiMMLcpCjAGvp4hdDi+0XDCy7Y8jkC2W03El4vSRXMuLEqqwrFdK0gB 05H6NYD2ozSZkLSz6kKZzDriAmV7soM2oCUtQ+lBTeYuz7dHFV0KFUtmka5mK5Hw WRmES6tba2YsjZcBnVOuEkrGOcXmV7rSG/Q4VI45Dcq0xyQIIoMbk5StAhi3htzg zmNTj58VhrHnqJeicxjD9PAwm2Pil1eAb97Rp/jTkGc7h8gdjHPjRiN4D2Hzv+3u POIs9Wnw/B7Nu+cbah6VrwbhkZJ6ONOdO969FwEKVqUAgrYQNOlpb764IfsNqWSd 4SrBJxcX6Rf49cDgpeVdMu2M+y3JrSx8B34Y2Jvrjqfu7+Fqg1oUmaiIraZTw7Mx 2L+r9XOSjoImov5pWFOQK6TQLFAQxg/Jzc3VbQW/Asthgh9J1IdnaawQ1tUmd7X3 2SkPbFifpMXG/q4Kzo7ziNHEChdugUtgjqSedknGrxRhTgYMcoFuvmqg11yv5giF cQ4aiPTi7iwKtIUJ6der5Ypyym8WH6g9McEkXHr8MHTPwy5VwjoOIa5f9h8c0DF3 JVw7pOJIyEgFtmcvn4p1 =YM+j -----END PGP SIGNATURE----- --mhOzvPhkurUs4vA9-- --===============2000916252416521293== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline --===============2000916252416521293==-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Fri, 26 Sep 2014 09:05:38 +0000 Subject: Re: [PATCH v2 00/22] Use MSI chip framework to configure MSI/MSI-X in all platforms Message-Id: <20140926090537.GH31106@ulmo> MIME-Version: 1 Content-Type: multipart/mixed; boundary="mhOzvPhkurUs4vA9" List-Id: References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <20140925074235.GN12423@ulmo> <20140925144855.GB31157@bart.dudau.co.uk> <20140925164937.GB30382@ulmo> <20140925171612.GC31157@bart.dudau.co.uk> <542505B3.7040208@huawei.com> <20140926085430.GG31106@ulmo> In-Reply-To: <20140926085430.GG31106@ulmo> To: Yijing Wang Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org, linux-ia64-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Xinwei Hu , sparclinux-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arch-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-s390-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King , Michael Ellerman , x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Sebastian Ott , Benjamin Herrenschmidt , xen-devel-GuqFBffKawtpuQazS67q72D2FQJk+8+b@public.gmane.org, arnab.basu-KZfg59tc24xl57MIdRCFDg@public.gmane.org, Arnd Bergmann , Chris Metcalf , Bjorn Helgaas , Thomas Gleixner , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Thomas Petazzoni , Liviu Dudau , Tony Luck , Sergei Shtylyov , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ralf Baechle , iommu@lists.l --mhOzvPhkurUs4vA9 Content-Type: multipart/mixed; boundary="7J16OGEJ/mt06A90" Content-Disposition: inline --7J16OGEJ/mt06A90 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Sep 26, 2014 at 10:54:32AM +0200, Thierry Reding wrote: [...] > At least for Tegra it's trivial to just hook it up in tegra_pcie_scan_bus() > directly (patch attached). Really attached this time. Thierry --7J16OGEJ/mt06A90 Content-Type: text/x-diff; charset=us-ascii Content-Disposition: inline; filename="0001-PCI-tegra-Remove-.add_bus-callback.patch" Content-Transfer-Encoding: quoted-printable =46rom 2cedfcf38cdfe21688d1363659f28e271ce43358 Mon Sep 17 00:00:00 2001 =46rom: Thierry Reding Date: Fri, 26 Sep 2014 10:35:47 +0200 Subject: [PATCH] PCI: tegra: Remove .add_bus() callback The .add_bus() callback is called for every bus and used to associate an MSI chip with each bus. However the PCI core code already propagates the root bus' MSI chip to child busses, so it is enough to associate the MSI chip with the root bus upon creation. Conveniently the Tegra PCIe host bridge driver creates the root bus directly, so the association can be done at the same time. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 3d43874319be..d314e549ac0c 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -694,15 +694,6 @@ static int tegra_pcie_map_irq(const struct pci_dev *pd= ev, u8 slot, u8 pin) return irq; } =20 -static void tegra_pcie_add_bus(struct pci_bus *bus) -{ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - struct tegra_pcie *pcie =3D sys_to_pcie(bus->sysdata); - - bus->msi =3D &pcie->msi.chip; - } -} - static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sy= s) { struct tegra_pcie *pcie =3D sys_to_pcie(sys); @@ -713,6 +704,9 @@ static struct pci_bus *tegra_pcie_scan_bus(int nr, stru= ct pci_sys_data *sys) if (!bus) return NULL; =20 + if (IS_ENABLED(CONFIG_PCI_MSI)) + bus->msi =3D &pcie->msi.chip; + pci_scan_child_bus(bus); =20 return bus; @@ -1885,7 +1879,6 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie) hw.private_data =3D (void **)&pcie; hw.setup =3D tegra_pcie_setup; hw.map_irq =3D tegra_pcie_map_irq; - hw.add_bus =3D tegra_pcie_add_bus; hw.scan =3D tegra_pcie_scan_bus; hw.ops =3D &tegra_pcie_ops; =20 --=20 2.1.0 --7J16OGEJ/mt06A90-- --mhOzvPhkurUs4vA9 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUJSxhAAoJEN0jrNd/PrOhoLsQAMJ5GxCoND9IRjKBHBmrC/51 EfiGjh/v0yQqfkGFBzV41mV+tCThGSuHsefr0h7ItMMzGSclLZNdT2VKt/KaFqem Q6V+CwdSlDiMMLcpCjAGvp4hdDi+0XDCy7Y8jkC2W03El4vSRXMuLEqqwrFdK0gB 05H6NYD2ozSZkLSz6kKZzDriAmV7soM2oCUtQ+lBTeYuz7dHFV0KFUtmka5mK5Hw WRmES6tba2YsjZcBnVOuEkrGOcXmV7rSG/Q4VI45Dcq0xyQIIoMbk5StAhi3htzg zmNTj58VhrHnqJeicxjD9PAwm2Pil1eAb97Rp/jTkGc7h8gdjHPjRiN4D2Hzv+3u POIs9Wnw/B7Nu+cbah6VrwbhkZJ6ONOdO969FwEKVqUAgrYQNOlpb764IfsNqWSd 4SrBJxcX6Rf49cDgpeVdMu2M+y3JrSx8B34Y2Jvrjqfu7+Fqg1oUmaiIraZTw7Mx 2L+r9XOSjoImov5pWFOQK6TQLFAQxg/Jzc3VbQW/Asthgh9J1IdnaawQ1tUmd7X3 2SkPbFifpMXG/q4Kzo7ziNHEChdugUtgjqSedknGrxRhTgYMcoFuvmqg11yv5giF cQ4aiPTi7iwKtIUJ6der5Ypyym8WH6g9McEkXHr8MHTPwy5VwjoOIa5f9h8c0DF3 JVw7pOJIyEgFtmcvn4p1 =YM+j -----END PGP SIGNATURE----- --mhOzvPhkurUs4vA9-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wg0-x234.google.com (mail-wg0-x234.google.com [IPv6:2a00:1450:400c:c00::234]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id D45DB1A00FA for ; Fri, 26 Sep 2014 19:05:44 +1000 (EST) Received: by mail-wg0-f52.google.com with SMTP id n12so7503133wgh.23 for ; Fri, 26 Sep 2014 02:05:40 -0700 (PDT) Date: Fri, 26 Sep 2014 11:05:38 +0200 From: Thierry Reding To: Yijing Wang Subject: Re: [PATCH v2 00/22] Use MSI chip framework to configure MSI/MSI-X in all platforms Message-ID: <20140926090537.GH31106@ulmo> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <20140925074235.GN12423@ulmo> <20140925144855.GB31157@bart.dudau.co.uk> <20140925164937.GB30382@ulmo> <20140925171612.GC31157@bart.dudau.co.uk> <542505B3.7040208@huawei.com> <20140926085430.GG31106@ulmo> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="mhOzvPhkurUs4vA9" In-Reply-To: <20140926085430.GG31106@ulmo> Cc: linux-mips@linux-mips.org, linux-ia64@vger.kernel.org, linux-pci@vger.kernel.org, Xinwei Hu , sparclinux@vger.kernel.org, linux-arch@vger.kernel.org, linux-s390@vger.kernel.org, Russell King , Joerg Roedel , x86@kernel.org, Sebastian Ott , Bharat.Bhushan@freescale.com, xen-devel@lists.xenproject.org, arnab.basu@freescale.com, Arnd Bergmann , Konrad Rzeszutek Wilk , Chris Metcalf , Bjorn Helgaas , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Liviu Dudau , Tony Luck , Sergei Shtylyov , linux-kernel@vger.kernel.org, Ralf Baechle , iommu@lists.linux-foundation.org, David Vrabel , Wuyun , linuxppc-dev@lists.ozlabs.org, "David S. Miller" , Lucas Stach List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , --mhOzvPhkurUs4vA9 Content-Type: multipart/mixed; boundary="7J16OGEJ/mt06A90" Content-Disposition: inline --7J16OGEJ/mt06A90 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Sep 26, 2014 at 10:54:32AM +0200, Thierry Reding wrote: [...] > At least for Tegra it's trivial to just hook it up in tegra_pcie_scan_bus() > directly (patch attached). Really attached this time. Thierry --7J16OGEJ/mt06A90 Content-Type: text/x-diff; charset=us-ascii Content-Disposition: inline; filename="0001-PCI-tegra-Remove-.add_bus-callback.patch" Content-Transfer-Encoding: quoted-printable =46rom 2cedfcf38cdfe21688d1363659f28e271ce43358 Mon Sep 17 00:00:00 2001 =46rom: Thierry Reding Date: Fri, 26 Sep 2014 10:35:47 +0200 Subject: [PATCH] PCI: tegra: Remove .add_bus() callback The .add_bus() callback is called for every bus and used to associate an MSI chip with each bus. However the PCI core code already propagates the root bus' MSI chip to child busses, so it is enough to associate the MSI chip with the root bus upon creation. Conveniently the Tegra PCIe host bridge driver creates the root bus directly, so the association can be done at the same time. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 3d43874319be..d314e549ac0c 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -694,15 +694,6 @@ static int tegra_pcie_map_irq(const struct pci_dev *pd= ev, u8 slot, u8 pin) return irq; } =20 -static void tegra_pcie_add_bus(struct pci_bus *bus) -{ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - struct tegra_pcie *pcie =3D sys_to_pcie(bus->sysdata); - - bus->msi =3D &pcie->msi.chip; - } -} - static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sy= s) { struct tegra_pcie *pcie =3D sys_to_pcie(sys); @@ -713,6 +704,9 @@ static struct pci_bus *tegra_pcie_scan_bus(int nr, stru= ct pci_sys_data *sys) if (!bus) return NULL; =20 + if (IS_ENABLED(CONFIG_PCI_MSI)) + bus->msi =3D &pcie->msi.chip; + pci_scan_child_bus(bus); =20 return bus; @@ -1885,7 +1879,6 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie) hw.private_data =3D (void **)&pcie; hw.setup =3D tegra_pcie_setup; hw.map_irq =3D tegra_pcie_map_irq; - hw.add_bus =3D tegra_pcie_add_bus; hw.scan =3D tegra_pcie_scan_bus; hw.ops =3D &tegra_pcie_ops; =20 --=20 2.1.0 --7J16OGEJ/mt06A90-- --mhOzvPhkurUs4vA9 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUJSxhAAoJEN0jrNd/PrOhoLsQAMJ5GxCoND9IRjKBHBmrC/51 EfiGjh/v0yQqfkGFBzV41mV+tCThGSuHsefr0h7ItMMzGSclLZNdT2VKt/KaFqem Q6V+CwdSlDiMMLcpCjAGvp4hdDi+0XDCy7Y8jkC2W03El4vSRXMuLEqqwrFdK0gB 05H6NYD2ozSZkLSz6kKZzDriAmV7soM2oCUtQ+lBTeYuz7dHFV0KFUtmka5mK5Hw WRmES6tba2YsjZcBnVOuEkrGOcXmV7rSG/Q4VI45Dcq0xyQIIoMbk5StAhi3htzg zmNTj58VhrHnqJeicxjD9PAwm2Pil1eAb97Rp/jTkGc7h8gdjHPjRiN4D2Hzv+3u POIs9Wnw/B7Nu+cbah6VrwbhkZJ6ONOdO969FwEKVqUAgrYQNOlpb764IfsNqWSd 4SrBJxcX6Rf49cDgpeVdMu2M+y3JrSx8B34Y2Jvrjqfu7+Fqg1oUmaiIraZTw7Mx 2L+r9XOSjoImov5pWFOQK6TQLFAQxg/Jzc3VbQW/Asthgh9J1IdnaawQ1tUmd7X3 2SkPbFifpMXG/q4Kzo7ziNHEChdugUtgjqSedknGrxRhTgYMcoFuvmqg11yv5giF cQ4aiPTi7iwKtIUJ6der5Ypyym8WH6g9McEkXHr8MHTPwy5VwjoOIa5f9h8c0DF3 JVw7pOJIyEgFtmcvn4p1 =YM+j -----END PGP SIGNATURE----- --mhOzvPhkurUs4vA9-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: thierry.reding@gmail.com (Thierry Reding) Date: Fri, 26 Sep 2014 11:05:38 +0200 Subject: [PATCH v2 00/22] Use MSI chip framework to configure MSI/MSI-X in all platforms In-Reply-To: <20140926085430.GG31106@ulmo> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <20140925074235.GN12423@ulmo> <20140925144855.GB31157@bart.dudau.co.uk> <20140925164937.GB30382@ulmo> <20140925171612.GC31157@bart.dudau.co.uk> <542505B3.7040208@huawei.com> <20140926085430.GG31106@ulmo> Message-ID: <20140926090537.GH31106@ulmo> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Sep 26, 2014 at 10:54:32AM +0200, Thierry Reding wrote: [...] > At least for Tegra it's trivial to just hook it up in tegra_pcie_scan_bus() > directly (patch attached). Really attached this time. Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-PCI-tegra-Remove-.add_bus-callback.patch Type: text/x-diff Size: 1887 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 819 bytes Desc: not available URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Fri, 26 Sep 2014 09:05:38 +0000 Subject: Re: [PATCH v2 00/22] Use MSI chip framework to configure MSI/MSI-X in all platforms Message-Id: <20140926090537.GH31106@ulmo> MIME-Version: 1 Content-Type: multipart/mixed; boundary="mhOzvPhkurUs4vA9" List-Id: References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <20140925074235.GN12423@ulmo> <20140925144855.GB31157@bart.dudau.co.uk> <20140925164937.GB30382@ulmo> <20140925171612.GC31157@bart.dudau.co.uk> <542505B3.7040208@huawei.com> <20140926085430.GG31106@ulmo> In-Reply-To: <20140926085430.GG31106@ulmo> To: Yijing Wang Cc: Liviu Dudau , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Xinwei Hu , Wuyun , linux-arm-kernel@lists.infradead.org, Russell King , linux-arch@vger.kernel.org, arnab.basu@freescale.com, Bharat.Bhushan@freescale.com, x86@kernel.org, Arnd Bergmann , Thomas Gleixner , Konrad Rzeszutek Wilk , xen-devel@lists.xenproject.org, Joerg Roedel , iommu@lists.linux-foundation.org, linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, Sebastian Ott , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , Sergei Shtylyov , Michael Ellerman , Thomas Petazzoni --mhOzvPhkurUs4vA9 Content-Type: multipart/mixed; boundary="7J16OGEJ/mt06A90" Content-Disposition: inline --7J16OGEJ/mt06A90 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Sep 26, 2014 at 10:54:32AM +0200, Thierry Reding wrote: [...] > At least for Tegra it's trivial to just hook it up in tegra_pcie_scan_bus() > directly (patch attached). Really attached this time. Thierry --7J16OGEJ/mt06A90 Content-Type: text/x-diff; charset=us-ascii Content-Disposition: inline; filename="0001-PCI-tegra-Remove-.add_bus-callback.patch" Content-Transfer-Encoding: quoted-printable =46rom 2cedfcf38cdfe21688d1363659f28e271ce43358 Mon Sep 17 00:00:00 2001 =46rom: Thierry Reding Date: Fri, 26 Sep 2014 10:35:47 +0200 Subject: [PATCH] PCI: tegra: Remove .add_bus() callback The .add_bus() callback is called for every bus and used to associate an MSI chip with each bus. However the PCI core code already propagates the root bus' MSI chip to child busses, so it is enough to associate the MSI chip with the root bus upon creation. Conveniently the Tegra PCIe host bridge driver creates the root bus directly, so the association can be done at the same time. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 3d43874319be..d314e549ac0c 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -694,15 +694,6 @@ static int tegra_pcie_map_irq(const struct pci_dev *pd= ev, u8 slot, u8 pin) return irq; } =20 -static void tegra_pcie_add_bus(struct pci_bus *bus) -{ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - struct tegra_pcie *pcie =3D sys_to_pcie(bus->sysdata); - - bus->msi =3D &pcie->msi.chip; - } -} - static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sy= s) { struct tegra_pcie *pcie =3D sys_to_pcie(sys); @@ -713,6 +704,9 @@ static struct pci_bus *tegra_pcie_scan_bus(int nr, stru= ct pci_sys_data *sys) if (!bus) return NULL; =20 + if (IS_ENABLED(CONFIG_PCI_MSI)) + bus->msi =3D &pcie->msi.chip; + pci_scan_child_bus(bus); =20 return bus; @@ -1885,7 +1879,6 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie) hw.private_data =3D (void **)&pcie; hw.setup =3D tegra_pcie_setup; hw.map_irq =3D tegra_pcie_map_irq; - hw.add_bus =3D tegra_pcie_add_bus; hw.scan =3D tegra_pcie_scan_bus; hw.ops =3D &tegra_pcie_ops; =20 --=20 2.1.0 --7J16OGEJ/mt06A90-- --mhOzvPhkurUs4vA9 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUJSxhAAoJEN0jrNd/PrOhoLsQAMJ5GxCoND9IRjKBHBmrC/51 EfiGjh/v0yQqfkGFBzV41mV+tCThGSuHsefr0h7ItMMzGSclLZNdT2VKt/KaFqem Q6V+CwdSlDiMMLcpCjAGvp4hdDi+0XDCy7Y8jkC2W03El4vSRXMuLEqqwrFdK0gB 05H6NYD2ozSZkLSz6kKZzDriAmV7soM2oCUtQ+lBTeYuz7dHFV0KFUtmka5mK5Hw WRmES6tba2YsjZcBnVOuEkrGOcXmV7rSG/Q4VI45Dcq0xyQIIoMbk5StAhi3htzg zmNTj58VhrHnqJeicxjD9PAwm2Pil1eAb97Rp/jTkGc7h8gdjHPjRiN4D2Hzv+3u POIs9Wnw/B7Nu+cbah6VrwbhkZJ6ONOdO969FwEKVqUAgrYQNOlpb764IfsNqWSd 4SrBJxcX6Rf49cDgpeVdMu2M+y3JrSx8B34Y2Jvrjqfu7+Fqg1oUmaiIraZTw7Mx 2L+r9XOSjoImov5pWFOQK6TQLFAQxg/Jzc3VbQW/Asthgh9J1IdnaawQ1tUmd7X3 2SkPbFifpMXG/q4Kzo7ziNHEChdugUtgjqSedknGrxRhTgYMcoFuvmqg11yv5giF cQ4aiPTi7iwKtIUJ6der5Ypyym8WH6g9McEkXHr8MHTPwy5VwjoOIa5f9h8c0DF3 JVw7pOJIyEgFtmcvn4p1 =YM+j -----END PGP SIGNATURE----- --mhOzvPhkurUs4vA9--